DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority based on an application filed in Japan on January 10, 2020.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “an interface between the semiconductor layer and the gate electrode.” It is unclear whether the interface is a separate and distinct layer that is between the semiconductor layer and the gate electrode, or if the interface is included as part of the semiconductor layer or the gate electrode. Depending on the interpretation of “interface,” this could conflict with the prior limitation of claim 1 which recites “a gate electrode that is arranged directly or via another layer on the semiconductor layer”. If the interface is a separate and distinct layer that is between the semiconductor layer and the gate electrode, the gate electrode cannot be arranged directly on the semiconductor layer. For the purposes of this action, the limitation of claim 1, which recites “an interface between the semiconductor layer and the gate electrode,” will be interpreted as a separate and distinct layer apart from the semiconductor layer and gate electrode.
Claim 6 recites the limitation "wherein the first surface is an m-plane". There is insufficient antecedent basis for this limitation in the claim. Claim 1, in which claim 6 is dependent, contains no earlier recitation or limitation of a “first surface”. Additionally, claim 6 does not specify the surface of which layer, making the limitation unclear. For the purposes of this action, the limitation of claim 6 which recites “the first surface” will be interpreted using the limitation of claim 2 which recites “an upper surface of the semiconductor layer”.
Appropriate correction is required.
Note by the Examiner
For clarity, the references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 and/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hitora et al. (US 2015/0325659 A1) in view of Kanno et al. (US 2022/0140084 A1). Tokuda et al. (US 2018/0061952 A1), Yoshida et al. (US 2017/0040241 A1), Wu et al. (2018/0047826 A1) are herein used as evidentiary references.
Regarding claim 1, Hitora discloses a semiconductor device ([0001] “the present invention relates to […] a semiconductor device”) comprising (Fig. 7);
at least a semiconductor layer (elements 131a, 131b, and 131c; [0075] "n- type semiconductor layer 131a, n+ type semiconductor layers 131b and 131c"); and
a gate electrode (element 135a, [0075] “gate electrode 135a”) that is arranged directly or via another layer on the semiconductor layer (see Fig. 7 in which gate electrode 135a is disposed on a gate insulating film 134 on the semiconductor layer 131a),
the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer ([0075] "the n+ type semiconductor layers are embedded in the n- type semiconductor layer, so that that the current can be passed more favorably.”) at least in a first direction that is along (“along” is interpreted as a horizontal direction in parallel with the long side of the interface) with an interface (element 134 of Fig. 7, [0075] “gate insulating film 134”) between the semiconductor layer and the gate electrode (see Fig. 7, wherein the gate insulating film 134 is between the semiconductor layer 131a and the gate electrode 135a),
the semiconductor layer having a corundum structure ([0038] "the corundum-structured oxide semiconductor"),
Hitora fails to explicitly disclose a direction of a c-axis in the semiconductor layer being the first direction.
Kanno discloses a semiconductor film layer with a surface that is an m-plane ([0023] “an oxide film including […] a principal surface that is an m-plane” [0037] “preferable that the oxide film be a semiconductor film”). See evidentiary reference Wu ([0004] “crystal planes of {1010} […] (also referred to as an m-plane) are nonpolar”, wherein “nonpolar surfaces [are] parallel to c-axis”). As the semiconductor oxide film of Kanno is an m-plane surface, the direction on its surface runs parallel to the direction of the c-axis, making the direction of the c-axis run horizontally.
The semiconductor layer as taught by Kanno is incorporated as the semiconductor layer of Hitora (Hitora: elements 131a-c; [0075] "n- type semiconductor layer 131a, n+ type semiconductor layers 131b and 131c"), wherein the combination discloses a direction of a c-axis in the semiconductor layer being the first direction.
Kanno and Hitora are analogous art because they are directed to crystalline oxide semiconductor film layers, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hitora with the specified features of Kanno because they are from the same field of endeavor.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Kanno with Hitora, because the combination allows for enhanced electrical characteristics (see evidentiary reference Tokuda: [0030] “The crystalline oxide semiconductor film may include a principal plane that is an m-plane, which may be more enhanced in electrical characteristics than the crystalline oxide semiconductor [that is an] a-plane.”). The combination is simple substitution of one known element for another to obtain predictable results, i.e., one known crystalline oxide semiconductor layer for another to obtain predictable results; see MPEP 2143(I)(B).
Regarding claim 2, the combination of Hitora and Kanno discloses the semiconductor device according to claim 1, wherein the first direction is a direction along (“along” is interpreted as a horizontal direction in parallel with the long side of the interface) with an upper surface of the semiconductor layer (Kanno: [0023] “an oxide film including […] a principal surface that is an m-plane”; evidentiary reference Wu ([0004] “crystal planes of {1010} […] (also referred to as an m-plane) are nonpolar”, wherein “nonpolar surfaces [are] parallel to c-axis”. Since the oxide film is an m-plane, which is a non-polar surface parallel to the c-axis, the first direction is a direction that is along the upper surface of the semiconductor layer.).
Regarding claim 3, Hitora discloses the semiconductor device according to claim 1, wherein the semiconductor layer contains a metal oxide including at least one metal selected from gallium, indium, rhodium, and iridium ([0036] “"the oxide semiconductor contains indium and/or gallium as a major component").
Regarding claim 4, Hitora discloses the semiconductor device according to claim 1, wherein the semiconductor layer contains a metal oxide including at least gallium as a major component ([0036] “the oxide semiconductor contains indium and/or gallium as a major component").
Regarding claim 5, Hitora discloses the semiconductor device according to claim 1, wherein the semiconductor layer has a carrier concentration of equal to or less than 1 x 1019/cm3 ([0040] "In the present invention, when forming an n−-type semiconductor layer, the concentration of germanium, silicon, titanium, zirconium, vanadium, or niobium in the crystalline oxide semiconductor thin film is preferably about 1×1013 to 1×1017/cm3, more preferably about 1×1015 to 1×1017/cm3.")
Regarding claim 6, the combination of Hitora and Kanno discloses the semiconductor device according to claim 1, wherein the first surface is an m-plane (Kanno: [0023] “an oxide film including […] a principal surface that is an m-plane” [0037] “preferable that the oxide film be a semiconductor film”).
Regarding claim 7, Hitora discloses the semiconductor device according to claim 1, wherein the semiconductor device is a power device ([0050] “the present invention is useful for various types of semiconductors, particularly for power devices.”).
Regarding claim 8, Hitora discloses the semiconductor device according to claim 7,
Hitora fails to explicitly disclose wherein the semiconductor device is a power module, an inverter, or a converter.
Kanno discloses an inverter circuit using MOSFETs of the same arrangement (Kanno: [0059] “an inverter configured with MOSFET A to D”).
The inverter circuit using a semiconductor device as taught by Kanno is incorporated with the semiconductor device of Hitora, wherein the combination discloses wherein the semiconductor device is a power module, an inverter, or a converter.
Kanno and Hitora are analogous art because they are directed to crystalline oxide semiconductor film layers, and one of ordinary skill in the art would have had a reasonable expectation of success to incorporate the teachings of Kanno with Hitora, because they are from the same field of endeavor and because the combination allows for the creation of an inverter that may be used in a power supply device (Kanno: [0059]).
Regarding claim 9, Hitora discloses the semiconductor device according to claim 7,
Hitora fails to explicitly disclose wherein the semiconductor device is a power card.
Kanno discloses a power card structure that includes non-descript semiconductor devices (Kanno: [0060] “Fig. 14 is double sided cooling-type power card 201”).
The power card structure comprising of a semiconductor device as taught by Kanno is incorporated with the semiconductor device of Hitora, wherein the combination discloses wherein the semiconductor device is a power card.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Kanno with Hitora, because the combination allows for the usage of multiple semiconductor devices in conjunction without loss of performance caused by overheating due to the coolers and heat dissipation elements of power card structures (see evidentiary reference Yoshida [0010] “Techniques disclosed in this specification […] ensures cooling performance for the power card;” [0029] “Each of the semiconductor elements generates a large amount of heat.”).
Regarding claim 10, the combination of Hitora and Kanno discloses the semiconductor device according to claim 9, further comprising (see Kanno Fig. 14):
a cooler (elements 202; [0060] “refrigerant tube 202”) and an insulating member (elements 208; [0060] “insulating plate 208”), the cooler being provided on each of both sides of the semiconductor layer across at least the insulating member ([0060] “the coolers are provided on opposite sides of the semiconductor layers via at least the insulating members” see Fig. 14 wherein the refrigerant tubes 202 are provided on both sides of the semiconductor layer across the insulating plates 208).
Regarding claim 11, the combination of Hitora and Kanno discloses the semiconductor device according to claim 10,
wherein a heat dissipation layer (elements 302b and 303b; [0060] “metal heat transfer plates 302b” “metal heat transfer plates 303b”) is provided on each of the both sides of the semiconductor layer (see Fig. 17 wherein the heat transfer plates 302b and 303b are provided on both sides of the semiconductor element 301a), and
the cooler is provided external to the heat dissipation layer across at least the insulating member (see Fig. 14 wherein the refrigerant tubes 202 are provided on the outermost region, externally to the heat transfer plates 302b/303b and the insulating plates 208).
Regarding claim 12, the combination of Hitora and Kanno discloses a semiconductor system (Kanno: [0036] “a semiconductor system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to structure 11 above.”; see Fig. 12. Additionally, structure 11 points a semiconductor device “including at least a semiconductor layer, an insulator film, or an electrically conductive layer, and an electrode” [0035]) comprising a semiconductor device, the semiconductor device being the semiconductor device according to claim 1 (Hitora: [0075] “The MOSFET in FIG. 7” wherein the MOSFET of Fig. 7 includes a semiconductor layer ([0075] “semiconductor layer 131a”), an insulator film ([0075] “a gate insulating film 134”), and an electrode ([0075] “a gate electrode 135a”)).
Conclusion
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/D.N./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818