Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This is a Final Office Action of the instant application 17/861,582
(hereinafter the ‘582 application) filed on 7/11/2022, responsive to the Amendment filed 3/2/2026. The ‘582 application claims priority to KR 10-2021-0123364 which has an filing date of 9/15/2021. A certified copy has been received and placed on the record.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Specifically, the Applicant adds the following limitations to the independent claims while providing only paragraphs 3-5, 59, 69, 80, and 102, for support without any detail of how these paragraphs support the claim amendments. The Examiner can’t find any support in the cited paragraphs nor the rest of the specification for the amendments.
Amendments:
“the virtual target representative of both measurable and non-measurable electrical operating regions of a first semiconductor device of the current generation, and the virtual target being free of data measurement associated with the first semiconductor device of the current generation”
“verifying the virtual target by comparing the virtual target with a real target, the real target being measured from a second semiconductor device of the current generation”
Here the only reference to both measurable and non-measurable operating regions is in the background noting that prior system relied on a combination of both to evaluate target models, furthermore the specification does not make clear what it is to be “representative of both”. Additionally, the specification does not describe a virtual target being “free of data measurement”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, the claims note that the “virtual target” is “representative of” a measurable but yet “free of data measurement”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lei et al., U.S. Publication No. 2019/0385047, hereinafter Lei, Kim, U.S. Patent No. 10,902,173, and David, U.S. Publication No. 2017/0109646.
With regard to claim 1, which teaches a method for generating a model using a virtual target, the method comprising: performing machine learning based on previous generation data stored in a database to generate the virtual target of a current generation; the virtual target representative of both measurable and non-measurable electrical operating regions of a first semiconductor device of the current generation, and the virtual target being free of data measurement associated with the first semiconductor device of the current generation; extracting parameters related to the virtual target, and determining values of the extracted parameters based on the virtual target to generate the model; and verifying the virtual target by comparing the virtual target with a real target, the real target being measured from a second semiconductor device of the current generation, Lei teaches using machine learning and Artificial Neural Networks (ANN) to generate device models via virtual model target characteristics based on a prior generations data (see Lei 31-32, 46, 50, and 53 and figure 10). Here the system targets a transformation of the select characteristic (in this case ‘drain current’) and evaluates the varied weights of system characteristics (inputs) that weigh on the select characteristic. The inputs are applied to the deep neural network that then evaluates results as fitting target data and subsequently adapts the weights (non-measured data, not derived from measurements of initial semiconductor) in updated evaluations (see paragraphs 37, 41, and 46). Lei further teaches processor and pre-processor 40 for use in implementing the simulation (see paragraphs 33 and claim 16).
Kim teaches a similar system for transistor design, but further lays out how individual parameters contribute to the overall target characteristic traits. Kim teaches ‘process variables’ (PV1, PV2, etc.) that denote physical / structural characteristics of the semiconductor device, for example length of a gate line, width of an active area, channel length, device width, etc. (see 8: 4-20 and figure 3). Model interface 120 may then determine a set of parameters associated with each of the combinations of process variables, for example a parameter set associated with the value of process variable PV1 and the value of the second process variable PV2 (see 10:45-61). Next (in step S213) the “model interface 120 may predict the electrical characteristics and/or physical characteristics of the semiconductor device corresponding to the received value of the fist process variable PV1 and the value of the second process variable PV2 based on the determined model parameters and may output the characteristic data DATA_C” (see 10:62-67). The characteristic parameters all being stored in storage device 17 with results also being stored therein (see 6:23-34 and figure 2). Kim further evaluates targets against ‘extracted parameters’ and ‘internal conditions’ of a semiconductor device, while further verifying the accuracy by comparing the targets with real measurements (see 13:5-28).
It would be obvious to one of ordinary skill in the art at the time of the invention to use the interrelations of transistor properties outlined in Kim in a transistor design system as described in Lei, as the electrical and physical characteristics of transistors interrelate the same way regardless of the design system utilized. Both of the disclosed systems further operate in the same art space.
While Lei teaches transforming targets in a system using Neural Networks to get more accurate models it is not explicit about how these transformations occur. David teaches a similar system for using machine learning in semiconductor manufacturing, but is further explicit about using machine learning to generate a target. David teaches performing machine learning on training data to generate a ‘yield prediction’ then further teaches setting the ‘yield as the target’, ‘identifying parameters’, ‘train[ing an] algorithm’ and ‘produc[ing] a model’ (see paragraphs 144-151 and figures 11 and 12). David teaches an iterative process where “outputs can be used as input” in the machine learning algorithms utilized in David to further adapt the simulation and better model semiconductors (see paragraphs 96-98). Here data ‘from prior production runs can be used to create a model for a target parameter’ (see paragraph 29). In this manner, the virtual target is generated based machine learning initially fed with data from the current generation, but generating new iterations through subsequent passes, each leading to improved targets. David specifically describes using ‘metrology’ data, measured data and data derived without having to measure, in machine learning algorithms to arrive at virtual targets (see paragraphs 45-50).
It would be obvious to one of ordinary skill in the art at the time of the invention to use the targets created via machine learning as done in David in the systems of Lei and Kim as this enables better accuracy of model results. Lei further describes the benefits of transforming targets.
With regard to claim 2, which further teaches wherein the virtual target includes a first virtual target of a first transistor having a first channel length and a first channel width, and a second virtual target of a second transistor having a second channel length different from the first channel length and the first channel width, and the model includes a first transistor model generated on the basis of the first virtual target and a second transistor model generated on the basis of the second virtual target, Lei discloses use of transistor channel length and transistor channel width as features of a model that weigh into the resultant measured target characteristic (see paragraphs 32 and 43).
Kim further teaches evaluating multiple different combinations of channel length and channel width generating models of each and evaluating the parameters the weigh in to the efficiency of each configuration (see 8:4-20, 14:7-41, and figure 7).
With regard to claim 3, which further teaches wherein the generating the virtual target includes a first verification operation of comparing a real target, which is measured from a third transistor having the first channel length and the first channel width, with the first virtual target, Lei teaches evaluation of virtual target configuration by a comparison to a real target data, and using this evaluation to adapt future weightings (see paragraphs 7, 8, 37, 41, and 46).
With regard to claim 4, which further teaches wherein the generating the virtual target further includes a second verification operation of verifying a trend of the first virtual target and the second virtual target, Lei teaches utilizing trends to enable modeling to converge on a target (see paragraph 52).
With regard to claim 5, which further teaches wherein the virtual target further includes a third virtual target of a third transistor which has a third channel length different from the second channel length and a second channel width different from the first channel width, and the model further includes a third transistor model generated on the basis of the third virtual target, Lei discloses use of transistor channel length and transistor channel width as features of a model that weigh into the resultant measured target characteristic (see paragraphs 32 and 43).
Kim further teaches evaluating multiple different combinations of channel length and channel width generating models of each and evaluating the parameters the weigh in to the efficiency of each configuration (see 8:4-20, 14:7-41, and figure 7).
With regard to claim 6, which further teaches wherein the virtual target includes at least one of a threshold voltage target, an off-current target, a linear region current target, a middle region current target, a saturation region current target, and a drive temperature target of a transistor, Lei teaches evaluation threshold voltages (paragraph 14), current targets (paragraph 12-15), temperature targets (see paragraphs 12-15). Kim teaches evaluation of threshold voltages (7:32-44), threshold currents (6:3-8 and 120:54-59), and drive temperature (see 8:4-16).
With regard to claim 7, which further teaches wherein the generating the virtual target includes generating all virtual targets on given channel lengths and given channel widths, Kim further teaches evaluating multiple different combinations of channel length and channel width, generating models of each, and evaluating the parameters that weigh in to the efficiency of each configuration (see 8:4-20, 14:7-41, and figure 7).
With regard to claim 8, which teaches a system configured to generate a model using a virtual target comprising: a database; a processor; and a virtual target generator configured to generate the virtual target of a transistor using the processor, wherein the virtual target generator is configured to perform machine learning based on previous generation data stored in the database and is configured to generate a virtual target of a current generation, Lei teaches using machine learning and Artificial Neural Networks (ANN) to generate virtual model characteristics based on a prior generations data (see Lei 31-32, 46, 50, and 53 and figure 10). Here the system targets a transformation of the select characteristic (in this case ‘drain current’) and evaluates the varied weights of system characteristics (inputs) that weigh on the select characteristic. The inputs are applied to the deep neural network that then evaluates result as fitting target data and subsequently adapts the weights (non-measured data, not derived from measurements of initial semiconductor) in updated evaluations (see paragraphs 37, 41, and 46). Lei further teaches processor and pre-processor 40 for use in implementing the simulation (see paragraphs 33 and claim 16).
Kim teaches a similar system for transistor design, but further lays out how individual parameters contribute to the overall target characteristic traits. Kim teaches ‘process variables’ (PV1, PV2, etc.) that denote physical / structural characteristics of the semiconductor device, for example length of a gate line, width of an active area, channel length, device width, etc. (see 8: 4-20 and figure 3). Model interface 120 may then determine a set of parameters associated with each of the combinations of process variables, for example a parameter set associated with the value of process variable PV1 and the value of the second process variable PV2 (see 10:45-61). Next (in step S213) the “model interface 120 may predict the electrical characteristics and/or physical characteristics of the semiconductor device corresponding to the received value of the fist process variable PV1 and the value of the second process variable PV2 based on the determined model parameters and may output the characteristic data DATA_C” (see 10:62-67). The characteristic parameters all being stored in storage device 17 with results also being stored therein (see 6:23-34 and figure 2). Kim further evaluates targets against ‘extracted parameters’ and ‘internal conditions’ of a semiconductor device, while further verifying the accuracy by comparing the targets with real measurements (see 13:5-28).
It would be obvious to one of ordinary skill in the art at the time of the invention to use the interrelations of transistor properties outlined in Kim in a transistor design system as described in Lei, as the electrical and physical characteristics of transistors interrelate the same way regardless of the design system utilized. Both of the disclosed system further operate in the same art space.
While Lei teaches transforming targets in a system using Neural Networks to get more accurate models it is not explicit about how these transformations occur. David teaches a similar system for using machine learning in semiconductor manufacturing, but is further explicit about using machine learning to generate a target. David teaches performing machine learning on training data to generate a ‘yield prediction’ then further teaches setting the ‘yield as the target’, ‘identifying parameters’, ‘train[ing an] algorithm’ and ‘produc[ing] a model’ (see paragraphs 144-151 and figures 11 and 12). David teaches an iterative process where “outputs can be used as input” in the machine learning algorithms utilized in David to further adapt the simulation and better model semiconductors (see paragraphs 96-98). Here data ‘from prior production runs can be used to create a model for a target parameter’ (see paragraph 29). In this manner, the virtual target is generated based machine learning initially fed with data from the current generation, but generating new iterations through subsequent passes, each leading to improved targets. David specifically describes using ‘metrology’ data, measured data and data derived without having to measure, in machine learning algorithms to arrive at virtual targets (see paragraphs 45-50).
It would be obvious to one of ordinary skill in the art at the time of the invention to use the targets created via machine learning as done in David in the systems of Lei and Kim as this enables better accuracy of model results. Lei further describes the benefits of transforming targets.
With regard to claim 9, which further teaches wherein the virtual target generator is configured to generate all virtual targets of given channel lengths of the transistor and given channel widths of the transistor, Lei discloses use of transistor channel length and transistor channel width as features of a model that weigh into the resultant measured target characteristic (see paragraphs 32 and 43).
Kim further teaches evaluating multiple different combinations of channel length and channel width, generating models of each, and evaluating the parameters that weigh into the efficiency of each configuration (see 8:4-20, 14:7-41, and figure 7).
With regard to claim 10, which further teaches wherein the virtual target generator is configured to perform a first verification which compares at least a part of the virtual targets with a real target, Lei teaches evaluation of virtual target configuration by a comparison to a real target data, and using this evaluation to adapt future weightings (see paragraphs 7, 8, 37, 41, and 46).
With regard to claim 11, which further teaches wherein the virtual target generator is configured to perform a second verification which verifies a trend of the virtual targets, Lei teaches utilizing trends to enable modeling to converge on a target (see paragraph 52).
With regard to claim 12, which further teaches further comprising: a model generator configured to generate a transistor model using the processor, wherein the model generator is configured to receive the virtual target generated by the virtual target generator, the model generator is configured to extract parameters related to the virtual target, and the model generator is configured to determine the values of extracted parameters based on the virtual target and is configured to generate the transistor model, Lei teaches using machine learning to generate virtual model characteristics based on a prior generations data (see Lei 31-32, 46, 50, and 53 and figure 10). Here the system targets a transformation of the select characteristic (in this case ‘drain current’) and evaluates the varied weights of system characteristics (inputs) that weigh on the select characteristic. The inputs are applied to the deep neural network that then evaluates result as fitting target data and subsequently adapts the weights (non-measured data, not derived from measurements of initial semiconductor) in updated evaluations (see paragraphs 37, 41, and 46).
Kim teaches ‘process variables’ (PV1, PV2, etc.) that denote physical / structural characteristics of the semiconductor device, for example length of a gate line, width of an active area, channel length, device width, etc. (see 8: 4-20 and figure 3). Model interface 120 may then determine a set of parameters associated with each of the combinations of process variables, for example a parameter set associated with the value of process variable PV1 and the value of the second process variable PV2 (see 10:45-61). Next (in step S213) the “model interface 120 may predict the electrical characteristics and/or physical characteristics of the semiconductor device corresponding to the received value of the fist process variable PV1 and the value of the second process variable PV2 based on the determined model parameters and may output the characteristic data DATA_C” (see 10:62-67).
With regard to claim 13, which further teaches wherein the virtual target includes at least one of a threshold voltage target, an off-current target, a linear region current target, a middle region current target, a saturation region current target, and a drive temperature target of the transistor, Lei teaches evaluation threshold voltages (paragraph 14), current targets (paragraph 12-15), temperature targets (see paragraphs 12-15). Kim teaches evaluation of threshold voltages (7:32-44), threshold currents (6:3-8 and 120:54-59), and drive temperature (see 8:4-16).
With regard to claim 14, which teaches a system configured to generate a model using a virtual target, the system comprising: a storage unit configured to store instructions; and a processor, wherein when the instructions are executed by the processor, the instructions cause the processor to perform machine learning based on previous generation data and generate a virtual target of a current generation, the instructions cause the processor to extract parameters related to the virtual target, and the instructions cause the processor to determine values of extracted parameters based on the virtual target and generate the model, Lei teaches using machine learning and Artificial Neural Networks (ANN) to generate virtual model characteristics based on a prior generations data (see Lei 31-32, 46, 50, and 53 and figure 10). Here the system targets a transformation of the select characteristic (in this case ‘drain current’) and evaluates the varied weights of system characteristics (inputs) that weigh on the select characteristic. The inputs are applied to the deep neural network that then evaluates result as fitting target data and subsequently adapts the weights in updated evaluations (see paragraphs 37, 41, and 46). Lei further teaches processor and pre-processor 40 for use in implementing the simulation (see paragraphs 33 and claim 16).
Kim teaches a similar system for transistor design, but further lays out how individual parameters contribute to the overall target characteristic traits. Kim teaches ‘process variables’ (PV1, PV2, etc.) that denote physical / structural characteristics of the semiconductor device, for example length of a gate line, width of an active area, channel length, device width, etc. (see 8: 4-20 and figure 3). Model interface 120 may then determine a set of parameters associated with each of the combinations of process variables, for example a parameter set associated with the value of process variable PV1 and the value of the second process variable PV2 (see 10:45-61). Next (in step S213) the “model interface 120 may predict the electrical characteristics and/or physical characteristics of the semiconductor device corresponding to the received value of the fist process variable PV1 and the value of the second process variable PV2 based on the determined model parameters and may output the characteristic data DATA_C” (see 10:62-67). The characteristic parameters all being stored in storage device 17 with results also being stored therein (see 6:23-34 and figure 2). Kim further evaluates targets against ‘extracted parameters’ and ‘internal conditions’ of a semiconductor device, while further verifying the accuracy by comparing the targets with real measurements (see 13:5-28).
It would be obvious to one of ordinary skill in the art at the time of the invention to use the interrelations of transistor properties outlined in Kim in a transistor design system as described in Lei, as the electrical and physical characteristics of transistors interrelate the same way regardless of the design system utilized. Both of the disclosed system further operate in the same art space.
While Lei teaches transforming targets in a system using Neural Networks to get more accurate models it is not explicit about how these transformations occur. David teaches a similar system for using machine learning in semiconductor manufacturing, but is further explicit about using machine learning to generate a target. David teaches performing machine learning on training data to generate a ‘yield prediction’ then further teaches setting the ‘yield as the target’, ‘identifying parameters’, ‘train[ing an] algorithm’ and ‘produc[ing] a model’ (see paragraphs 144-151 and figures 11 and 12). David teaches an iterative process where “outputs can be used as input” in the machine learning algorithms utilized in David to further adapt the simulation and better model semiconductors (see paragraphs 96-98). Here data ‘from prior production runs can be used to create a model for a target parameter’ (see paragraph 29). In this manner, the virtual target is generated based machine learning initially fed with data from the current generation, but generating new iterations through subsequent passes, each leading to improved targets. David specifically describes using ‘metrology’ data, measured data and data derived without having to measure, in machine learning algorithms to arrive at virtual targets (see paragraphs 45-50).
It would be obvious to one of ordinary skill in the art at the time of the invention to use the targets created via machine learning as done in David in the systems of Lei and Kim as this enables better accuracy of model results. Lei further describes the benefits of transforming targets.
With regard to claim 15, which further teaches wherein the virtual target includes at least one of a threshold voltage target, an off-current target, a linear region current target, a middle region current target, a saturation region current target, and a drive temperature target of a transistor, Lei teaches evaluation threshold voltages (paragraph 14), current targets (paragraph 12-15), temperature targets (see paragraphs 12-15). Kim teaches evaluation of threshold voltages (7:32-44), threshold currents (6:3-8 and 120:54-59), and drive temperature (see 8:4-16).
With regard to claim 16, which further teaches wherein the virtual target includes a first virtual target of a first transistor having a first channel length and a first channel width, and a second virtual target of a second transistor having a second channel length different from the first channel length and the first channel width, and the model includes a first transistor model generated on the basis of the first virtual target and a second transistor model generated on the basis of the second virtual target, Lei discloses use of transistor channel length and transistor channel width as features of a model that weigh into the resultant measured target characteristic (see paragraphs 32 and 43).
Kim further teaches evaluating multiple different combinations of channel length and channel width, generating models of each, and evaluating the parameters that weigh into the efficiency of each configuration (see 8:4-20, 14:7-41, and figure 7).
With regard to claim 17, which further teaches wherein when the instructions are executed by the processor, the instructions cause the processor to perform a first verification which compares a real target measured from a third transistor having the first channel length and the first channel width with the first virtual target, Lei teaches evaluation of virtual target configuration by a comparison to a real target data, and using this evaluation to adapt future weightings (see paragraphs 7, 8, 37, 41, and 46).
With regard to claim 18, which further teaches wherein when the instructions are executed by the processor, the instructions cause the processor to perform a second verification which verifies a trend of the first virtual target and the second virtual target, Lei teaches utilizing trends to enable modeling to converge on a target (see paragraph 52).
With regard to claim 19, which further teaches wherein the virtual target further includes a third virtual target of a third transistor which has a third channel length different from the second channel length and a second channel width different from the first channel width, and the model further includes a third transistor model generated on the basis of the third virtual target, Lei discloses use of transistor channel length and transistor channel width as features of a model that weigh into the resultant measured target characteristic (see paragraphs 32 and 43).
Kim further teaches evaluating multiple different combinations of channel length and channel width generating models of each and evaluating the parameters the weigh in to the efficiency of each configuration (see 8:4-20, 14:7-41, and figure 7).
With regard to claim 20, which further teaches wherein when the instructions are executed by the processor, the instructions cause the processor to generate all virtual targets of given channel lengths and given channel widths, Kim further teaches evaluating multiple different combinations of channel length and channel width, generating models of each, and evaluating the parameters that weigh in to the efficiency of each configuration (see 8:4-20, 14:7-41, and figure 7).
Response to Arguments
Applicant's arguments filed 3/2/2026 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to the independent claims have been considered but are moot given the new ground of rejection laid out above.
It appears that the Applicant’s arguments are directed against the references individually, where one cannot show nonobviousness by attacking references individually when the rejection is based on a combination of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Here, the Applicant argues the references individually rather than the combination as a whole, specifically:
“Lei does not disclose (1) generating a virtual target that is free of current- generation measurement data, does not address (2) representing non-measurable device regions, and does not teach (3) verifying a generated virtual target by comparison with a real transistor measurement.”
“Kim does not (4) employ machine learning to generate targets, does not (5) use previous-generation data to generate models for a current generation, and does not disclose (~2) creating or verifying a virtual target that represents both measurable and non-measurable regions of a transistor.”
“David… does not (~4) generate virtual device targets, does not (5) rely on previous-generation device data to generate a current-generation device model, and does not (3) verify a virtual target by comparison with a real transistor measurement.”
This seems to imply that Kim and David teach (1), David teaches (2), Kim teaches (3), and Lei teaches (4) / (5). There is no argument against the claimed rejection as a whole or against the combination of references provided in the response.
With regard to the added limitation of “the virtual target representative of both measurable and non-measurable electrical operating regions of a first semiconductor device of the current generation, and the virtual target being free of data measurement associated with the first semiconductor device of the current generation”, Davis specifically teaches the virtual target is generated based machine learning initially fed with data from the current generation, but generating new iterations through subsequent passes, each leading to improved targets. David specifically describes using ‘metrology’ data, measured data and data derived without having to measure, in machine learning algorithms to arrive at virtual targets (see paragraphs 45-50). Lei teaches an analogous neural network for continual processing to improve end results (closing in on a target) (paragraphs 34-37), while using non-measured data, not derived from measurements of initial semiconductor.
With regard to the added limitation of “verifying the virtual target by comparing the virtual target with a real target, the real target being measured from a second semiconductor device of the current generation”, Kim further evaluates targets against ‘extracted parameters’ and ‘internal conditions’ of a semiconductor device, while further verifying the accuracy by comparing the targets with real measurements (see 13:5-28).
Summary
Claims 1-20 are REJECTED.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS G BONSHOCK whose telephone number is (571)272-4047. The examiner can normally be reached M-F 7:15 - 4:45.
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/DENNIS G BONSHOCK/Primary Examiner, Art Unit 3992