Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Status/ Amendment
Claims 1-20 are presented for examination based on the amendment filed 12/19/2025. Claims 1, 5-11, and 14-20 have been amended.
The 35 USC 103 rejection is maintained and modified to address the amended claim language.
The arguments pertaining to claims 1, 11, and 20 are moot due to the replacement of prior art for claim 1, 11, and 20.
The arguments pertaining to claim 5, and 15 are moot due to the replacement of prior art for claims 5, and 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11, and 20 are rejected under 35 U.S.C. 102 as being anticipated by Song et al., A kind of Fault of Integrated Circuits injection attacks analogy method based on partial scan (Song).
Claim 1
Song teaches A method comprising: receiving a circuit representation comprising a node and an overstress controller associated with the node; (Song Pg. 4 Step 1) “Synthesize the source code of the circuit to be tested (that is, design the hardware description source code for the circuit to be tested) into the original netlist, set the target variable for fault injection, and extract the target register for fault injection.” {Examiners note: Circuit representation corresponds to netlist. Node corresponds with target register, controller associated with node reads on fault injection control module. Forms a representation, and inserts a fault injection control module into the representation.}
and performing a simulation of an operation of the circuit using the circuit representation in an emulation model, including providing a stressor to the circuit representation at the node via the overstress controller during the simulation. (Song Pg. 5 Step 4) “Use the new netlist to generate the FPGA configuration file, and download the configuration file to the FPGA; The fault injection control module executes 3 to 7, injects faults into the circuit to be tested, and collects the output data of the circuit to be tested; Provide the input vector to the circuit to be tested, run the circuit to be tested until the fault is injected, and switch the circuit to be tested from the normal mode to the scan mode.” {Examiners note: Under BRI, emulation module reads on hardware emulation (configured to FPGA). The stressor is the injected “fault”/injected register value.}
Claim 11.
Song teaches A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to: receive a circuit representation comprising a node and an overstress controller associated with the node; (Song Pg. 4 Step 1) “Synthesize the source code of the circuit to be tested (that is, design the hardware description source code for the circuit to be tested) into the original netlist, set the target variable for fault injection, and extract the target register for fault injection.” {Examiners note: Circuit representation corresponds to netlist. Node corresponds with target register, controller associated with node reads on fault injection control module. Forms a representation, and inserts a fault injection control module into the representation. Song inherently describes a non-transitory computer readable medium. }
and perform a simulation of an operation of the circuit using the circuit representation in an emulation model, including to provide a stressor to the circuit representation at the node via the overstress controller during the simulation. (Song Pg. 5 Step 4) “Use the new netlist to generate the FPGA configuration file, and download the configuration file to the FPGA; The fault injection control module executes 3 to 7, injects faults into the circuit to be tested, and collects the output data of the circuit to be tested; Provide the input vector to the circuit to be tested, run the circuit to be tested until the fault is injected, and switch the circuit to be tested from the normal mode to the scan mode.” {Examiners note: Under BRI, emulation module reads on hardware emulation (configured to FPGA). The stressor is the injected “fault”/injected register value.}
Claim 20.
Modified Song teaches An emulation model comprising: a circuit representation comprising a node; and an overstress controller associated with the node of the circuit representation, wherein the overstress controller is configured to provide a stressor to the circuit representation at the node during simulation of the circuit representation using the emulation model. (Song Pg. 4 Step 2) “Use heuristic algorithm or other algorithms to select some registers from the original netlist as scan registers, insert scan chains and fault injection control modules into the original netlist to generate a new netlist.” (Pg. 5 Step 4) “Starting from the fault vector with the largest group number, scan into the scan register and run corresponding clock cycles in tum, that is, scan the value vector S k of the scan register into the scan register, let the circuit under test run for k clock cycles, and inject the fault into the target register;” {Examiners note: Circuit representation corresponds to netlist. Node corresponds with target register, controller associated with node reads on fault injection control module. Forms a representation, and inserts a fault injection control module into the representation. Under BRI, emulation module reads on hardware emulation (configured to FPGA). The stressor is the injected “fault”/injected register value.}
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4, 7, 10, 12 -14, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al., A kind of Fault of Integrated Circuits injection attacks analogy method based on partial scan (Song) in view of Wortman et al., US 8,650,447B1 (Wortman).
Claim 2.
Song does not explicitly teach, but Wortman teaches The method of claim 1, wherein the node is located at a communications interface of the circuit representation. (Wortman Summary Lines 60-64 “a transceiver includes a data transmission path arranged to transfer an outgoing data signal through a first series of protocol logic blocks and a data reception path arranged to transfer an incoming data signal through a second series of protocol logic blocks.”) {EXAMINERS NOTE: Communications interface can be any input/output port or interconnect through which a circuit exchanges data with other components.}
Song and Wortman are analogous to the claimed invention because they are from the same field of endeavor of error injection.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Song and Wortman before him or her, to modify the emulation model of Song with the node and overstress architecture of Wortman to increase precision of error injection as described in Wortman Col 2 Lines 56-60.
Claim 3.
Modified Song with Wortman teaches The method of claim 2, wherein the communications interface is an intra- die, inter-die, stack-to-stack, or socket-to-socket interface. (Wortman Background Lines 23-26 “XAUI is a multi-lane serial interface that has an aggregated bandwidth of 10 gigabits per second serial interface which may be used, for example, as a chip-to-module or chip-to-chip interface”) {EXAMINERS NOTE: Xaui is a protocol that operates as a chip to chip or chip to module interface. The transceiver injects errors using these interfaces which corresponds to inter-die or socket to socket connections.}
Claim 4.
Modified Song with Wortman teaches The method of claim 1, wherein the stressor is provided by the overstress controller, the method further comprising configuring the overstress controller to control the stressor. (Wortman Col 3 Lines 6-18 “The synchronous error signals may be used to trigger error events in a given protocol logic block (i.e. in a given sub-component of the data path). Logic circuitry in the protocol logic block is arranged and configured to determine whether any action is to be taken upon the 10 assertion of the error signal. For example, upon assertion of the error signal, logic circuitry in the protocol logic block may invert the expected data, purposefully corrupting the data integrity of the data transfer. By using the precisely-controlled error injection, multiple 15 error events may be triggered as the data signal (and its accompanying synchronous error signal) passes through pipelined functions of the data path so as to create complex error conditions.”) {EXAMINERS NOTE: Under BRI, stressor covers any deliberately introduced fault, error or disturbance used to test circuits. The corrupted data is the stressor, it is supplied by the error injection circuitry (overstress controller)}
Claim 7.
Modified Song teaches The method of claim 4, wherein configuring the overstress controller comprises configuring the overstress controller to produce errors, distortions, or random data in the stressor in the circuit representation. From the above list of alternatives the Examiner is selecting “errors.” (Song Pg. 6 (3)) “according to fault type, recalculates the value of destination register, updates each The register value vector of group. . .” (Pg. 5 (2)) “The fault injection control module executes® to 0 , injects faults into the circuit to be tested, and collects the output data of the circuit to be tested;” {Examiners note: The injected fault is an error because it intentionally causes the circuit node to have a value different from fault free value.}
Claim 10.
Modified Song teaches The method of claim 1, further comprising including the overstress controller in a request for manufacture of the circuit representation. (Song Pg. 4 Step 2) “insert scan chains and fault injection control modules into the original netlist to generate a new netlist.” (Pg. 5 Step 4) “Use the new netlist to generate the FPGA configuration file, and download the configuration file to the FPGA;” {Examiners note: Under BRI the FPGA configuration file is an implementation artifact used to configure the circuit.}
Claims 12 -14, 17, and 19
Claims 12 -14, 17, and 19 contain limitations similar to the limitations in claims 2-4, 7, 10 and are rejected for the same reasons.
Claims 5, 8, 9, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al., A kind of Fault of Integrated Circuits injection attacks analogy method based on partial scan (Song) in view of Wortman et al., US 8,650,447B1 (Wortman) in further view of Quijada et al., A Virtual Device for Simulation-Based Fault Injection (Quijada).
Claim 5.
Modified Song with Wortman does not explicitly teach, but Quijada teaches The method of claim 4, wherein configuring the overstress controller comprises configuring the overstress controller to produce a FIFO override in the circuit representation. (Quijada Pg. 5-6 Section 2.1-2.6) “This module receives the commands from tntsh and returns the requested data to it through a pair of input/output pipes. (2.4) “This module is responsible for accepting instructions from the tntsh software and returning the appropriate values” (2.5) (2.6) “The configuration module is responsible for reading and writing in the simulated target FPGA. It can configure a valid bitstream, and perform I/O operations on individual configuration bits, such as bit flips.” {Examiners note: Circuit representation corresponds to VHDL model and includes a FIFO memory for an override. Configuring corresponds to setting up/controlling injection/override via commands. Fault injection actions (bit flips)}
Song, Wortman, and Quijada are analogous to the claimed invention because they are from the same field of endeavor of error injection.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Song, Wortman, and Quijada before him or her, to modify the emulation model of Song with the node and overstress architecture of Wortman and the configuration of the overstress controller to produce FIFO overrides of Quijada to increase redundancy. (Quijada Pg. 2 paragraph 2)
Claim 8.
Modified Song with Quijada teaches The method of claim 4, wherein the circuit representation includes a control interface operable in the simulation to configure the overstress controller, (Quijada Pg. 4 Section 2) “The virtual device is a VHDL model of the firmware architecture for an FPGA-based fault injection platform . . . This software operates the hardware by sending the necessary commands and data to perform the injection campaigns . . .” (Pg. 5 Section 2.4) “This module is responsible for accepting instructions from the tntsh software and returning the appropriate values. It instances the command interpreter, which manages the commands received from the software and also interfaces with the vectors and configuration modules.” (Pg. 6 Section 2.6) “The configuration module is responsible for reading and writing in the simulated target FPGA. It can configure a valid bitstream, and perform I/O operations on individual configuration bits, such as bit flips.” {Examiners note: Control interface reads on the software command/ command interpreter/configuration module path. The interface operates in simulation and reads/writes to simulated target FPGA. Overstress controller reads on fault injection logic controlled by the interface. }
the method further comprising including the overstress controller and the control interface in a request for manufacture of the circuit representation. (Song Pg. 3) “select some registers as scan registers from the original netlist, insert scan chains and fault injection, control modules into the original netlist to generate a new netlist;” (Pg. 5 Step 4) “Use the new netlist to generate the FPGA configuration file, and download the configuration file to the FPGA;” {Examiners note: Under BRI the FPGA configuration file generated from the modified netlist is a request/implementation artifact for manufacturing/configuring the circuit.}
Claim 9.
Modified Song with Quijada teaches The method of claim 8, wherein the control interface is operable to selectively bypass the overstress controller in the circuit representation. (Quijada Pg. 4 Section 2) “The software part of the system is named tntsh. This software operates the hardware by sending the necessary commands and data to perform the injection campaigns. . .” (Pg. 5 Section 2.4) “This module is responsible for accepting instructions from the tntsh software and returning the appropriate values. It instances the command interpreter, which manages the commands received from the software and also interfaces with the vectors and configuration modules.” (Pg. 7 Section event Queue) “The event queue allows one to configure flags for the fault injection campaign that can alter the course of the test depending on what happens during the experiment, without continuously communicating with the software. . . by stopping a run (a complete execution of the test vectors with zero, one or more injections)” {Examiners note: Overstress controller reads on fault injection functionality. Under BRI configuring the campaign to use zero injections bypasses the fault injection operation, while other injector options enable to fault injection path. The control interface is operable to selectively bypass the overstress controller in the circuit representation by selecting a no injection mode during simulation.}
Claims 15, and 18
Claims 15, and 18 contain limitations similar to the limitations in claims 2-9 and are rejected for the same reasons.
Claims 6, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al., A kind of Fault of Integrated Circuits injection attacks analogy method based on partial scan (Song) in view of Wortman et al., US 8,650,447B1 (Wortman) in further view of Dang et al., Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems (Dang).
Claim 6.
Modified Song with Wortman does not explicitly teach, but Dang teaches The method of claim 4, wherein configuring the overstress controller comprises configuring the overstress controller to produce a network or credit override in the circuit representation. (Dang Pg. 1 Section 2) “The 3D-Network-on-Chip (3D-ONoC) router block diagram is shown in Fig. 1. The router has three pipeline stages: (1) BW (Buffer Writing), (2) NPC/SA (Next Port Computation and Switch Allocation), and (3) CT (Crossbar Traversal).” (Pg. 2 Paragraph 1) “The router architecture contains seven Input-port modules for each direction in addition to the Switch-Allocation and the Crossbar module, which handle the transfer of flits to the next node. . . the Next-Port-Computing module uses the routing information (destination and output-port) to calculate the routing information for the next node . . .” (Pg. 5 Section B) “For this evaluation, we used the three benchmarks over five injection rates : 0%, 8:33%, 16:67%, 11:11%&6:67% (in Routing and Switch Allocator) and 33%. . . We also inject the soft-errors inside the baseline model (LAFT-OASIS) and measure the transmission time.” {Examiners note: Under BRI network override corresponds to the intentional injecting of erroneous conditions into network control circuitry that determine packet/switching behavior. (The injections override the normal network control behavior within the modeled circuit.}
Song, Wortman, and Dang are analogous to the claimed invention because they are from the same field of endeavor of error injection.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Song, Wortman, and Dang before him or her, to modify the emulation model of Song with the node and overstress architecture of Wortman and the network override of Dang to reduce the time and computing resources as Dang suggests on Pg. 1 Paragraph 2.
Song, Wortman, and Dang are analogous to the claimed invention because they are from the same field of endeavor of error injection.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Song, Wortman, and Dang before him or her, to modify the emulation model of Song with the node and overstress architecture of Wortman and the network override of Dang
Claim 16
Claim 16 contains limitations similar to the limitations in claim 6 and is rejected for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOHN DAVID HAGLER/Examiner, Art Unit 2189
/REHANA PERVEEN/Supervisory Patent Examiner, Art Unit 2189
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