DETAILED ACTION
This Office Action is in response to claims filed on 02/19/2026.
Claims 1-44 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 13 of Applicant's remarks, filed 2/19/2026, with respect to objection to specification have been fully considered and are persuasive. The objection of 11/19/2025 has been withdrawn.
Applicant's arguments filed 02/19/2026 have been fully considered but they are not persuasive. Applicant argues in substance:
The Gokhale reference has not been shown to disclose obtaining hardware resource metadata containing error rate information for processing node … In other words, the present Application indicates that the error rate of a quantum logic gate can be specified as error per quantum operation such as gate fidelity. On the other hand, the cited portion of Gokhale refers to “target state infidelity”, which quantifies the closeness between two density matrices. In this case, the “target state” is the desired quantum state (or desired effect of the subcircuit/unitary), and GRAPE tries to drive the physical evolution under the candidate pulse, so the final state matches the target state – high “target state fidelity” corresponds to low target state infidelity”. Thus, “target state infidelity” is a threshold for the state produced by the control sequence. Importantly, a state fidelity is not a gate fidelity.
Therefore, the office action’s mapping of target state infidelity in Gokhale to the error rate information for processing nodes is inaccurate; and the Gokhale reference has not been shown to disclose or suggest obtaining hardware resource metadata specifying properties of a plurality of processing nodes in the computing system, the hardware resource metadata comprising error rate information and availability information for the respective processing nodes.
With respect to point (a), the Examiner respectfully disagrees. In summary, Applicant argues that the Gokhale reference’s disclosure of “target state infidelity” is an internal cost function optimization objective that does not teach “error rate information”. On page 17 of Applicant’s remarks, Applicant characterizes the “target state infidelity” particularly as “a threshold for the state produced by the control sequence.” However, Examiner rejects the characterization of “target state infidelity” set forth by the Applicant. As such, the Examiner sets forth that the “target state infidelity”, as reasonably interpreted in view of the Applicant’s specification, is a particular type of error rate associated with a hardware resource, thus satisfying the limitation of claim 1.
The Examiner has taken the reasonable interpretation of “target state infidelity” as a measure of error. Particularly, fidelity serves as the foundational metric from which infidelity is derived as its complement, wherein infidelity quantifies the degree to which an observed quantum operation state differs from an ideal quantum operation state (Qopt, Quantum Fidelity, 2021). Critically, an observed quantum operation state is necessary to produce a meaningful infidelity value. Without an actual hardware output to evaluate against the target, the error rate cannot be obtained. Applicant’s remarks, on page 17, acknowledge this characterization reciting that the target state infidelity “quantifies the closeness between two density matrices”, wherein the term “closeness” expresses a quantitative relationship between two states. As such, the Applicant’s argument that the “target state infidelity” as a “threshold for the state” does not accurately reflect this technical relationship. A threshold necessitates a comparator structure such that a measured quantity is evaluated against a bound. The “target state infidelity” serve this function as it is the quantity being measured. Applicant’s characterization of the “target state infidelity” as a threshold does not exclude it from being an error rate. Therefore, Gokhale’s “target state infidelity” is reasonably interpreted as a type of error rate.
Further, Applicant characterization of the “target state infidelity” as a threshold derives from the rationale, on page 15 of Applicant’s remarks, reciting that “target state infidelity is an internal optimization objective within a numerical pulse-level compilation routine (GRAPE), not hardware resource metadata that specifies properties of processing nodes.” However, Examiner directs Applicant’s attention to paragraph [0026] of Gokhale, which recites “[t]he quantum processor 132 can be continuously driven by external physical operations to any state in the space spanned by the logical states. The physical operations, called control fields, are specific to the underlying system” and “quantum gates can be regarded as a set of pre-programmed control fields performed on the quantum processor 132”. Further, paragraph [0051] of Gokhale discloses “the GRAPE algorithm manipulates a set of time-discrete control fields that act on a quantum system. It may analytically compute gradients of the cost function to be minimized with respect to the control fields” which includes “target state infidelity”. Thus, when taken as a whole, the disclosure establishes that the GRAPE algorithm operates on pre-programmed, hardware-specific control fields reflecting properties of the quantum processor, such that the “target state infidelity” is directly associated with error rate of a quantum operation relative to a target state produced by quantum hardware using the pre-existing properties. That is, Gokhale’s “target state infidelity” is associated with the properties of the quantum processor, thus satisfying the limitation of “hardware resource metadata comprising error rate information” as recited in claim 1.
Moreover, Applicant sets forth, on page 17 of Applicant’s remarks, that “the error rate of a quantum logic gate can be specified as error per quantum operation such as gate fidelity” and “[i]mportantly, a state fidelity is not a gate fidelity.” Examiner recognizes the technical distinction between a “state fidelity”, which measures the difference between an achieved quantum state and a target quantum state for an operation, and a “gate fidelity”, which characterizes the performance of a quantum gate more generally. In addition, Examiner recognizes that the Gokhale reference is limited to state fidelity metrics. However, “error rate information” as recited in claim 1 is not clearly claimed with any limitation that would exclude state fidelity metrics, and therefore cannot be read narrowly to encompass gate fidelity particularly. Furthermore, Applicant’s characterization of “error rate information”, as discussed in paragraph [0060] in the specification, is an exemplary description that extends the term beyond gate fidelity to any information from which error per quantum operations can be derived.
Therefore, the Office Action’s mapping of Gokhale’s “target state infidelity” reasonably satisfies the limitation of “hardware resource metadata comprising error rate information”. As established above, “error rate information” is a broad limitation that encompasses error rate structures beyond gate fidelity alone. Further, Gokhale’s disclosure of “target state infidelity”, as reasonably interpreted, constitutes error rate information within the bounds of the claim. Accordingly, the Examiner maintains that the combination of Rastogi and Gokhale teach all limitations of the claim.
Argument has not been found to be persuasive.
The cited references have not been shown to disclose generating a plurality of execution tasks based on hardware resource metadata, with each of the plurality of execution tasks comprising a respective subset of quantum logic operations.
With regard to point (b), Examiner respectfully disagrees. In summary, Applicant argues, on page 19 of Applicant’s remarks, that the combination of cited references have not been shown to disclose the generation of a plurality of execution tasks based configured to execute the quantum logic circuit on the plurality of processing nodes, wherein each of the plurality of execution tasks comprises a respective subset of the quantum logic operation and the plurality of execution tasks are generated based on the hardware resource metadata. Applicant points to Gokhale, reciting that the reference is “directed to quantum compilation, not distributed task generation”. However, Examiner argues that Gokhale was not relied upon to teach the generation of a plurality of execution tasks based on hardware resource metadata, nor the distribution of logic operations across multiple processing nodes. These teachings are supplied by Rastogi, which discloses a scheduling framework wherein hardware resource metadata is obtained and used to generate and distribute execution tasks across a plurality of processing nodes, with each task comprising a respective subset of operations assigned based on the properties of the nodes.
Argument has not been found to be persuasive.
A person of ordinary skill in the art would not be motivated to combine the two references, and the combination still does not teach the subject matter of claim 1.
With regard to point (c), Examiner respectfully disagrees. Examiner sets forth the combination of Rastogi in view of Gokhale represent a reasonable and predictable combination of known techniques. Task scheduling and resource allocation represent a well-established class of computational problems, wherein solutions to such problems have been applied across a broad range of computing contexts. Nothing in the claims precludes the application of known task scheduling and distribution techniques to quantum resources. The recitation of quantum computing resources describes the system being operated, however, does not recite any constraint on how execution tasks are generated or distributed particularly further than application on the quantum system. In other words, the claims reflect the application of a general scheduling methodology to a specific class of hardware, wherein a person of ordinary skill in the art would find the combination of references obvious, as the character of the processing nodes do not alter the fundamental nature of task scheduling and distribution that Rastogi addresses.
As discussed in point (b), Rastogi teaches task scheduling and resource allocation in the context of classical computing resources. Claim 1, as presented, recites “quantum computing resources” as the type of resource being scheduled, but does not recite any clear scheduling methodology or resource allocation technique that is specific to the quantum nature of those resources. The claimed scheduling limitations of claim 1, particularly directed to “the plurality of processing nodes comprising at least a subset of quantum computing resources”, “generating a plurality of execution tasks configured to execute the quantum logic circuit on the plurality of processing nodes”, and “dispatching the plurality of execution tasks to the plurality of processing nodes”, merely recite the application of quantum resources and would be equally satisfied by Rastogi’s teaching regardless of the type of computing resource recited. Thus, the combination of Rastogi in view of Gokhale is reasonable because Gokhale establishes that the resource being scheduled are quantum in nature, enabling Rastogi’s general task distribution methodology to be applied to the specific type of resource the claims recite.
Further, Applicant argues, on page 22 of Applicant’s remarks, that the motivation for combining fails to discuss why incorporating error-rate inputs into scheduling logic would yield predictable results. However, Rastogi reasonably teaches the use of hardware resource metadata as inputs related to scheduling, thus, demonstrating that the use of hardware properties in scheduling decision is a known technique. Gokhale merely teaches that a relevant hardware property in a quantum context would incorporate error rate.
Therefore, it would be clear to one of ordinary skill in the art to recognize that the predictable result of combining Rastogi’s scheduling methodology with Gokhale’s quantum computing resources disclosure produces a system capable of scheduling and distributing execution tasks across quantum processing system.
Argument has not been found to be persuasive.
Examiner Notes
Applicant is encouraged to contact the Examiner prior to submitting a response to discuss the cited issues and further advance prosecution.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10-21, 27-32, 34-36, 40-41, and 43-44 are rejected under 35 U.S.C. 103 as being unpatentable over Rastogi Patent No. US 8,887,163 B2 (hereinafter Rastogi) in view of Gokhale et al. Pub No. WO 2021/050541 A1 (hereinafter Gokhale).
With regard to claim 1, Rastogi teaches a method of operating a computing system comprising quantum computing [data processing] resources, the method comprising (Col. 1, lines 20-25, In data processing technology, software may include instructions to perform various tasks. As used herein, a “task” is a unit of work that may be scheduled for execution, either independently of other tasks or dependent upon one or more other tasks. Performance of a particular task may involve the use of a data processing resource.):
obtaining a computer program (Col. 2, lines 17-23, A software application (e.g., a web application) may entail one or more requests for execution of a set of tasks. In various example embodiments, execution of the software application causes the set of tasks to be requested for execution, designated as in need of execution, prescribed for execution, marked for execution or otherwise identified as designated for execution.), the computer program comprising a quantum logic circuit comprising quantum logic operations (FIG. 1; Col. 3, lines 40-44, FIG. 1, is a diagram illustrating an example of an execution schedule for a set 100 of tasks 110, 120, 130, 140, 150, and 160. The set 100 corresponds to a software application. For example, execution (e.g., invocation or initiation) of the software application may designate the set 100 for execution.);
obtaining hardware resource metadata specifying properties of a plurality of processing nodes in the computing system (Col. 6, lines 30-32 and 51-52, Task data (e.g., task configuration data), may specify an ability to constrain a number of concurrently executing tasks that may utilize a particular data processing resource … The task data may specify information (e.g., metadata) pertinent to the data processing resource), the plurality of processing nodes comprising at least a subset of the quantum computing [data processing] resources (Col. 6, lines 32-37, The task data may specify usage of the data processing resource as being unconstrained (e.g., unbounded). For example, lightweight business logic (e.g., aggregate results from subtasks) may utilize the data processing resource in an unconstrained matter. The task data may specify a constrain upon the usage of the data processing resource. Specifying a constraint may have the effect of limiting a maximum concurrent utilization of one or more data processing resource to a fixed (e.g., predetermined) number of concurrent executions), the hardware resource metadata comprising error rate information and availability information for the respective processing nodes (Col. 5, lines 1-10, A data processing resource may have a thread profile (e.g., a resource-thread profile) that indicates a task execution pattern (e.g., a queue of scheduled tasks) for that data processing resource );
generating a plurality of execution tasks configured to execute the quantum logic circuit on the plurality of processing nodes (Col. 11, lines 37-41, generating 630 dependency model data of the set of tasks based on the task dependency data, with the dependency model data indicating that the first task is to be executed prior to the second task, and the generating of the dependency model data being performed by a processor of a machine), wherein each of the plurality of execution tasks comprises a respective subset of the quantum logic operations (Col. 2, DGTaskExecutor allows the set of tasks (e.g., data defining the set) or a particular task (e.g., data defining the task) to configure a number of threads (e.g., a), and the plurality of execution tasks are generated based on the hardware resource metadata (Col. 6, lines 55-63, Task data may specify any number of prerequisites (e.g., a parent task) or no prerequisites, if none are needed … Taken together, static and dynamic prerequisites, if any, represent a minimum set of tasks required for a task to execute. Task data may specify a method that represents work to be accomplished by execution of the task);
dispatching (Col. 11, lines 42-46, scheduling 640 an execution of the first task using a data processing resource based on the dependency model data with the first task being scheduled for execution using the data processing resource) the plurality of execution tasks (Col. 14, lines 61-62, one or more of the individual operations may be performed concurrently) to the plurality of processing nodes (Col. 16, lines 7-16, The various operations of the example methods described herein may be performed, at least partially, by one or more processors that are temporality configured (e.g., by software) or permanently configured to perform relevant operations);
receiving output data generated by the plurality of processing nodes executing the plurality of execution tasks (Col. 13, lines 8-12, As shown in FIG. 11, the method 600 may include: obtaining 1120 information resultant from the execution of the first task (Examiner notes; which is substantially similarly performed for all execution tasks); and
producing an output of the computer program based on the output data (Col. 12, lines 51-56, Fig. 10 illustrates that the method 600 may include receiving 1010 a request that a document be provided to a user, with the document including a portion definable by information resultant from the execution of the first task. In some situations, the identifying 610 of the set of tasks is in response to this request; Col. 13, lines 8-12, As shown in FIG. 11, the method 600 may include: obtaining 1120 information resultant from the execution of the first task; generating 1130 a portion of the document based on the information resultant (Examiner notes: an output of the computer program from resulting data) from the execution of the first task). Rastogi teaches, at a high level, data processing resources but does not explicitly teach quantum computing resources, quantum logic circuits, quantum logic operations, and metadata comprising error rate information.
However, Gokhale teaches quantum computing resources ([0020], The quantum computing system described herein includes … a quantum processor. In some instances, the quantum processor may include tens, hundreds of qubits for use in execution), quantum logic circuits, quantum logic operations ([0024], A quantum algorithm may be described in terms of a quantum circuit. During quantum compilation, the quantum program 112 is first decomposed into a set of 1- and 2-qubit discrete quantum operations called logical quantum gates. These quantum gates are represented in a matrix form as unitary matrices) and error rate information ([0051], In GRAPE, an optimal control pulse is one that minimizes a set of cost functions corresponding to control amplitude, target state infidelity (Examiner notes: error rate of gate measurements), and evolution time, amongst others. hyperparameter optimization is employed on GRAPE ADAM optimizer, realizing faster convergence to a desired error rate over a baseline)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Gokhale with the teachings of Rastogi in order to provide a method that teaches scheduling of a computer program onto quantum/data processing resources and producing an output. The motivation for applying Gokhale teaching with Rastogi teaching is to provide a method that applies the known technique of scheduling allocating computational resources to subtasks to quantum computing processes in order to produce a desired result. As such the modification would have been motivated by the desire of combining known techniques of scheduling to quantum computing programs on quantum resources to yield predictable results. Rastogi and Gokhale are analogous art directed towards allocation of resources. Therefore, it would have been obvious for one of ordinary skill in the art to combine Gokhale with Rastogi to teach the claimed invention in order to provide scheduling framework to a quantum computing environment.
With regard to claim 2, Gokhale teaches wherein the quantum logic circuit is configured to be applied to a plurality of qubits, each of the plurality of execution tasks comprises a quantum logic block comprising a respective subset of the quantum logic operations ([0028], At the lowest level of hardware, quantum computers are controlled by analog pulses. Therefore, quantum compilations translate from a high-level quantum algorithm down to a sequence of control pulses 120. Once a quantum algorithm has been decomposed into a quantum circuit comprising single- and two-qubit gates (Examiner notes: such that the quantum logic circuit is mapped to n-qubit gate logic blocks), gate-based compilation can be performed by concatenating a sequence of pulses corresponding to each gate (Examiner notes: each quantum logic block performs a quantum logic operation on pulse), and each quantum logic block is configured to be applied to a subset of the plurality of qubits ([0028], In particular, a lookup table maps from each gate in the gate set (Examiner notes: wherein each gate logic block comprises n-qubits from a plurality) to a sequence of control pulses that executes that gate).
Rationale to claim 1 applied here.
Examiner notes: It would have been obvious for one of ordinary skill in the art to recognize that quantum logic circuits can be applied to qubits, and thus specifying qubits as the quantum computing resources of claim 1 which would have yielded predictable results.
With regard to claim 3, Gokhale teaches obtaining a hyperparameter associated with a requested execution of the computer program ([0032], FIG. 2 is a component diagram of the compilation engine 114 shown in FIG. 1. The modules shown in FIG. 2 pre-compile the quantum program 112 and prepare the optimized physical schedule 116 for execution. In the example embodiment, the compilation engine 114 includes … a hyperparameter optimization module 214); and
generating the plurality of execution tasks based on the hyperparameter and the hardware resource metadata ([0051], In the hyperparameter optimization method, the compilation engine 114 precomputes hyperparameters for each parameter-monotonic block 410 that can be used during runtime to converge much faster to the optimal pulse sequence for each block 410).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Gokhale with the teachings of Rastogi in order to provide a method that teaches hyperparameter associated with task generation. The motivation for applying Gokhale teaching with Rastogi teaching is to provide a method that allows for optimal pulse condition in operating a quantum computer such that reduces errors in measurements and can be replicated across other configurations ([0052], Gokhale). Rastogi and Gokhale are analogous art directed towards allocation of resources. Therefore, it would have been obvious for one of ordinary skill in the art to combine Gokhale with Rastogi to teach the claimed invention in order to provide task generation associated with hyperparameter optimization.
With regard to claim 4, Gokhale teaches wherein generating the plurality of execution tasks comprises determining the quantum logic blocks based on the hyperparameter in a cost function ([0043], the compilation engine 114 performs blocking of the circuit 300 prior to execution (e.g., at compile time). Many variational algorithms contain sets of gates that do not change from iteration to iteration. More specifically, the compilation engine 114 identifies blocks of gates (or just "fixed blocks") 402 (e.g. one or more gates) that do not depend upon the variational parameters theta.sub.i (e.g., parameterization-independent gates or subcircuits). All of the other variational parameterization-dependent gates (or subcircuits) 404 are excluded from the fixed blocks 402 but remain part of the circuit; [0051], To obtain an optimal control pulse, the GRAPE algorithm manipulates a set of time-discrete control fields that act on a quantum system. It may analytically compute gradients of the cost function to be minimized with respect to the control fields. These gradients are used to update control fields with an optimizer such as ADAM or L-BFGS-B. As opposed to the control fields, which are parameters manipulated by GRAPE, these optimizers have their own parameters such as learning rate and learning rate decay. These parameters are termed “hyperparameters” because they are set before the learning process begins).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Gokhale with the teachings of Rastogi in order to provide a method that teaches a determination of the quantum gate structures during the generation of tasks associated with a hyperparameter. The motivation for applying Gokhale teaching with Rastogi teaching is to provide a method that allows for identifying parameter-independent circuits from parameter-dependent circuits such that allows for partial compilation and achieving pulse speedup ([0045], Gokhale). Rastogi and Gokhale are analogous art directed towards allocation of resources. Therefore, it would have been obvious for one of ordinary skill in the art to combine Gokhale with Rastogi to teach the claimed invention in order to provide partial compilation of parameter-dependent circuits associated with pulse tasks generated from a hyperparameter.
With regard to claim 10, Rastogi teaches wherein the availability information in the hardware resource metadata indicates a number of qubits [data processing threads] available on the respective processing nodes (Col. 4-Col. 5, lines 65-67 and lines 1-3, DGTaskExecutor may allow the software application to configure a number of additional threads (e.g., processing threads beyond a single thread) to be used in a processing tasks of the software application. A data processing resource may have a thread profile (e.g., a resource-thread profile) that indicates a task execution pattern (e.g., a queue of scheduled tasks) for that processing resource), and the plurality of execution tasks are configured to be applied to the number of qubits [data processing threads] available on the respective processing nodes (Col. 5, lines 5-9, Based on the availability of resources, one or more of the DGTaskExecutor threads may select (e.g., configure a processor or other data processing resource to select) the highest priority task that can be executed).
However, Rastogi does not explicitly teach qubits.
Gokhale teaches qubits ([0020], In some instances, the quantum processor may include tens, hundreds of qubits for us in execution)
Rationale to claim 1 applied here.
With regard to claim 11, Rastogi teaches further comprising generating an execution schedule for the plurality of execution tasks (Col. 3, lines 30-31, A task graph may be generated at runtime; Col. 3 lines 40-44, FIG. 1, is a diagram illustrating an example of an execution schedule for a set 100 of tasks 110, 120, 130, 140, 150, and 160. This set corresponds to a software application. For example, execution (e.g., invocation or initiation) of the software application may designate the set 100 for execution), wherein the plurality of execution tasks are dispatched to the plurality of processing nodes according to the execution schedule (Col. 3, lines 35-37, Generation of the task graph at runtime may have the effect of allowing DGTTaskExecutor to dynamically optimize an execution plan for the set of tasks).
With regard to claim 12, Rastogi teaches wherein the number of execution tasks exceeds the number of processing nodes (Col. 9, A resource manager class (e.g., Resource Manager 320) may manage one or more data processing resources one or more resource queries (e.g., queries regarding capacity, constraints, or status of a data processing resource), one or more executable tasks, or any suitable combination thereof (Examiner notes: it is understood resource scheduling and allocation inherently operate in environments where task demand may surpass available processing nodes), and multiple of the execution tasks are dispatched to at least a subset of the plurality of processing nodes (Col. 9, A resource constraint class (e.g., ResourceConstraint 350) may define a type of constraint on a data processing resource. For example, the type may be “fixed” (e.g., with a fixed number of data processing resources (Examiner notes: a fixed subset of processing resources).
With regard to claim 13, Rastogi teaches wherein the execution schedule comprises logical synchronization points, and the method comprises (Col. 5-6, lines 65-67 and line 1, Simple join tasks (e.g., joins) can be added as a synchronization points within a task graph. In some example embodiments, a DGTaskExecutor system may support join tasks that neither add nor impart priority within the task graph):
iteratively receiving the output data from the plurality of processing nodes (Col. 6-Col.7, DGTaskExecutor may also support an ability to save a result (e.g., store information resultant from the execution of a task). DGTaskExecutor may access (e.g., load) results from any task, and DGTaskExecutor may update (e.g., modify or clear) results from any task); and
combining subsets of the output data at the logical synchronization points according to the execution schedule (Col. 5, lines 35-36, Dependencies among tasks may be described in terms of “parent-child” relationships (Examiner notes: set forth by the execution schedule) … In some example embodiments, execution of multiple software applications designates multiple sets of tasks for execution, and DGTaskExecutors may combine dependencies (e.g., multiple instances of task dependency data) together for task scheduling with shared threads, data processing resources, or constraints on data processing resources; Col. 6, lines 1-5, A task can also, at runtime, ask to join on an existing task. When this happens, the thread executing the task pauses execution of the currently executing task, and instead, executes other tasks until the join task has completed; Col. 7, lines 1-3, Task may support the ability to save information by other tasks or the calling software application (Examiner notes: wherein a parent tasks may join with a parent child, combining subsets of their respective output data).
With regard to claim 15, Gokhale teaches wherein the computing system comprises classical computing resources and quantum computing resources, and the plurality of processing nodes comprise at least a subset of the quantum computing resources and at least a subset of the classical computing resources ([0054], The quantum computing system includes the quantum processor including a plurality of qubits, a classical memory including a quantum program, a quantum program defines a plurality of instructions in a source language, and a classical processor communicatively coupled to the classical memory).
Rationale to claim 1 applied here.
With regard to claim 17, Rastogi teaches wherein receiving output data comprises receiving data buffers from the plurality of processing nodes (Col. 15-Col. 16, lines 66-67 and lines 1-6, For example, one hardware module may perform an operation and store the output of that operation in a memory device to which it is communicatively coupled. A further hardware module may then, at a later time, access the memory device to retrieve and process stored output. Hardware modules may also initiate communications with input or output devices, and can operate on a resource (e.g., a collection of information)
However, Rastogi does not explicitly teach a buffer comprising measured bit string values, Pauli measurement outcomes, and runtime metadata.
Gokhale teaches wherein each data buffer comprises measured bit string values, Pauli measurement outcomes, and runtime metadata ([0035], The fundamental of quantum computation is the qubit (e.g., qubit 134). A qubit has two basis states which may be represented by state vectors … the state of a qubit can be in a superposition of both 0 and 1 … When a qubit is measured, its quantum state collapses and either 0 or 1 are measured, with probabilities alpha.squared and beta.squared, respectivetly (Examiner notes: a Pauli measurement outcome)
Rationale to claim 1 applied here.
With regard to claim 18, Rastogi teaches a computing system comprising (Col. 1, lines 14-16, The subject matter disclosed herein generally relates to the processing of data. Specifically, the present disclosure addresses systems and methods of task scheduling):
…
the one or more classical computing resources configured (Col. 2, lines 5-8, An example task scheduling system is referred to herein as “DGTaskExecutor” or “Directed Graph TaskExecutor.” The example system is configured to perform one or more of the example methods discussed herein):
In addition, Gokhale teaches quantum computing resources ([0020], The quantum computing system described herein includes … a quantum processor. In some instances, the quantum processor may include tens, hundreds of qubits for use in execution); and
one or more classical computing resources communicably coupled to the quantum computing resources (FIG. 1; [0054], The quantum computing system includes the quantum processor including a plurality of qubits, a classical memory including a quantum program, the quantum program defines a plurality of instructions in a source language, and a classical processor communicatively coupled to the classical memory)
Claim 18 is a computer system having similar limitations to claim 1. Thus, claim 18 is rejected for the same rationale as applied to claim 1.
With regard to claim 19, it is a computer system having similar limitations to claim 2. Thus, claim 19 is rejected for the same rationale as applied to claim 2.
With regard to claim 20, it is a computer system having similar limitations to claim 3. Thus, claim 20 is rejected for the same rationale as applied to claim 3.
With regard to claim 21, it is a computer system having similar limitations to claim 4. Thus, claim 21 is rejected for the same rationale as applied to claim 4.
With regard to claim 27, it is a computer system having similar limitations to claim 10. Thus, claim 27 is rejected for the same rationale as applied to claim 10.
With regard to claim 28, it is a computer system having similar limitations to claim 11. Thus, claim 28 is rejected for the same rationale as applied to claim 11.
With regard to claim 29, it is a computer system having similar limitations to claim 12. Thus, claim 29 is rejected for the same rationale as applied to claim 12.
With regard to claim 30, it is a computer system having similar limitations to claim 13. Thus, claim 30 is rejected for the same rationale as applied to claim 13.
With regard to claim 32, it is a computer system having similar limitations to claim 15. Thus, claim 32 is rejected for the same rationale as applied to claim 15
With regard to claim 34, it is a computer system having similar limitations to claim 17. Thus, claim 34 is rejected for the same rationale as applied to claim 17.
With regard to claim 35, Rastogi teaches a method of operating a computing system comprising quantum computing [data processing] resources, the method comprising (Col. 1, lines 20-25, In data processing technology, software may include instructions to perform various tasks. As used herein, a “task” is a unit of work that may be scheduled for execution, either independently of other tasks or dependent upon one or more other tasks. Performance of a particular task may involve the use of a data processing resource.):
obtaining a quantum logic circuit comprising quantum logic operations (FIG. 1; Col. 3, lines 40-44, FIG. 1, is a diagram illustrating an example of an execution schedule for a set 100 of tasks 110, 120, 130, 140, 150, and 160. The set 100 corresponds to a software application. For example, execution (e.g., invocation or initiation) of the software application may designate the set 100 for execution.)
obtaining quantum hardware resource metadata indicating properties of processing nodes capable of executing respective portions of the quantum logic circuit (Col. 6, lines 30-32 and 51-52, Task data (e.g., task configuration data), may specify an ability to constrain a number of concurrently executing tasks that may utilize a particular data processing resource … The task data may specify information (e.g., metadata) pertinent to the data processing resource), the processing nodes comprising at least a subset of the quantum computing resources in the computing system (Col. 6, lines 32-37, The task data may specify usage of the data processing resource as being unconstrained (e.g., unbounded). For example, lightweight business logic (e.g., aggregate results from subtasks) may utilize the data processing resource in an unconstrained matter. The task data may specify a constrain upon the usage of the data processing resource. Specifying a constraint may have the effect of limiting a maximum concurrent utilization of one or more data processing resource to a fixed (e.g., predetermined) number of concurrent executions), the quantum hardware resource metadata comprising error rate information and availability information for the respective processing nodes (Col. 5, lines 1-10, A data processing resource may have a thread profile (e.g., a resource-thread profile) that indicates a task execution pattern (e.g., a queue of scheduled tasks) for that data processing resource);
determining an execution program for a decomposition of the quantum logic circuit (Col. 11, lines 37-41, generating 630 dependency model data of the set of tasks based on the task dependency data, with the dependency model data indicating that the first task is to be executed prior to the second task, and the generating of the dependency model data being performed by a processor of a machine) based on the quantum hardware resource metadata (Col. 6, lines 55-63, Task data may specify any number of prerequisites (e.g., a parent task) or no prerequisites, if none are needed … Taken together, static and dynamic prerequisites, if any, represent a minimum set of tasks required for a task to execute. Task data may specify a method that represents work to be accomplished by execution of the task);
causing execution tasks of the execution program to execute on the processing nodes consistent with the execution program (Col. 11, lines 42-46, scheduling 640 an execution of the first task using a data processing resource based on the dependency model data with the first task being scheduled for execution using the data processing resource); and
determining an output of the quantum logic circuit, the output being based on intermediate outputs generated by the execution tasks being executed on the processing nodes (Col. 12, lines 51-56, Fig. 10 illustrates that the method 600 may include receiving 1010 a request that a document be provided to a user, with the document including a portion definable by information resultant from the execution of the first task. In some situations, the identifying 610 of the set of tasks is in response to this request; Col. 13, lines 8-12, As shown in FIG. 11, the method 600 may include: obtaining 1120 information resultant from the execution of the first task; generating 1130 a portion of the document based on the information resultant (Examiner notes: an output of the computer program from resulting data) from the execution of the first task).
Rastogi teaches, at a high level, data processing resources but does not explicitly teach quantum computing resources, quantum logic circuits, quantum logic operations, quantum hardware resource metadata and metadata comprising error rate information.
However, Gokhale teaches quantum computing resources ([0020], The quantum computing system described herein includes … a quantum processor. In some instances, the quantum processor may include tens, hundreds of qubits for use in execution), quantum logic circuits, quantum logic operations ([0024], A quantum algorithm may be described in terms of a quantum circuit. During quantum compilation, the quantum program 112 is first decomposed into a set of 1- and 2-qubit discrete quantum operations called logical quantum gates. These quantum gates are represented in a matrix form as unitary matrices), quantum hardware resource metadata (), and error rate information ([0051], In GRAPE, an optimal control pulse is one that minimizes a set of cost functions corresponding to control amplitude, target state infidelity (Examiner notes: error rate of gate measurements), and evolution time, amongst others)
Rationale to claim 1 applied here.
With regard to claim 36, Gokhale teaches obtaining hyperparameters associated with the quantum logic circuit, the hyperparameters comprising a cost function hyperparameter ([0051], hyperparameter optimization is employed on GRAPE ADAM optimizer, realizing faster convergence (Examiner notes: Applied to a cost function) to a desired error rate over a baseline); and
determining the decomposition of the quantum logic circuit using the cost function hyperparameter in a cost function ([0032], FIG. 2 is a component diagram of the compilation engine 114 shown in FIG. 1. The modules shown in FIG. 2 pre-compile the quantum program 112 and prepare the optimized physical schedule 116 for execution. In the example embodiment, the compilation engine 114 includes … a hyperparameter optimization module 214; [0051], In the hyperparameter optimization method, the compilation engine 114 precomputes hyperparameters for each parameter-monotonic block 410 that can be used during runtime to converge much faster to the optimal pulse sequence for each block 410)
Rationale to claim 3 applied here.
With regard to claim 40, it is a method having similar limitations to claim 10. Thus, claim 40 is rejected for the same rationale as applied to claim 10.
With regard to claim 41, it is a method having similar limitations to claim 13. Thus, claim 41 is rejected for the same rationale as applied to claim 13.
With regard to claim 43, it is a method having similar limitations to claims 14 and 15. Thus claim 43 is rejected for the same rationale as applied to claims 14 and 15.
With regard to claim 44, Rastogi teaches wherein causing the execution tasks to execute on the processing nodes comprises dispatching (Col. 11, lines 42-46, scheduling 640 an execution of the first task using a data processing resource based on the dependency model data with the first task being scheduled for execution using the data processing resource) the execution tasks Col. 14, lines 61-62, one or more of the individual operations may be performed concurrently) to the respective processing nodes (Col. 16, lines 7-16, The various operations of the example methods described herein may be performed, at least partially, by one or more processors that are temporality configured (e.g., by software) or permanently configured to perform relevant operations)
Claims 5-6, 22-23, and 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Rastogi in view of Gokhale as applied to claims 1, 18, and 35 above, and further in view of Javadiabhari et al. Patent No. US 11,194,642 B2 (hereinafter Javadiabhari) in view of Murali et al. Patent No. US 11,121,725 B2 (hereinafter Murali).
With regard to claim 5, Javadiabhari teaches determining a runtime of a set of quantum logic blocks based on the availability information (Col. 9, Component 408 analyzes the set of qubit parameter values 416 … for example component 408 can determine a coherence time of a quit fails to satisfy a threshold coherence time to perform a set of operations. As another example, component can determine a coherence time of another qubit meets a threshold coherence time to perform the set of operations); and
determining an error rate of the set of quantum logic blocks based on the error rate information (Col. 10, In an embodiment, component 410 generates composite gate error rate for a composite gate from a set of primitive gate error rates, the composite gate formed from a set of primitive gates corresponding to the primitive gate error rates. In an embodiment, component 410 generates a composite gate error rate for a composite gate formed using three qubits from the formula)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Javadiabhari with the teachings of Rastogi and Gokhale in order to provide a method that teaches determinations of runtime and error rate of a set of quantum logic blocks. The motivation for applying Javadiabhari teaching with Rastogi and Gokhale teaching is to provide a method that allows for ascertaining qubit capabilities, such that enables construction of quantum gates meeting acceptability criterion (Col. 10, Javadiabhari). Rastogi and Gokhale and Javadiabhari are analogous art directed towards quantum computing arrangements. Therefore, it would have been obvious for one of ordinary skill in the art to combine Javadiabhari with Rastogi and Gokhale to teach the claimed invention in order to provide qubit capability information.
However, the combination does not explicitly teach a cost function comprising two components associated with the runtime and error state of the quantum logic blocks with a weighing factor.
Murali teaches wherein the cost function comprises (Col. 15, Objective Function: Scheduler component 110 can employ the objective function defined below to minimize both gate errors from crosstalk and decoherence errors):
a first component associated with the runtime of the set of quantum logic blocks (Col. 15, the second term minimizes the product of decoherence errors (Examiner notes: coherence time); and
a second component associated with the error rate of the set of quantum logic blocks (Col. 15, The first term minimizes the product of the gate errors), and the hyperparameter specifies a weighting of the second component relative to the first component (Col. 15, To test the relative importance of crosstalk and decoherence errors, scheduler component 110 can employ a weighted objective where scheduler component 110 applies a crosstalk weight factor (Examiner notes: hyperparameter) omega an element of [0, 1] to the gate error rate terms).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Murali with the teachings of Rastogi, Gokhale, and Javadiabhari in order to provide a method that teaches a cost function that incorporates qubit runtime and error rate provided with a weight parameter. The motivation for applying Murali teaching with Rastogi, Gokhale, and Javadiabhari teaching is to provide a method that allows for an objective function to minimize gate and decoherence error such that improves the efficiency and accuracy of quantum outputs (Col. 15, Murali). Rastogi, Gokhale, and Javadiabhari and Murali are analogous art directed towards quantum computing arrangements. Therefore, it would have been obvious for one of ordinary skill in the art to combine Murali with Rastogi, Gokhale, and Javadiabhari to teach the claimed invention in order to provide a quantum gate cost function.
With regard to claim 6, Murali teaches wherein comprising:
evaluating the cost function for respective sets of quantum logic blocks based on the error rate information and availability information in the hardware resource metadata (Col. 15-Col. 16, To compute the optimal schedule for a program (e.g., a schedule that minimizes both crosstalk errors (Examiner notes: gate error rate) and decoherence errors), scheduler component 110 can first use a quantum computing system's passes to generate the program IR (e.g., program IR 304) and map it to the quantum hardware (e.g., map it to a qubit coupling map such as, for instance, qubit coupling map 302 that represents the quantum hardware). The mapped program IR can be used by scheduler component 110 to create the above described optimization problem using the objective function defined above along with data dependency, gate error, and decoherence error constraints defined above.).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Murali with the teachings of Rastogi, Gokhale, and Javadiabhari in order to provide a method that teaches an evaluation of the quantum gate cost function provided. The motivation for applying Murali teaching with Rastogi, Gokhale, and Javadiabhari teaching is to provide a method that allows for a quantum scheduler to generate an optimal schedule with respect to the components provided in the cost function (Col. 16, Murali). Rastogi, Gokhale, and Javadiabhari and Murali are analogous art directed towards quantum computing arrangements. Therefore, it would have been obvious for one of ordinary skill in the art to combine Murali with Rastogi, Gokhale, and Javadiabhari to teach the claimed invention in order to evaluate and apply a cost function to quantum resource scheduling.
With regard to claim 22, it is a computer system having similar limitations to claim 5. Thus, claim 22 is rejected for the same rationale as applied to claim 5.
With regard to claim 23, it is a computer system having similar limitations to claim 6. Thus, claim 23 is rejected for the same rationale as applied to claim 6.
With regard to claim 37, it is a method having similar limitations to claim 5, Thus, claim 37 is rejected for the same rationale as applied to claim 5.
With regard to claim 38, it is a method having similar limitations to claim 6, Thus, claim 38 is rejected for the same rationale as applied to claim 6.
Claims 7, 24, and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Rastogi in view of Gokhale as applied to claims 1, 18, and 35 above, and further in view of Perlin et al. "Quantum Circuit Cutting with Maximum Likelihood Tomography" (hereinafter Perlin).
With regard to claim 7, Perlin teaches wherein generating the plurality of execution tasks comprises performing a wire cutting process, and each execution task specifies (Pg. 1, One decomposition, inspired by the fragmentation methods used for quantum molecular cluster simulations, applies fragmentation to the execution of quantum circuits. This decomposition consists of first “cutting” a quantum circuit into smaller subcircuits, or “fragments”, that can be executed on processors with fewer qubits, and then reconstructing the probability distribution over measurement outcomes for the original quantum circuit from probability distributions associated with its fragments):
one or more initial states determined by the wire cutting process (Pg. 2, FIG. 1. Circuit Cutting Example. … Green … boxes labeled by the state M.sub.s … correspond to preparations … of a qubit in the corresponding state (Examiner notes: wherein qubit preparers are operators in which initialize a qubit’s state); Pg. 2, The decomposition in Eq. (7) allows interpreting each (M.sub.s) as a conditional state, obtained either by … preparing a qubit in state); and
one or more measurements determined by the wire cutting process (Pg. 2, FIG. 1. Circuit Cutting Example. … (Red) boxes labeled by the state … (M.sub.r) correspond to … (projections) of a qubit in the corresponding state (Examiner notes: wherein qubit projectors are operators in which measure a qubit’s state); Pg. 2 The decomposition in Eq. (7) allows interpreting each (M.sub.s) as a conditional state, obtained either by post-selecting onto the measurement of a qubit in state).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Perlin with the teachings of Rastogi and Gokhale in order to provide a method that teaches a wire cutting process applied to quantum machines including quantum circuits defined by initial states and measurements. The motivation for applying Perlin teaching with Rastogi and Gokhale teaching is to provide a method that demonstrations that “circuit cutting can estimate the output of a cluster circuit with higher fidelity than full circuit execution, thereby motivating the use of circuit cutting as a standard tool for running cluster circuits on quantum hardware” (Abstract, Perlin). Rastogi and Gokhale and Perlin are analogous art directed towards quantum circuits and computing. Therefore, it would have been obvious for one of ordinary skill in the art to combine Perlin with Rastogi and Gokhale to teach the claimed invention in order to provide quantum circuit cutting techniques to improve quantum computing accuracy.
With regard to claim 24, it is a computer system having similar limitations to claim 7. Thus, claim 24 is rejected for the same rationale as applied to claim 7.
With regard to claim 42, it is a method having similar limitations to claim 7. Thus, claim 42 is rejected for the same rationale as applied to claim 7.
Claims 8-9, 25-26, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Rastogi in view of Gokhale as applied to claims 1, 18, and 35 above, and further in view of Germain et al. Patent No. US 9,866,954 B2 (hereinafter Germain).
With regard to claim 8, Germain teaches comprising receiving a stopping criterion for a requested execution of the computer program, and determining a number of iterations for each of the plurality of execution tasks based on the stopping criterion (Col. 5, lines 40-45, Accordingly, techniques are described in which one or more stopping criteria 120 are identified by the computing device 102. The iterative algorithm module 118, for instance, may configured to identify stopping criteria (e.g., a number of iterations that are to be performed for the algorithm) from a training dataset).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Germain with the teachings of Rastogi and Gokhale in order to provide a method that teaches a stopping criterion specifying a number of iterations for execution tasks of a computer program. The motivation for applying Germain teaching with Rastogi and Gokhale teaching is to provide a method that improves algorithmic efficiency by preventing excessive iterative processing, reducing computational overhead, and ensuring timely convergence such that combination would yield predictable results. Rastogi and Gokhale and Germain are analogous art directed towards digital processing. Therefore, it would have been obvious for one of ordinary skill in the art to combine Germain with Rastogi and Gokhale to teach the claimed invention in order to provide stopping criterion for iterative algorithms.
With regard to claim 9, Germain teaches wherein the stopping criterion comprises an error bound for the output of the computer program (Col. 8-9, lines 60-67 and lines 1-5, considering the non-monotonic relation between the convergence score (e.g., cost) and a score computed using values of performance metrics, the iterative algorithm module 118 may be configured to identify stopping criteria based on a measurable quantity (e.g., either on the number of iterations or the cost function log-derivative value) that maximizes the performance of the algorithm).
Rationale to claim 8 applied here.
Examiner notes: It would have been obvious for one of ordinary skill in the art to employ a cost function’s error output as a stopping criterion to control convergence of iterative optimization algorithms, as such techniques were well known for ensuring computational efficiency. As such the modification would have yielded predictable results.
With regard to claim 25, it is a computer system having similar limitations to claim 8. Thus, claim 25 is rejected for the same rationale as applied to claim 8.
With regard to claim 26, it is a computer system having similar limitations to claim 9. Thus, claim 26 is rejected for the same rationale as applied to claim 9.
With regard to claim 39, it is a method having similar limitations to claim 8. Thus, claim 39 is rejected for the same rationale as applied to claim 8.
Claims 14 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Rastogi in view of Gokhale as applied to claims 1 and 18 above, and further in view of Sun et al. Pub. No. US 2008/0273457 (hereinafter Sun).
With regard to claim 14, Rastogi teaches generating a first execution schedule for the plurality of execution tasks (Col. 3, lines 4-6 and lines 13-15 and lines 20-23, DGTaskExecutor identifies a set of tasks as being designated for (e.g., requested for, prescribed for, marked for, or in need of) execution … DGTaskExecutor generates a dependency model (E.g., dependency model data) based on the task dependency data … The scheduling of the execution is based on the dependency model);
in response to failure of a first processing node of the processing nodes (Col. 7, When adding tasks to the dependency model (e.g., a dependency graph), DGTaskExecutor may use a lightweight algorithm to evaluate static prerequisites; Col. 8, In the event that a deadlock is detected, all of the tasks that are depend upon the task that is adding the dynamic dependency may be marked (e.g., by DGTaskExecutor in accordance with the algorithm) as failed within the graph),
However, Rastogi does not explicitly teach truncation and augmenetation of the execution schedule.
Sun teaches identifying a logical synchronization point in the first execution schedule ([0030], Once a synchronization point is reached, the process reaches a consensus to spawn a new process);
truncating the first execution schedule by removing execution tasks associated with the first processing node after the logical synchronization point the first execution schedule ([0030], Then the processes collectively spawn a new process P.sub.n. The new process P.sub.n is initialized. Then the processes collectively establish a new group C.sub.new. The new group C.sub.new includes the newly spawned process P.sub.n. It should be appreciated that establishing a new process or group may consist one or more operations … The new process P.sub.n replaces P.sub.j in operation and P.sub.j will exit at some point (Examiner notes: such that Process N truncates the first execution schedule consisting of Process J); and
augmenting a second execution schedule with the truncated first execution schedule at the logical synchronization point ([0030], Once the new group C.sub.new is established, C.sub.new will replace the old group C. The migrated process P.sub.j collects group membership information, coordinates with the new process P.sub.n, and sends the group membership information to process P.sub.n to restore and/or update the group membership information at group C.sub.new.), the second execution schedule comprising an execution task for execution by a second processing node ([0028], For example, while participating in group communication, each process asynchronously waits to receive migration signal from UNIX indicating the process should migrate to a new device; [0030]. All processes in group C.sub.new may reset migration flags and synchronization flags. Group C.sub.new continues operating with process P.sub.n in its new location).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Sun with the teachings of Rastogi and Gokhale in order to provide a method that teaches dynamic migration of scheduled tasks. The motivation for applying Sun teaching with Rastogi and Gokhale teaching is to provide a method that allows for “fault tolerance of processes supported by migrating a process from a failing device to a stable device, in order to provide continued service” ([0004], Sun). Rastogi and Gokhale and Sun are analogous art directed towards scheduling arrangement of resources. Therefore, it would have been obvious for one of ordinary skill in the art to combine Sun with Rastogi and Gokhale to teach the claimed invention in order to provide scheduling failover.
With regard to claim 31, it is a computer system having similar limitations to claim 14. Thus, claim 31 is rejected for the same rationale as applied to claim 14.
Claims 16 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Rastogi in view of Gokhale as applied to claims 1 and 18 above, and further in view of Smith et al. Pub. No. US 2018/0365585 A1 (hereinafter Smith).
Smith was cited in the IDS filed 20 July 2022.
With regard to claim 16, Gokhale teaches wherein the processing node comprise:
a first processing node comprising a quantum processing unit that uses qubit devices to process a first subset of the plurality of execution tasks ([0022], The quantum computing device 130 includes multiple qubits 134 that represent a quantum processor 132 upon which the quantum program 112 is executed); and
However, the combination does not explicitly teach a virtual quantum machine.
Smith teaches a second processing node comprising a virtual quantum machine (FIG. 2, Server 208 hosting a QVM 245; [0040], FIG. 2 is a block diagram of example computing system 200. Example computing system 200 comprises an example server 208 and one or more example QPUs 203. Example servers may be, e.g., server 108 described in FIG. 1 … Server 208 includes … a QVM 245) that comprises a classical processor ([0018] The server 108 can allocate quantum computing resources (e.g., one or more QPUs, one or more quantum virtual machines, etc.) and other computing resources in the hybrid computing environment according to the schedule, and delegate computing jobs to the allocated computing resources for execution (Examiner notes: such that the QVM is allocated classical computing resources). The other (non-quantum) computing resources in the hybrid environment may include, for example, one or more digital microprocessors, one or more specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), or other types of computing modules.) to process a second subset of the plurality of execution tasks ([0019] In some cases, the server 108 can select the type of computing resource (e.g., quantum or otherwise) to execute an individual computing job in the computing environment 101).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Smith with the teachings of Rastogi and Gokhale in order to provide a method that teaches quantum virtual machines performing a subset of execution tasks. The motivation for applying Smith teaching with Rastogi and Gokhale teaching is to provide a method that allows for integration of quantum resources with classical resource, such that enables quantum operations to be managed and coordinated alongside classical processes using existing hardware infrastructures (Smith, [0053]). Rastogi and Gokhale and Smith are analogous art directed towards scheduling strategies. Therefore, it would have been obvious for one of ordinary skill in the art to combine Smith with Rastogi and Gokhale to teach the claimed invention in order to provide quantum and classical computing integration through quantum virtual machines.
With regard to claim 33, it is a computer system having similar limitations to claim 16. Thus, claim 33 is rejected for the same rationale as applied to claim 16.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2020/0117764 A1
teaches
[0038], At action 206, the hardware metadata associated with the quantum computer is received. As earlier described, the hardware metadata may include parameters that impact the performance of the quantum computing hardware such as frequencies, coherence times, error rates, etc.
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/I.A.C./Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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