DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to amendments filed January 8th, 2026. The status of the claims is as follows. Examiner notes that as of 07/22/2025, applicant has elected Group I Claims 1-15, drawn to bit-level pruning and quantization of neural network weights during training of a neural network, for examination without traverse. As such, Claims 16-20 are withdrawn from consideration and will not be examined. Claims 1, 5, 9-11, 15 are amended. Claims 1-15 are currently pending.
Applicant is reminded in the future to use correct status identifiers. The proper identifier for Claims 16-20 is either (Withdrawn) or (Withdrawn-Currently Amended.) See MPEP 714: “For any amendment being filed in response to a restriction or election of species requirement and any subsequent amendment, any claims which are non-elected must have the status identifier (withdrawn). Any non-elected claims which are being amended must have either the status identifier (withdrawn) or (withdrawn – currently amended) and the text of the non-elected claims must be presented with markings to indicate the changes. Any non-elected claims that are being canceled must have the status identifier (canceled).” Use of improper status identifiers in future responses will result in the response being considered non-compliant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Fang (CN111582471A) in view of Suri et al. (US 20220383121 A1, hereinafter “Suri”).
Regarding Claim 1,
Fang discloses A method, comprising: training a neural network, based on training data, to generate a trained neural network, the neural network including weights (Fang [Page 2 Line 1]; “The pruned neural network model is retrained by using the improved gradient descent algorithm. The improved stochastic gradient descent algorithm refers to: determining the descending gradient by using the straight-through gradient estimation method and judging to use the descending gradient to update the quantized weight Whether the set condition can be satisfied, if yes, use the descending gradient to update the quantized weight; if not, do not update the quantized weight.” wherein the process of training a neural network using quantization and pruning of a network and performing gradient descent (implying gradients computed between training data and cost) on the resulting quantized and pruned network read on generating a weight-based trained neural network based on training data)
the training including: quantizing the weights to generate quantized weights, each quantized weight including a number of bits set to 1 (Fang [Page 3 Line 5]; “The weights and activation values in the trained neural network model are quantized according to the set quantization bit width” wherein the weights are quantized to generate quantized weights
Fang [Page 3 Line 43]; “It can be seen from the above description that the proportion and distribution of 1 in the binary representation of the weight will affect the performance of the neural network model on the bit-serial accelerator. Among them, from a macro perspective, for the same network structure, when the proportion of 1 in the binary representation of the weight is lower, the bit-serial accelerator can skip more redundant computations, thereby improving performance. Therefore, in the application scenario where the neural network model needs to be deployed in a bit-serial accelerator, it is of great significance to compress the neural network model to improve the bit sparsity of the weights (that is, to increase the proportion of 0 in the weight binary)." wherein the compression (involving quantization) of the neural network involving the weight binaries’ proportion and distribution of bits set to 1 reads on the quantized weights including a number of bits set to 1)
and pruning by at least one processing node of a plurality of processing nodes coupled to a number of less significant bitlines of a plurality of bitlines including a most significant bitline and the number of less significant bitlines, based on the number of bits set to 1, the quantized weights to generate bit-pruned weights (Fang [Page 3 Line 23]; “The method provided by the embodiment of the present invention determines the bit pruning strength of each layer in the quantized neural network model by quantizing the weights and activation values in the trained neural network model. For each layer, the weight and activation value in the layer are pruned based on the bit pruning strength of the layer, and the pruned neural network model is retrained” wherein pruning of each individual layer according to the specified parameters of the associated layer thus reads on a plurality of processing nodes (comprising the neural network layers) by which pruning is performed; wherein the processing nodes of the neural network are implicitly coupled to a number of bitlines, of which the compression involving the weight binaries’ proportion and distribution of bits set to 1 thus read on such bitlines comprising a “most significant” and “least significant” bitlines)
each bit-pruned weight including a smaller number of bits set to 1 than the respective quantized weight to reduce a density of set bits of each bit-pruned weight (Fang [Page 3 Line 25]; “network model pruning can fully reduce the bit redundancy of the neural network model, and further enable the neural network model to have good performance on the bit-serial accelerator” wherein bit-pruned weights with reduced bit redundancy
Fang [Page 2 “Background technique” section, Line 6]; “At the same time, for the same neural network structure, the lower the proportion of 1 in the weight binary, the more redundant calculations can be skipped by the bit-serial accelerator, and the performance can be improved more effectively. It is of great significance to compress the network model (also known as de-redundancy) to improve the sparsity of the weight bits (ie, to increase the proportion of 0 in the weight binary).” wherein improved performance on the bit-serial accelerator describe as an increased proportion of 0 in the weight binary reads on a lower proportion of 1 in the weight binary; wherein the reduced proportion of bits set to 1 in the weight binary thus reads on the reduction of density of set bits of each bit-pruned weight)
where the trained neural network includes the bit-pruned weights (Fang [Page 2 Line 7]; “a pruning module, configured to perform pruning processing on the weights in the layer based on the bit pruning strength of the layer for each layer of the quantized neural network model;
The retraining module is used to retrain the neural network model after bit pruning”)
Fang fails to explicitly disclose but Suri discloses where the reduced density of each bit-pruned weight reduces bit-level switching and power consumption during inference (Suri [0028]; “For example, an input to a compute node that multiplies and input tensor by a specific weight can be eliminated when the entire input tensor is set to zero, and thus this compute operation can be completely skipped in subsequent layers. This can result in a significant compute reduction in the neural network”)
It would have been obvious for Fang’s method of bit-pruning weights to be performed for Suri’s disclosed intended use of reducing density for reducing bit-level switching and power consumption. One would have been motivated to do so because “as the computational demands and input sizes of modern neural networks continue to increase, memory storage between layers is rapidly becoming a serious bottleneck, and the demands of parallel processing are becoming difficult to manage” (Suri [0003]).
Regarding Claim 3,
Fang/Suri teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Fang/Suri further discloses for each quantized weight, reducing the number of bits set to 1 to N; and N is greater than 0 (Fang [Page 3 Line 45]; “Therefore, in the application scenario where the neural network model needs to be deployed in a bit-serial accelerator, it is of great significance to compress the neural network model to improve the bit sparsity of the weights (that is, to increase the proportion of 0 in the weight binary).” wherein increasing the proportion of 0 in the weight binary reads on reducing the number of bits set to 1)
Regarding Claim 4,
Fang/Suri teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Fang/Suri further discloses determining an average number of the bits set to 1 in the quantized weights and reducing the number of the bits set to 1 in each quantized weight to reduce an average number of bits set to 1 to N; and N is greater than 0 (Fang [Page 3 Line 45]; “Therefore, in the application scenario where the neural network model needs to be deployed in a bit-serial accelerator, it is of great significance to compress the neural network model to improve the bit sparsity of the weights (that is, to increase the proportion of 0 in the weight binary).” wherein increased bit sparsity comprising reducing the average number of bits set to 1 comprises reducing the non-zero bits set to 1; wherein increasing bit sparsity reads on the reduction of some number of bits set to 1 to N value)
Regarding Claim 5,
Fang/Suri teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Fang/Suri further discloses quantizing activations to generate quantized activations, each quantized activation including a number of bits set to 1 (Fang [Page 3 Line 5]; “The weights and activation values in the trained neural network model are quantized according to the set quantization bit width” wherein the activations are quantized to generate quantized activations
Fang [Page 4 Line 14]; “Therefore, the above-mentioned quantization bit width may be 8 bits, that is, the weights and activation values in the trained neural network model are expressed in an 8-bit binary format” wherein the binary quantized activation values reads on a number of bits set to 1)
and pruning by the at least one processing node of the plurality of processing nodes, based on the number of bits set to 1, the quantized activations to generate bit-pruned activations (Fang [Page 3 Line 23]; “The method provided by the embodiment of the present invention determines the bit pruning strength of each layer in the quantized neural network model by quantizing the weights and activation values in the trained neural network model. For each layer, the weight and activation value in the layer are pruned based on the bit pruning strength of the layer, and the pruned neural network model is retrained”)
each bit-pruned activation including a smaller number of bits set to 1 than the respective quantized activation to reduce a density of set bits of each bit-pruned activation (Fang [Page 3 Line 25]; “network model pruning can fully reduce the bit redundancy of the neural network model, and further enable the neural network model to have good performance on the bit-serial accelerator” wherein bit-pruned weights with reduced bit redundancy)
where the reduced density of each bit-pruned weight reduces bit-level switching and power consumption during inference (Suri [0028]; “For example, an input to a compute node that multiplies and input tensor by a specific weight can be eliminated when the entire input tensor is set to zero, and thus this compute operation can be completely skipped in subsequent layers. This can result in a significant compute reduction in the neural network”)
Regarding Claim 7,
Fang/Suri teaches the method of Claim 5 (and thus the rejection of Claim 5 is incorporated). Fang/Suri further discloses for each quantized activation, reducing the number of bits set to 1 to N; and N is greater than 0 (Fang [Page 3 Line 5]; “The weights and activation values in the trained neural network model are quantized according to the set quantization bit width” wherein the activations quantized to generate quantized activations interpreted as compression of the neural network model
Fang [Page 3 Line 45]; “Therefore, in the application scenario where the neural network model needs to be deployed in a bit-serial accelerator, it is of great significance to compress the neural network model to improve the bit sparsity of the weights (that is, to increase the proportion of 0 in the weight binary).” wherein increasing the proportion of 0 in the weight binary reads on reducing the number of bits set to 1)
Regarding Claim 8,
Fang/Suri teaches the method of Claim 5 (and thus the rejection of Claim 5 is incorporated). Fang/Suri further discloses determining an average number of the bits set to 1 in the quantized activation, and reducing the number of the bits set to 1 in each quantized activation to reduce an average number of bits set to 1 to N; and N is greater than zero (Fang [Page 3 Line 5]; “The weights and activation values in the trained neural network model are quantized according to the set quantization bit width” wherein the activations quantized to generate quantized activations interpreted as compression of the neural network model
Fang [Page 3 Line 45]; “Therefore, in the application scenario where the neural network model needs to be deployed in a bit-serial accelerator, it is of great significance to compress the neural network model to improve the bit sparsity of the weights (that is, to increase the proportion of 0 in the weight binary).” wherein increased bit sparsity comprising reducing the average number of bits set to 1 comprises reducing the non-zero bits set to 1; wherein increasing bit sparsity reads on the reduction of some number of bits set to 1 to N value)
Claims 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Fang (CN111582471A) in view of Suri et al. (US 20220383121 A1, hereinafter “Suri”) in view of Ahn et al. (“Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks” [2020], hereinafter “Ahn”).
Regarding Claim 2,
Fang/Suri teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Fang/Suri does not explicitly disclose but Ahn discloses for each quantized weight: replacing each sequence of N consecutive bits set to 1 with a sequence of N consecutive bits set to zero; setting the bit in the next highest bit position relative to each sequence of N consecutive bits to 1; and N is greater than 1 (Ahn [Figure 3B];
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It would have been obvious to use Ahn’s method of pruning weights by replacing consecutive non-zero bits with a sequence of zeros lead by a 1 at the highest bit location in Fang/Suri’s method of generating a neural network using quantized, bit-pruned weights. One would have been motivated to do so because “the maximal computation speedup was bounded by the total number of non-zero bits” (Ahn [Section VI]), and by reducing the number of non-zero bits, computation efficiency is improved.
Regarding Claim 6,
Fang/Suri teaches the method of Claim 5 (and thus the rejection of Claim 5 is incorporated). Fang/Suri does not explicitly disclose but Ahn discloses for each quantized activation: replacing each sequence of N consecutive bits set to 1 with a sequence of N consecutive bits set to zero, and setting the bit in the next highest bit position relative to each sequence of N consecutive bits to 1; and N is greater than 1 (Ahn [Figure 3B];
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Ahn [Figure 8];
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It would have been obvious to use Ahn’s method of pruning activations by replacing consecutive non-zero bits with a sequence of zeros lead by a 1 at the highest bit location in Fang/Suri’s method of generating a neural network using quantized, bit-pruned weights. One would have been motivated to do so because “the maximal computation speedup was bounded by the total number of non-zero bits” (Ahn [Section VI]), and by reducing the number of non-zero bits, computation efficiency is improved.
Claims 9-11, 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Fang (CN111582471A) in view of Suri et al. (US 20220383121 A1, hereinafter “Suri”) in view of Muvva et al. (“On the Effectiveness of Quantization and Pruning on the Performance of FPGAs-based NN Temperature Estimation” [2021], hereinafter “Muvva”).
Regarding Claim 9,
Fang/Suri teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Fang/Suri already discloses quantizing activations to generate quantized activations, each quantized activation including a number of bits set to 1 (Fang [Page 3 Line 5]; “The weights and activation values in the trained neural network model are quantized according to the set quantization bit width” wherein the activations are quantized to generate quantized activations
Fang [Page 4 Line 14]; “Therefore, the above-mentioned quantization bit width may be 8 bits, that is, the weights and activation values in the trained neural network model are expressed in an 8-bit binary format” wherein the binary quantized activation values reads on a number of bits set to 1)
and dynamically pruning by the at least one processing node of the plurality of processing nodes, based on the number of bits set to 1, the quantized activations to generate bit-pruned activations, each bit pruned activation including a smaller number of bits set to 1 than the respective quantized activation (Fang [Page 3 Line 23]; “The method provided by the embodiment of the present invention determines the bit pruning strength of each layer in the quantized neural network model by quantizing the weights and activation values in the trained neural network model. For each layer, the weight and activation value in the layer are pruned based on the bit pruning strength of the layer, and the pruned neural network model is retrained”
Fang [Page 3 Line 25]; “network model pruning can fully reduce the bit redundancy of the neural network model, and further enable the neural network model to have good performance on the bit-serial accelerator” wherein bit-pruned weights with reduced bit redundancy)
to reduce a density of set bits of each bit-pruned activation (Fang [Page 3 Line 25]; “network model pruning can fully reduce the bit redundancy of the neural network model, and further enable the neural network model to have good performance on the bit-serial accelerator” wherein bit-pruned weights with reduced bit redundancy)
where the reduced density of each bit-pruned weight reduces bit-level switching and power consumption during inference (Suri [0028]; “For example, an input to a compute node that multiplies and input tensor by a specific weight can be eliminated when the entire input tensor is set to zero, and thus this compute operation can be completely skipped in subsequent layers. This can result in a significant compute reduction in the neural network”)
Fang/Suri does not explicitly disclose but Muvva discloses executing the trained neural network, based on input data from one or more sensors, to generate at least one prediction (Muvva [Section IV]; “The ultimate goal of the project is to implement the model in the chip so it may use the information to perform appropriate temperature management. Then we worked on compiling the model into FPGA logic. TensorFlow optimization tools are utilized to prune the model, while Vitis AI is utilized to quantize and compile the model.
A. Pruning
Tensorflow Model Optimization toolkit is used to prune the models. Two different percentages are used to prune the models. The percentages are 25% and 50%. A part of the training dataset is used to calibrate the pruning model. The performance results of the pruned model can be found in the results section.
B. Quantization
Vitis AI development kit is implemented by Xilinx. It consists of tools such as Quantizer, Compiler, Profiler among others. A significant purpose of the system is to quantize and compile deep learning neural networks for FPGA implementation. The Vitis AI quantizer was used to quantize both models, the MLP and the RNN. We have used two different quantization depths; those are 8-bit and 16-bit quantization techniques to implement two different quantized versions for each model. The results of these models can be found in the results section” wherein the Neural Network is quantized and bit-pruned reading on a trained Neural Network comprising bit-pruned neural network weights
Muvva [Section I Column 2 Line 8]; “Later, during the run time, the trained NN model uses the information from the on-chip thermal sensors and the performance counters in order to infer the thermal map of the chip.” wherein the trained neural network makes inferences or predictions based on one or more sensors)
executing an autonomous or semi-autonomous process based, at least in part, on the prediction (Muvva [Section VI]; “This paper presents a technique for estimating both the current on-chip thermal map and the rate of temperature change. This information is useful for proactive thermal management. The models are very good at predicting the closed loop temperature, however they have difficulty as time passes. “ wherein proactive thermal management dependent on the estimated thermal predictions of the pruned and quantized model reads on executing an autonomous or semi-autonomous proactive process based on the prediction)
It would have been obvious to use Muvva’s method of using sensor data as input to a trained neural network to execute some autonomous or semi-autonomous process depending on the outputted inference in Fang/Suri’s method of generating a neural network using quantized, bit-pruned weights. One would have been motivated to do so because “information from all available on-chip thermal sensors as well as performance counters together with data of the measured infrared images are jointly use training process of NN models” (Muvva [Section I]) thus allowing Neural Networks to be trained for deployment process capabilities specific to the inputted sensory data.
Regarding Claim 10,
Fang discloses processing circuitry including at least one processing node of a plurality of processing nodes coupled to a number of less significant bitlines of a plurality of bitlines including a most significant bitline and the number of less significant bitlines, the at least one processing node configured to:execute, based on input data, a neural network to generate at least one prediction during inference, the neural network including bit-pruned weights (Fang [Page 3 Line 23]; “The method provided by the embodiment of the present invention determines the bit pruning strength of each layer in the quantized neural network model by quantizing the weights and activation values in the trained neural network model. For each layer, the weight and activation value in the layer are pruned based on the bit pruning strength of the layer, and the pruned neural network model is retrained” wherein pruning of each individual layer according to the specified parameters of the associated layer thus reads on a plurality of processing nodes (comprising the neural network layers) by which pruning is performed; wherein the processing nodes of the neural network are implicitly coupled to a number of bitlines, of which the compression involving the weight binaries’ proportion and distribution of bits set to 1 thus read on such bitlines comprising a “most significant” and “least significant” bitlines)
quantize activations to generate quantized activations, each quantized activation including a number of bits set to 1 (Fang [Page 3 Line 5]; “The weights and activation values in the trained neural network model are quantized according to the set quantization bit width” wherein the activations are quantized to generate quantized activations
Fang [Page 4 Line 14]; “Therefore, the above-mentioned quantization bit width may be 8 bits, that is, the weights and activation values in the trained neural network model are expressed in an 8-bit binary format” wherein the binary quantized activation values reads on a number of bits set to 1)
and prune by the at least one processing node, based on the number of bits set to 1, the quantized activations to generate bit-pruned activations, each bit-pruned activation including a smaller number of bits set to 1 than the respective quantized activation (Fang [Page 3 Line 23]; “The method provided by the embodiment of the present invention determines the bit pruning strength of each layer in the quantized neural network model by quantizing the weights and activation values in the trained neural network model. For each layer, the weight and activation value in the layer are pruned based on the bit pruning strength of the layer, and the pruned neural network model is retrained”)
to reduce a density of set bits of each bit-pruned activation (Fang [Page 3 Line 25]; “network model pruning can fully reduce the bit redundancy of the neural network model, and further enable the neural network model to have good performance on the bit-serial accelerator” wherein bit-pruned weights with reduced bit redundancy)
Fang fails to explicitly disclose but Suri discloses where the reduced density of each bit-pruned weight reduces bit-level switching and power consumption during inference (Suri [0028]; “For example, an input to a compute node that multiplies and input tensor by a specific weight can be eliminated when the entire input tensor is set to zero, and thus this compute operation can be completely skipped in subsequent layers. This can result in a significant compute reduction in the neural network”)
It would have been obvious for Fang’s method of bit-pruning weights to be performed for Suri’s disclosed intended use of reducing density for reducing bit-level switching and power consumption. One would have been motivated to do so because “as the computational demands and input sizes of modern neural networks continue to increase, memory storage between layers is rapidly becoming a serious bottleneck, and the demands of parallel processing are becoming difficult to manage” (Suri [0003]).
Fang/Suri does not explicitly disclose but Muvva discloses to Execute, based on input data, a neural network to generate at least one prediction, the neural network including bit-pruned weights (Muvva [Section IV]; “The ultimate goal of the project is to implement the model in the chip so it may use the information to perform appropriate temperature management. Then we worked on compiling the model into FPGA logic. TensorFlow optimization tools are utilized to prune the model, while Vitis AI is utilized to quantize and compile the model.
A. Pruning
Tensorflow Model Optimization toolkit is used to prune the models. Two different percentages are used to prune the models. The percentages are 25% and 50%. A part of the training dataset is used to calibrate the pruning model. The performance results of the pruned model can be found in the results section.
B. Quantization
Vitis AI development kit is implemented by Xilinx. It consists of tools such as Quantizer, Compiler, Profiler among others. A significant purpose of the system is to quantize and compile deep learning neural networks for FPGA implementation. The Vitis AI quantizer was used to quantize both models, the MLP and the RNN. We have used two different quantization depths; those are 8-bit and 16-bit quantization techniques to implement two different quantized versions for each model. The results of these models can be found in the results section” wherein the Neural Network is quantized and bit-pruned reading on a trained Neural Network comprising bit-pruned neural network weights
Muvva [Section I Column 2 Line 8]; “Later, during the run time, the trained NN model uses the information from the on-chip thermal sensors and the performance counters in order to infer the thermal map of the chip.” wherein the trained neural network makes inferences or predictions based on one or more sensors)
It would have been obvious to use Muvva’s method of executing a neural network on inputted sensory data to generate predictions in Fang/Suri’s method of generating a neural network using quantized, bit-pruned weights. One would have been motivated to do so because “information from all available on-chip thermal sensors as well as performance counters together with data of the measured infrared images are jointly use training process of NN models” (Muvva [Section I]) thus allowing Neural Networks to be usable for deployment scenarios specific to the inputted data.
Regarding Claim 11,
The combination of Fang/Suri/Muvva teaches the method of Claim 10 (and thus the rejection of Claim 10 is incorporated). Fang/Suri/Muvva already discloses to where the processing circuitry includes a plurality of bit-pruning units (BPUs), and each BPU is configured to prune a quantized activation (Fang [Page 2 “Summary of the Invention” Section, Line 4]; “Quantify the weights and activations in the trained neural network model;
Determine the bit pruning strength of each layer in the quantized neural network model;
For each layer of the quantized neural network model, pruning the weights in the layer based on the bit pruning strength of the layer”
Fang [Page 2 Line 6]; “A determination module for determining the bit pruning strength of each layer in the quantized neural network model;
a pruning module, configured to perform pruning processing on the weights in the layer based on the bit pruning strength of the layer for each layer of the quantized neural network model” wherein a module comprising processes for each layer to perform independent iterations of pruning each respective layer’s quantized activations reads on processing circuitry associated with bit-pruning units wherein each BPU is configured to prune a quantized activation)
and having the plurality of processing nodes and including the at least one processing node coupled to a number of less significant bitlines of a plurality of bitlines including a most significant bitline and the number of less significant bitlines (Fang [Page 3 Line 23]; “The method provided by the embodiment of the present invention determines the bit pruning strength of each layer in the quantized neural network model by quantizing the weights and activation values in the trained neural network model. For each layer, the weight and activation value in the layer are pruned based on the bit pruning strength of the layer, and the pruned neural network model is retrained” wherein pruning of each individual layer according to the specified parameters of the associated layer thus reads on a plurality of processing nodes (comprising the neural network layers) by which pruning is performed; wherein the processing nodes of the neural network are implicitly coupled to a number of bitlines, of which the compression involving the weight binaries’ proportion and distribution of bits set to 1 thus read on such bitlines comprising a “most significant” and “least significant” bitlines)
Regarding Claim 13,
The combination of Fang/Suri/Muvva teaches the method of Claim 11 (and thus the rejection of Claim 11 is incorporated). Fang/Suri/Muvva already discloses to for each quantized activation, reduce the number of bits set to 1 to N; and N is greater than 0 (Fang [Page 2 “Summary of the Invention” Section, Line 4]; “Quantify the weights and activations in the trained neural network model;
Determine the bit pruning strength of each layer in the quantized neural network model;
For each layer of the quantized neural network model, pruning the weights in the layer based on the bit pruning strength of the layer”
Fang [Page 2 Line 6]; “A determination module for determining the bit pruning strength of each layer in the quantized neural network model;
a pruning module, configured to perform pruning processing on the weights in the layer based on the bit pruning strength of the layer for each layer of the quantized neural network model” wherein a module comprising processes for each layer to perform independent iterations of pruning each respective layer’s quantized activations reads on processing circuitry associated with bit-pruning units wherein each BPU is configured to prune a quantized activation)
Regarding Claim 14,
The combination of Fang/Suri/Muvva teaches the method of Claim 11 (and thus the rejection of Claim 11 is incorporated). Fang/Suri/Muvva already discloses to determine an average number of the bits set to 1 in the quantized activation, and reduce the number of the bits set to 1 in each quantized activation to reduce an average number of bits set to 1 to N; and N is greater than zero (Fang [Page 3 Line 5]; “The weights and activation values in the trained neural network model are quantized according to the set quantization bit width” wherein the activations quantized to generate quantized activations interpreted as compression of the neural network model
Fang [Page 3 Line 45]; “Therefore, in the application scenario where the neural network model needs to be deployed in a bit-serial accelerator, it is of great significance to compress the neural network model to improve the bit sparsity of the weights (that is, to increase the proportion of 0 in the weight binary).” wherein increasing the proportion of 0 in the weight binary reads on reducing the number of bits set to 1)
Regarding Claim 15,
The combination of Fang/Suri/Muvva teaches the method of Claim 10 (and thus the rejection of Claim 10 is incorporated). Fang/Suri/Muvva already discloses to at least one sensor, coupled to the processing circuitry, configured to generate and transmit sensor data to the processing circuitry (Muvva [Section I]; “Later, during the run time, the trained NN model uses the information from the on-chip thermal sensors and the performance counters in order to infer the thermal map of the chip.” wherein the trained neural network makes inferences or predictions based on one or more sensors; wherein the sensors relaying the information to the Neural Network reads on the sensors coupled to the processing circuitry to transmit the thermal sensory data for NN input
Muvva [Abstract]; “ Therefore, the network could be embedded in the chip, whether it be an ASIC or an FPGA.”)
where the processing circuitry is further configured to execute an autonomous or semi-autonomous process based, at least in part, on the prediction during inference (Muvva [Section VI]; “This paper presents a technique for estimating both the current on-chip thermal map and the rate of temperature change. This information is useful for proactive thermal management. The models are very good at predicting the closed loop temperature, however they have difficulty as time passes. “ wherein proactive thermal management dependent on the estimated thermal predictions of the pruned and quantized model reads on executing an autonomous or semi-autonomous proactive process based on the prediction)
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Fang (CN111582471A) in view of Suri et al. (US 20220383121 A1, hereinafter “Suri”) in view of Muvva et al. (“On the Effectiveness of Quantization and Pruning on the Performance of FPGAs-based NN Temperature Estimation” [2021], hereinafter “Muvva”) in view of Ahn et al. (“Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks” [2020], hereinafter “Ahn”).
Regarding Claim 12,
The combination of Fang/Suri/Muvva teaches the method of Claim 11 (and thus the rejection of Claim 11 is incorporated). Fang/Suri/Muvva does not explicitly disclose but Ahn discloses for each quantized activation: replace each sequence of N consecutive bits set to 1 with a sequence of N consecutive bits set to zero, and set the bit in the next highest bit position relative to each sequence of N consecutive bits to 1; and N is greater than 1 (Ahn [Figure 3B];
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Ahn [Figure 8];
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It would have been obvious to use Ahn’s method of pruning activations by replacing consecutive non-zero bits with a sequence of zeros lead by a 1 at the highest bit location in Fang/Suri/Muvva’s method of generating a neural network using quantized, bit-pruned weights and activations. One would have been motivated to do so because “the maximal computation speedup was bounded by the total number of non-zero bits” (Ahn [Section VI]), and by reducing the number of non-zero bits, computation efficiency is improved.
Response to Arguments
The Examiner acknowledges the Applicant’s amendments to Claims 1, 5, 9-11, 15.
Applicant’s arguments filed January 8th, 2026, traversing the rejection of claims 1-15 under 35 U.S.C. § 101 have been fully considered, and are fully persuasive.
Applicant’s arguments filed January 8th, 2026, traversing the rejection of claims 1-15 under 35 U.S.C. § 103 have been fully considered, but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JONATHAN J KIM/Examiner, Art Unit 2141
/MATTHEW ELL/Supervisory Patent Examiner, Art Unit 2141
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