DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 5-12 and 14-21 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 5 line 6, “an operation” should read “the operation” instead. Claim 16 recites a similar limitation in line 5 and is objected to for the same reason. Claims 6-11 inherit the same deficiency as claim 5 by reason of dependence.
B. In claim 12 line 16, “each of the first and data” should read “each of the first and the second data” instead for better clarity. Claims 14-17 inherit the same deficiency as claim 12 by reason of dependence.
C. In claim 17 line 2, “a processor” should read “the processor” instead because a processor is already introduced in claim 12 from which the claim depends.
D. In claim 18 lines 7 and 11, “separately processes” should read “separate processes” instead for better clarity. Claim 19recites a similar limitation in lines 12 and is objected to for the same reason. Claims 19-21 inherit the same deficiency as claim 18 by reason of dependence.
E. In claim 18 line 16, “a predetermined threshold” should read “the predetermined threshold” instead because a predetermined threshold already introduced in lines 3-4.
Claim Interpretation
The term “lazy update” in claim 18 as interpreted as described in paragraph [0075]
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites “the separately processes” in lines 1-2. It is unclear which separate processes this is supposed to be referring. It is unclear whether this meant to refer to the separate processes at the first time or the second time or both. For purposes of examination, this is interpreted to refer to both.
Claim 21 recites “the plurality of data” in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as a plurality of data. (Note: Applicant may want to amend the claim to recite “wherein the plurality of shared exponents comprising exponents of a plurality of data are stored into data fields separate from data fields storing the first and second data” instead for better clarity).
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 4 and 15 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 4 recites “wherein a total number of bits of the exponent identifier field is less than or equal to a total number of bits of each of the plurality of shared exponents”. Claim 1 upon which claim 4 depends recites “a plurality of shared exponents comprising exponents of the plurality of data” in lines 8-9; and “wherein the floating-point representation reduces a total number of bits required to represent each of the plurality of data in the memory by replacing an exponent field with the exponent identifier field having fewer bits than the exponent field” in lines 17-19. Claim 4 fails to include all the limitations of claim 1 because if the total number of bits of the exponent identifier field is equal to the total number of bits of each of the plurality of shared exponents, then there would be no reduction in the total number of bits required to represent each of the plurality of data because the exponent field is replaced by the exponent identifier field equal number of bits as exponent field. Claim 14 recites a similar limitation and is rejected for the same reason.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 18-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under Step 1, claims 18-21 recite a series of steps and, therefore, is a process.
Under Step 2A prong 1, claim 18 recites
A processor-implemented method, comprising:
determining, by a processor, whether an exponential difference between first data and second data on which an operation set to be performed is greater than a predetermined threshold based on respective exponent identifier fields in the first data and the second data identifying a location of a corresponding shared exponent among a plurality of shared exponents stored in a memory;
performing, at a first time, by the processor, separate processes on exponents of the first data and the second data, and mantissas of the first data and the second data, with a block floating point operation; and
performing, at a second time, by the processor, separate processes on the exponents of the first data and the second data, and the mantissas of the first data and the second data, with the block floating point operation and a lazy update
wherein the lazy update is performed in response to the exponential difference between the first and second data is greater than a predetermined threshold.
The above underlined limitations of determining whether an exponent difference between a first data and a second data is greater than a predetermined threshold and performing a block floating point operation or a block floating point operation and a lazy update based on the determining amounts to processing mathematical relationships and/or calculations that can be practically performed mentally and falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. The step of “determining”, “performing” and “performing” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “by a processor”, nothing in the claim element precludes the step from practically being performed in the human mind. For example, but for the “by a processor” language, the claim encompasses visually comparing whether an exponential difference value between a first data and a second data is greater than a predetermined threshold value and performing a block floating point addition operation if the exponential difference is less than the predetermined threshold and performing a block floating point addition operation with a lazy update if the exponential difference is greater than the predetermined threshold using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: a processor, and a memory. However, the additional elements of “a processor” and “a memory” is recited at a high-level of generality (i.e., as a generic computer component for executing a series of mathematical operations; and as a generic computer component for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 18 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a processor” and “a memory” is recited at a high-level of generality (i.e., as a generic computer component for executing a series of mathematical operations; and as a generic computer component for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 19-21 recite the same abstract idea as claim 18 by reason of dependence. Further, claim 19 recites further details of the abstract idea of the separate processes “wherein the separate processes are at least one or more of addition processes, subtraction processes, and multiplication processes”; and claim 20 recites further abstract idea of “wherein the predetermined threshold is dynamically determined in a data processing process” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claim 19 does not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 20 recites the following additional elements: an electronic device. Claim 21 recites the following additional elements wherein the plurality of shared exponents comprising exponents of the plurality of data into data fields are stored separately from data fields storing the first and second data. However, the additional elements of “an electronic device” in claim 20 is recited at a high-level of generality (i.e., as a generic computer device including a processor) such that it amounts to no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea. The additional elements of “wherein the plurality of shared exponents comprising exponents of the plurality of data into data fields are stored separately from data fields storing the first and second data” in claim 21 is merely adding an insignificant extra-solution activity. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under step 2B, claims 20 and 21 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “an electronic device” in claim 20 is recited at a high-level of generality (i.e., as a generic computer device including a processor) such that it amounts to no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea. The additional elements of “wherein the plurality of shared exponents comprising exponents of the plurality of data into data fields are stored separately from data fields storing the first and second data” in claim 21 is merely adding an insignificant extra-solution activity. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 12, 14-15, 17 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Dellinger et al. (US 12307217 B1), hereinafter Dellinger, in view of Xi et al. (US 20210064986 A1), hereinafter Xi. Xi is cited in the IDS submitted on 07/12/2022.
Regarding claim 1, Dellinger teaches an electronic device, comprising:
a processor, configured to execute instructions (Dellinger Fig. 3; col 5 lines 31-36; col 7 lines 23-24 and col 11 lines 34-38 “In certain implementations, a programmable circuit is one or more computer circuits programmed to execute a set (or sets) of instructions stored in a ROM or RAM and/or operate according to configuration data stored in a configuration memory”; processor - a host processor 302 and/or a hardware accelerator 304), and
a memory, storing the instructions, which, when executed by the processor, configures the processor to (Dellinger Fig. 3 and col 11 lines 34-38 “In certain implementations, a programmable circuit is one or more computer circuits programmed to execute a set (or sets) of instructions stored in a ROM or RAM and/or operate according to configuration data stored in a configuration memory”):
generate a floating-point representation comprising a sign field, an exponent identifier field, and a mantissa field for each of a plurality of data (Dellinger Fig. 1 step 106; Figs. 4 and 10; and col 3 lines 23-26 “The exponent compression parameters include the number of bits in a compressed exponent ("compressed ebit-width") and the exponent bias ("compressed exponent bias") associated with the compressed exponent”; col 3 lines 49-51 “At block 106, the exponents are compressed according to the current compressed ebit-width and current compressed exponent bias associated with the set”; col 8 lines 11-15 “This potentially "rounded" exponent is used for overflow/underflow detection, as well as being converted to the compressed exponent, by subtracting the bias adjustment factor in register 412 from the 8 exponent bits in register 408 by subtractor circuit 414”; col 8 lines 38-41 and 66-67; col 11 lines 16-27; plurality of data – set of floating-point values; floating-point representation - floating-point format in register 434 which includes a sign field (top portion bit [N-1]), an exponent identifier field (middle portion bits [N-2:M]), and a mantissa field (bottom portion bits [M-1:0]),
perform an operation on the plurality of data using the floating-point representation (Dellinger Fig. 1 step 110 and col 3 line 56 to col 4 line 6 “The set of floating point values having the compressed exponents is provided at block 110 for additional processing according to the application. For example, the additional processing can entail storing the set of floating point values having the compressed exponents in a memory for later decompressing and processing by a tensor processor, or inputting the set of floating point values having the compressed exponents directly to a processor that is configured to process floating point values having the compressed exponents”);
wherein, for each of the plurality of data, the exponent identifier field comprises a respective bit value (Dellinger Fig. 10 and col 11 lines 20-27), and
wherein the floating-point representation reduces a total number of bits required to represent each of the plurality of data in the memory by replacing an exponent field with the exponent identifier field having fewer bits than the exponent field, thereby reducing at least one of memory usage or communication bandwidth of transmitting the plurality of data (Dellinger Figs. 4 and 10 and col 11 lines 20-27 “An uncompressed 8-bit exponent can be compressed into a 4-bit exponent by subtracting the BAF from the 8-bit value”; col 5 lines 52-55 “The compression of the exponents reduces storage requirements of RAM 318 and bandwidth requirements for providing reading the tensors from the RAM for processing the tensor processor 314”).
Dellinger does not explicitly teach store, in the memory, a plurality of shared exponents comprising exponents of the plurality of data into data fields separate from data fields storing the plurality of data; and perform an operation on the plurality of data using the floating-point representation based on the plurality of shared exponents; wherein, for each of the plurality of data, the exponent identifier field comprises a respective bit value that identifies a location of a corresponding shared exponent among the plurality of shared exponents stored in the memory.
However, on the same field of endeavor, Xi discloses storing, in a memory, a plurality of shared exponents comprising exponents of a plurality of data into data fields separate from data fields of the plurality of data; performing an operation on the plurality of data based on the plurality of shared exponents; and wherein, for each of the plurality of data, an exponent identifier field comprises a respective bit value that identifies a location of a corresponding shared exponent among the plurality of shared exponents stored in the memory (Xi Figs. 2-3 and paragraphs [0049-0051, 0055] “the actual number of unique exponent values extracted across all of the parameters is typically one or more orders of magnitude less than the full range of possible exponent values … the number of unique values may not exceed 16 discrete or distinct integer values. In those scenarios, exponent encoder 316 may encode the exponent value set 314 to generate exponent LUT 318 that comprises the unique exponent values (less than 16 values), with the corresponding number of index values. As a result, each parameter's exponent value in this type of scenario may be represented by a 4-bit exponent LUT index value (or less) that identifies the particular exponent value for the parameter … In step 210, the mantissa lookup table, mantissa lookup table index values, exponent lookup table, and exponent lookup table values are provided to at least one processing entity to train the model”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Dellinger and generalize the teaching of Xi and store, in the memory, a plurality of shared exponents comprising exponents of the plurality of data into data fields separate from data fields storing the plurality of data; wherein, for each of the plurality of data, the exponent identifier field identifies a location of a corresponding shared exponent among the plurality of shared exponents stored in the memory and perform the operation on the plurality of data using the floating-point representation based on the plurality of shared exponents in order to store a mapping table of the compressed exponents and the original uncompressed exponents and to reduce storage and bandwidth requirements (Dellinger col 5 lines 52-55; col 11 lines 10-27; Xi paragraphs [0051, 0054]).
Therefore, the combination of Dellinger as modified in view of Xi teaches store, in the memory, a plurality of shared exponents comprising exponents of the plurality of data into data fields separate from data fields storing the plurality of data; and perform an operation on the plurality of data using the floating-point representation based on the plurality of shared exponents; wherein, for each of the plurality of data, the exponent identifier field comprises a respective bit value that identifies a location of a corresponding shared exponent among the plurality of shared exponents stored in the memory.
Regarding claim 3, Dellinger as modified in view of Xi teaches all the limitations of claim 1 as stated above. Further, Dellinger as modified in view of Xi teaches wherein a total number of bits of the exponent identifier field is determined based on total number of shared exponents in the plurality of exponents (Dellinger col 4 line 59 to col 5 line 4 “Continuing the pre-ceding example, the lower_exp=-12 and the upper_exp=-3, and there are 10 exponent values to represent. The 10 values require 4 exponent bits for representation”; Xi paragraph [0051] “exponent encoder 316 may encode the exponent value set 314 to generate exponent LUT 318 that comprises the unique exponent values (less than 16 values), with the corresponding number of index values. As a result, each parameter's exponent value in this type of scenario may be represented by a 4-bit exponent LUT index value (or less) that identifies the particular exponent value for the parameter”).
Regarding claim 4, Dellinger as modified in view of Xi teaches all the limitations of claim 1 as stated above. Further, Dellinger as modified in view of Xi teaches wherein a total number of bits of the exponent identifier field is less than or equal to a total number of bits of each of the plurality of shared exponents (Dellinger col 11 lines 23-25 “An uncompressed 8-bit exponent can be compressed into a 4-bit exponent by subtracting the BAF from the 8-bit value”).
Regarding claim 22, Dellinger as modified in view of Xi teaches all the limitations of claim 1 as stated above. Further, Dellinger as modified in view of Xi teaches wherein values of the shared exponents are stored separately from the exponent identifier field (Xi Fig. 3 and paragraphs [0049-0051])
Regarding claims 12 and 14-15, they are directed to a method that includes substantially the same limitations as the device claims 1 and 3-4 respectively. All steps performed by the method of claims 12 and 14-15 would be practiced by the device of claims 1 and 3-4 respectively. Claims 1 and 3-4 analysis applies equally to claims 12 and 14-15 respectively.
Regarding claim 17, it is directed to a non-transitory computer-readable storage medium storing that, when executed by a processor, causes the processor to perform the operating method of claim 12. All the operations performed in the method of claim 12 would be executed by the device of claim 1. Claim 1 analysis applies equally to claim 17.
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Dellinger in view of Xi as applied to claims 1 and 12 above, and further in view of Langhammer (US 20180081633 A1).
Regarding claim 5, Dellinger as modified in view of Xi teaches all the limitations of claim 1 as stated above.
Dellinger does not explicitly teach wherein the processor is further configured to: determine whether an exponential difference between first data and second data on which the operation is set to be performed, by the processor, among the plurality of data is greater than a predetermined threshold, and perform an operation between the first data and the second data using an operation scheme that is determined based on a result of the determining.
However, on the same field of endeavor, Langhammer discloses determining, by a processor, whether an exponential difference between first data and second data on which an operation is set to be performed is greater than a predetermined threshold and performing an operation between the first data and the second data using an operation scheme that is determined based on a result of the determining (Langhammer Fig. 4 and paragraph [0046] “adder 200 may include exponent/mantissa comparison and near/far path routing circuitry 400 that receives inputs A and B (i.e., the exponents and mantissa of numbers A and B), compares the exponents and also mantissas of inputs A and B, and splits the numbers into a "near" path and a "far" path. If the difference of the exponents is equal to zero or one, then the near path may be used (where the value of "1" is set as the predetermined threshold value). In the near path, typically only subtraction occurs … On the other hand, if the difference of the exponents is greater than one or for a true addition operation, then then far path may be taken ( e.g., the far path may handle addition for the near values as well)”; exponential difference - difference of the exponents; first data and second data - inputs A and B; predetermined threshold - predetermined threshold value; operation scheme – addition and/or subtraction).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Dellinger using Langhammer and generalize the teaching of Langhammer by determining whether an exponential difference between first data and second data on which the operation is set to be performed is greater than a predetermined threshold and performing an operation between the first data and the second data using an operation scheme that is determined based on a result of the determining in order to support a wide range of intermediate floating-point sizes such as FP32, FP16, FP17, FP18, FP20, etc., without incurring large area penalties (Langhammer paragraph [0044]) which may be used in a neural network application.
Therefore, the combination of Dellinger as modified in view of Xi and Langhammer wherein the processor is further configured to: determine whether an exponential difference between first data and second data on which the operation is set to be performed, by the processor, among the plurality of data is greater than a predetermined threshold, and perform an operation between the first data and the second data using an operation scheme that is determined based on a result of the determining..
Regarding claim 16, it is directed to a method that includes substantially the same limitations as the device of claim 5. All steps performed by the method of claim 16 would be practiced by the device of claim 5. Claim 5 analysis applies equally to claim 16.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Dellinger in view of Xi and Langhammer as applied to claim 5 above, and further in view of Pangal et al. (US 20020184285 A1), hereinafter Pangal.
Regarding claim 6, Dellinger as modified in view of Xi and Langhammer teaches all the limitations of claim 5 as stated above. Further, Dellinger as modified in view of XI and Langhammer teaches wherein, the processor is configured to, in response to the exponential difference being less than the predetermined threshold, perform the operation between the first data and the second data (Langhammer Fig. 4 and paragraph [0046] “If the difference of the exponents is equal to zero or one, then the near path may be used (where the value of "1" is set as the predetermined threshold value). In the near path, typically only subtraction occurs”).
Dellinger does not explicitly teach wherein, the processor is configured to, in response to the exponential difference being less than the predetermined threshold, perform the operation between the first data and the second data by separating an exponent of the first data and an exponent of the second data and a mantissa of the first data and a mantissa of the second data from each other.
However, on the same field of endeavor, Pangal discloses performing an operation between a first data and a second data by separating an exponent of the first data and an exponent of the second data and a mantissa of the first data and a mantissa of the second data from each other (Pangal Fig. 4 and paragraphs [0027 and 0028]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Dellinger in view of Xi and Langhammer using Pangal and configure at least the subtraction circuit 410 or the routing circuitry 400 to separate the exponents and mantissas of inputs A and B and input the exponents to an exponent processing path and the mantissas in a mantissa processing path because floating-point circuitry normally includes a separate data path for processing the exponents and the mantissas (Pangal Fig. 4 and paragraphs [0027-0028]).
Therefore, the combination of Dellinger as modified in view of Xi, Langhammer and Pangal teaches wherein, the processor is configured to, in response to the exponential difference being less than the predetermined threshold, perform the operation between the first data and the second data by separating an exponent of the first data and an exponent of the second data and a mantissa of the first data and a mantissa of the second data from each other.
Allowable Subject Matter
Claims 7-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-21 would be allowable if rewritten to overcome the 35 U.S.C. 101 and 35 U.S.C. 112(b) rejections discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
In addition to the statement of reasons for the indication of allowable subject matter provided in the non-final office action, none of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claims “performing, at a second time, by the processor, separate processes on the exponents of the first data and the second data, and the mantissas of the first data and the second data, with the block floating point operation and a lazy update” where the term “lazy update” is interpreted as defined in paragraph [0075].
Response to Arguments
Applicant’s arguments, see remarks page 9-12, filed 03/10/2026, with respect to the 35 U.S.C. 101 rejection of claims 1, 3-12 and 14-17 have been fully considered and are persuasive. The 35 U.S.C. 101 rejection of claims 1, 3-12 and 14-17 has been withdrawn.
Applicant's arguments, see remarks page 9-12, filed 03/10/2026, with respect to the 35 U.S.C. 101 rejection of claims 18-21 have been fully considered but they are not persuasive.
Regarding claims 18-21, Applicant relied on same arguments for claim 1. However, the alleged improvements are not reflected in claim 18. Claim 18 does not recite the features of generating a floating-point representation with a reduced total number of bits required to represent the original floating-point data by replacing an exponent field of the original floating-point data with an exponent identifier field having fewer bits than the exponent field. There is no indication that the exponent identifier fields in the first data and the second data comprises less bits than the exponent field. Therefore, the alleged improvement of reducing memory consumption in data storage, decreasing bandwidth requirements is not reflected in the claim. Perhaps Applicant may want to amend claim 18 to include the features similar to claim 1.
Applicant’s arguments, see remarks page 9-12, filed 03/10/2026, with respect to the 35 U.S.C. 102(a)(2) rejection of claims 1, 3-4, 12, 14-17 and 17 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of amendments made and previously cited prior art references.
Applicant amended claim 1 to recite “the exponent identifier field comprises a bit value that identifies a location of a corresponding shared exponent among the plurality of shared exponents stored in the memory” and argues the following:
1.) Dellinger discusses compressing the exponents of individual floating-point values by reducing their bit-width and storing the compressed exponent as part of each floating-point value (sign, compressed exponent, mantissa). However, there is no discussion in Dellinger regarding (1) multiple shared exponents stored separately in memory that multiple data values reference, (2) storing exponents in separate data fields from the data itself, and (3) an exponent identifier field that contains a bit value that identifies a location of one of several shared exponents stored in the memory.
Response: Examiner agrees. However, Xi discloses these features. Paragraph [0051] of Xi discloses generating a LUT comprising 16 exponent values indexed by a 4-bit exponent index value. Further, paragraph [0001] of Xi discloses that neural network includes millions or even billion of parameters. Therefore, having 16 exponent values for the neural network parameters would result in each exponent being shared by multiple parameters. Further, as shown in Fig. 3, the exponents are stored in separate data field (i.e., in the exponent LUT 318). With respect to Dellinger, the exponent index is equivalent to the 4-bit compressed exponents (0001-1111) in the right column of Fig. 10 while the exponent LUT is equivalent to the 8-bit uncompressed exponents in the same rows in the left column. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to combine the teaching of Dellinger and Xi and store, in a LUT memory, a plurality of shared exponents comprising the original exponents of the plurality of data (i.e., 01101010-01111000) separate from data fields storing the plurality of data wherein, for each of the plurality of data, the exponent identifier field (0001-1111) identifies a location of a corresponding shared exponent among the plurality of shared exponents (01101010-01111000) stored in the memory in order to store a mapping/conversion table of the compressed exponents and the original uncompressed exponents to reduce storage and bandwidth requirements and to be able to decompress and/or recover the original uncompressed exponents from the compressed exponents. Therefore, the combination of Dellinger as modified in view of Xi fairly teaches the claimed “the exponent identifier field comprises a bit value that identifies a location of a corresponding shared exponent among the plurality of shared exponents stored in the memory” as recited in claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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