DETAILED ACTION
This office action addresses Applicant’s response filed on 12 June 2026. Claims 1, 2, 4-12, and 14-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, 4-12, and 14-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 11 have been amended to recite, “the PNR edge identifiers comprise at least one PNR identifier that defines a shared-power configuration in which the second standard cell is offset by one contacted poly pitch (CPP) relative to the first standard cell such that corresponding transistor source connections are physically merged across abutting cell boundaries”, which is not supported by the originally-filed disclosure. It is not clear which embodiments Applicant intends the recited offset to refer to, as Applicant does not cite specific portions of the disclosure for support, but Applicant states in the accompanying Remarks that “Morton does not disclose positioning a second standard cell offset by one CPP relative to a first standard cell” (emphasis added), indicating that the offset is in positioning between the first and second cells. However, there is no disclosed embodiment where cells are positioned with a 1 CPP offset while also physically merging transistor source connections across abutting cell boundaries, as claimed. It is not clear how the disclosed cell arrangements could physically satisfy all of the recited limitations, since the 1 CPP positioning offset would seem to preclude merged/shared connections across abutting cell boundaries.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-9, 11, 12, and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morton (US 2006/0190893) in view of Ramesh (US 6,980,462), Higman (US 2008/0005717), Do (US 2021/0104550), and Hou (2010/0269081).
Regarding claim 1, Morton discloses an integrated circuit comprising: a first standard cell fabricated based on a Place and Route (PNR) library of standard cells (¶¶8-10), the first standard cell comprising: a cell boundary that includes a first edge and a second edge that is opposite the first edge (Figs. 3A-C); and at least one transistor source electrode that is physically shared between the first standard cell and a second standard cell based on cell configuration information that indicates a power connection configuration used with the second standard cell based on the first standard cell being placed next to the second standard cell in a layout in a PNR environment, wherein the shared transistor source electrode is outside the cell boundary of the first standard cell (Figs. 3A-C, 4, and 5; ¶¶8-10); and the cell configuration information comprises PNR edge identifiers, comprising at least one PNR edge identifier, for at least one of the first edge and the second edge that define a shared-power connection (Figs. 4 and 5; ¶26), and the PNR edge identifiers comprise at least one PNR identifier that defines a shared-power configuration (Figs. 4 and 5; ¶26) in which the second standard cell is offset by one contacted poly pitch (CPP) relative to the first standard cell such that corresponding transistor source connections are physically merged across abutting cell boundaries (Figs. 3A-C and 4, cell 12 is one CPP narrower than 32, and they share source connections across their boundary).
Morton does not appear to explicitly disclose the shared transistor source electrode being physically located outside the cell boundary of the first standard cell. Ramesh discloses these limitations (col. 17 line 64 to col. 18 line 16). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Morton and Ramesh, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of allowing shared electrodes to be offset from the cell boundary in order to further reduce required cell area. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Morton discloses cell libraries and layouts in which adjacent cells can share electrodes at their boundaries. Ramesh teaches that cells can also share electrodes offset from the boundary, which permits further reduction in cell area. The teachings of Ramesh are directly applicable to Morton in the same way, so that Morton would similarly use cells that share electrodes offset from cell boundaries, to further reduce cell area.
If Morton is found to be unclear regarding PNR edge identifiers, comprising at least one PNR edge identifier for at least one of the first edge and the second edge that define a shared-power connection, and the PNR edge identifier comprising at least one PNR identifier that defines a shared-power configuration, Higman discloses the same (¶¶27-28). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Morton, Ramesh, and Higman, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of ensuring correct placement of cells. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Morton discloses cell libraries and layouts in which adjacent cells can share electrodes at their boundaries. Higman teaches that the cell boundaries have assigned edge codes that indicate abutment compatibility. The teachings of Higman are directly applicable to Morton in the same way, so that Morton would similarly use edge codes to ensure that cells are placed next to compatible cells.
If Morton is found to be unclear regarding the second standard cell being offset by one CPP relative to the first standard cell such that corresponding transistor source connections are physically merged across abutting cell boundaries, Do discloses the same (Fig. 12, S300-S400). Furthermore (or alternatively), these limitations directly result from the combination of Morton and Ramesh, because Morton teaches cell width reduction due to sharing source connections, and Ramesh teaches that the shared source connection is in the adjacent cell rather than at the boundary, which would further reduce the cell width by the half pitch occupied by half of the source connection in the half-and-half sharing arrangement, as illustrated by Hou (Figs. 5 and 6).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Morton, Ramesh, Higman, Do, and Hou, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of reducing cell area by standard cell width intervals. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Morton discloses cell libraries and layouts in which adjacent cells can share connections across their boundaries. Ramesh teaches that cells can also share connections offset from the boundary that are in the adjacent cell. Do teaches that such shared connections allow offsetting the cell by 1 CPP. Furthermore, persons having ordinary skill in the art, reading Morton and Ramesh, would clearly recognize that the sharing of connections as taught by Morton and Ramesh would result in a cell offset by 1 CPP, as taught by Hou. The teachings of Ramesh, Do, and Hou are directly applicable to Morton in the same way, so that Morton would similarly share connections that are in an adjacent cell, to further reduce cell area by a standard interval.
Regarding claim 2, Morton discloses that the cell configuration information indicates that the power connection configuration for at least one of the first edge and the second edge is outside the cell boundary for the first standard cell (Figs. 3A-C, 4, and 5).
Regarding claim 5, Morton discloses that when the first standard cell is placed in the layout in the PNR environment, the cell boundary of the first standard cell abuts a cell boundary of the second standard cell (Figs. 4 and 5).
Regarding claim 6, Morton discloses that the cell configuration information indicates that the power connection configuration for at least one of the first edge and the second edge is inside a cell boundary for the second standard cell when the first standard cell is placed next to the second standard cell (Figs. 3A-C, 4, and 5).
Regarding claim 7, Morton discloses that the cell configuration information indicates that the power connection configuration for the first standard cell is outside of a cell boundary of the first standard cell (Figs. 3A-C, 4, and 5).
Regarding claims 8 and 9, Morton discloses that the library of standards cells includes at least one variant of the first standard cell that is equivalent in function and drive strength to the first standard cell and includes cell configuration information for the variant of the first standard cell that provides a power configuration that is different from the power configuration of the first standard cell, wherein the cell configuration information for the variant of the first standard cell indicates the power configuration to be inside a cell boundary of the variant of the first standard cell (Figs. 3A-C, upper cells).
Claims 11, 12, and 15-19 are directed to a method of fabricating the integrated circuit of claims 1, 2, and 5-9, recite substantially identical limitations, and are rejected under the same reasoning. Morton discloses the claimed PNR library of standard cells (¶¶1, 10).
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morton in view of Ramesh, Higman, Do, Hou, Lin (US 2020/0019667) and Chen (US 2021/0407985).
Regarding claims 4 and 14, Morton does not appear to explicitly disclose that when the first standard cell is placed in the layout in the PNR environment, a minimum distance between an outside edge of the first standard cell and an outside edge of the second standard cell is one Contacted Poly Pitch (CPP) for the shared power connection configuration. However, persons having ordinary skill in the art would recognize that the claimed features are implied, if not inherent, given that CPP is the minimum distance between gate patterns in a cell, and standard cell dimensions are defined in multiples of CPP, as disclosed by Lin (¶38). Thus, it would have been obvious or necessary for the minimum spacing between outside edges of two adjacent cells to be the minimum unit of cell distance measurement. As an illustrative example, Chen shows a row of cells where outside edges of adjacent cells are separated by one CPP (Fig. 4).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Morton, Ramesh, Higman, Do, Hou, Lin, and Chen, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of defining standard cell dimensions using conventional CPP for convenience/compatibility with industry standards and so that cell designs and placements are based on actual legal minimum physical spacing of cell features as the reference unit. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Morton discloses standard cells having outside edges, and that share power connections. Persons having ordinary skill in the art would recognize that the minimum distance between the outside edge of one cell and the outside edge of another cell is necessarily or obviously one CPP, since CPP is the minimum distance between gate patterns in the cell which defines standard cell dimensions, as taught by Lin and Chen. The teachings of Lin and Chen are directly applicable to Morton in the same way, so that Morton would similarly use the conventional reference unit of CPP for minimum cell dimensions to define the minimum spacing between the outside edges of cells for convenience/compatibility with industry standards and so that cell designs and placements are based on actual legal minimum physical spacing of cell features as the reference unit.
Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morton in view of Ramesh, Higman, Do, Hou, and Kamal (US 2014/0124868).
Regarding claims 10 and 20, Morton does not appear to explicitly disclose that the cell configuration information for the first standard cell indicates that one of the first edge or the second edge is configured as a dummy gate. Kamal discloses these limitations (¶30). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Morton, Ramesh, Higman, Do, Hou, and Kamal, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of improving performance while avoiding extraneous active devices. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Morton discloses standard cells with shared edge features. Kamal teaches that such cells should have extended diffusion regions with dummy gates at the cell edge to improve performance without creating extraneous active devices (¶18). The teachings of Kamal are directly applicable to Morton in the same way, so that Morton would similarly use dummy gates to allow improved performance through extended diffusion regions without creating extraneous active devices.
Response to Arguments
Applicant's arguments filed 12 June 2026 have been fully considered but they are not persuasive.
The claims have been amended to recite, “the PNR edge identifiers comprise at least one PNR identifier that defines a shared-power configuration in which the second standard cell is offset by one contacted poly pitch (CPP) relative to the first standard cell such that corresponding transistor source connections are physically merged across abutting cell boundaries”, which Applicant asserts is not taught by the prior art of record. Remarks 7. The examiner disagrees. Morton’s Figs. 3A-C and 4 clearly teach the shared-power configuration in which the second standard cell is offset by one CPP relative to the first standard cell such that corresponding transistor source connections are physically merged across abutting cell boundaries. In particular, the figures clearly show that cell 12 is offset one CPP from cell 32 (12 has one fewer poly pitches than 32, similar to Fig. 4 of Applicant’s drawings), and that the cells have a shared-power configuration with source connections physically merged across the abutting cell boundaries (Fig. 4’s adjacent cells all share merged source connections across their abutting boundaries). Morton (Figs. 4 and 5; ¶26) and Higman (¶¶27-28) also teach the PNR edge identifiers that define the edge compatibility for the shared-power configuration.
Persons having ordinary skill in the art would also recognize that the application of Ramesh to Morton further satisfies the claim limitations because having the shared connection be within an adjacent cell rather than at the boundary would allow a further half CPP offset of the second cell boundary since it would not longer need to include its half of the shared connection. Thus, the combination of Morton, Ramesh, and Higman clearly disclose the shared-power arrangement between abutting first and second cells, where the shared connection is in the first cell such that the second cell is offset by 1 CPP due to not including the connection within its boundary (as taught by Morton and Ramesh), and the PNR edge identifiers define the edge compatibility between such cells (as taught by Morton and Higman). Nevertheless, solely in the interest of advancing prosecution, Do and Hou and cited to provide further supporting evidence of the limitations at issue.
Applicant asserts that the examiner relies on impermissible hindsight, because “Morton does not disclose the claimed CPP-offset physical merging arrangement, Ramesh does not address PNR-defined standard-cell placement configurations, and Higman does not disclose physical merging of transistor source connections resulting from a one-CPP offset placement relationship.” Remarks 8. The examiner disagrees. Even assuming, arguendo, that the quoted lack of teachings is correct, asserting that each of the references lacks a different teaching is, at best, improper piecemeal analysis of the references rather than evidence of impermissible hindsight in combining the references. If references failing to teach a specific limitation were sufficient to show impermissible hindsight, essentially no § 103 rejections would be proper, since they generally refer to additional references to teach limitations that other references lack.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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24 August 2026
/ARIC LIN/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
