DETAILED ACTION
This office action addresses Applicant’s response filed on 22 January 2026. Claims 1, 2, 4-12, and 14-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-9, 11, 12, and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morton (US 2006/0190893) in view of Ramesh (US 6,980,462) and Higman (US 2008/0005717).
Regarding claim 1, Morton discloses an integrated circuit comprising: a first standard cell fabricated based on a Place and Route (PNR) library of standard cells (¶¶8-10), the first standard cell comprising: a cell boundary that includes a first edge and a second edge that is opposite the first edge (Figs. 3A-C); and at least one transistor source electrode that is physically shared between the first standard cell and a second standard cell based on cell configuration information that indicates a power connection configuration used with the second standard cell based on the first standard cell being placed next to the second standard cell in a layout in a PNR environment, wherein the shared transistor source electrode is outside the cell boundary of the first standard cell (Figs. 3A-C, 4, and 5; ¶¶8-10); and the cell configuration information comprises PNR edge identifiers for at least one of the first edge and the second edge that define a shared-power connection (Figs. 4 and 5; ¶26).
Morton does not appear to explicitly disclose the shared transistor source electrode being physically located outside the cell boundary of the first standard cell. Ramesh discloses these limitations (col. 17 line 64 to col. 18 line 16). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Morton and Ramesh, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of allowing shared electrodes to be offset from the cell boundary in order to further reduce required cell area. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Morton discloses cell libraries and layouts in which adjacent cells can share electrodes at their boundaries. Ramesh teaches that cells can also share electrodes offset from the, which permits further reduction in cell area. The teachings of Ramesh are directly applicable to Morton in the same way, so that Morton would similarly use cells that share electrodes offset from cell boundaries, in order to further reduce cell area.
If Morton is found to be unclear regarding PNR edge identifiers for at least one of the first edge and the second edge that define a shared-power connection, Higman discloses the same (¶¶27-28). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Morton, Ramesh, and Higman, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of ensuring correct placement of cells. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Morton discloses cell libraries and layouts in which adjacent cells can share electrodes at their boundaries. Higman teaches that the cell boundaries have assigned edge codes that indicate abutment compatibility. The teachings of Higman are directly applicable to Morton in the same way, so that Morton would similarly use edge codes to ensure that cells are placed next to compatible cells.
Regarding claim 2, Morton discloses that the cell configuration information indicates that the power connection configuration for at least one of the first edge and the second edge is outside the cell boundary for the first standard cell (Figs. 3A-C, 4, and 5).
Regarding claim 5, Morton discloses that when the first standard cell is placed in the layout in the PNR environment, the cell boundary of the first standard cell abuts a cell boundary of the second standard cell (Figs. 4 and 5).
Regarding claim 6, Morton discloses that the cell configuration information indicates that the power connection configuration for at least one of the first edge and the second edge is inside a cell boundary for the second standard cell when the first standard cell is placed next to the second standard cell (Figs. 3A-C, 4, and 5).
Regarding claim 7, Morton discloses that the cell configuration information indicates that the power connection configuration for the first standard cell is outside of a cell boundary of the first standard cell (Figs. 3A-C, 4, and 5).
Regarding claims 8 and 9, Morton discloses that the library of standards cells includes at least one variant of the first standard cell that is equivalent in function and drive strength to the first standard cell and includes cell configuration information for the variant of the first standard cell that provides a power configuration that is different from the power configuration of the first standard cell, wherein the cell configuration information for the variant of the first standard cell indicates the power configuration to be inside a cell boundary of the variant of the first standard cell (Figs. 3A-C, upper cells).
Claims 11, 12, and 15-19 are directed to a method of fabricating the integrated circuit of claims 1, 2, and 5-9, recite substantially identical limitations, and are rejected under the same reasoning. Morton discloses the claimed PNR library of standard cells (¶¶1, 10).
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morton in view of Ramesh, Higman, Lin (US 2020/0019667) and Chen (US 2021/0407985).
Regarding claims 4 and 14, Morton does not appear to explicitly disclose that when the first standard cell is placed in the layout in the PNR environment, a minimum distance between an outside edge of the first standard cell and an outside edge of the second standard cell is one Contacted Poly Pitch (CPP) for the shared power connection configuration. However, persons having ordinary skill in the art would recognize that the claimed features are implied, if not inherent, given that CPP is the minimum distance between gate patterns in a cell, and standard cell dimensions are defined in multiples of CPP, as disclosed by Lin (¶38). Thus, it would have been obvious or necessary for the minimum spacing between outside edges of two adjacent cells to be the minimum unit of cell distance measurement. As an illustrative example, Chen shows a row of cells where outside edges of adjacent cells are separated by one CPP (Fig. 4).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Morton, Ramesh, Higman, Lin, and Chen, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of defining standard cell dimensions using conventional CPP for convenience/compatibility with industry standards and so that cell designs and placements are based on actual legal minimum physical spacing of cell features as the reference unit. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Morton discloses standard cells having outside edges, and that share power connections. Persons having ordinary skill in the art would recognize that the minimum distance between the outside edge of one cell and the outside edge of another cell is necessarily or obviously one CPP, since CPP is the minimum distance between gate patterns in the cell which defines standard cell dimensions, as taught by Lin and Chen. The teachings of Lin and Chen are directly applicable to Morton in the same way, so that Morton would similarly use the conventional reference unit of CPP for minimum cell dimensions to define the minimum spacing between the outside edges of cells for convenience/compatibility with industry standards and so that cell designs and placements are based on actual legal minimum physical spacing of cell features as the reference unit.
Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morton in view of Ramesh, Higman, and Kamal (US 2014/0124868).
Regarding claims 10 and 20, Morton does not appear to explicitly disclose that the cell configuration information for the first standard cell indicates that one of the first edge or the second edge is configured as a dummy gate. Kamal discloses these limitations (¶30). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Morton, Ramesh, Higman, and Kamal, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of improving performance while avoiding extraneous active devices. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Morton discloses standard cells with shared edge features. Kamal teaches that such cells should have extended diffusion regions with dummy gates at the cell edge to improve performance without creating extraneous active devices (¶18). The teachings of Kamal are directly applicable to Morton in the same way, so that Morton would similarly use dummy gates to allow improved performance through extended diffusion regions without creating extraneous active devices.
Response to Arguments
Applicant's arguments filed 22 January 2026 have been fully considered but they are not persuasive.
Applicant asserts that Morton’s “U” and “S” identifiers “are merely descriptive annotations of example cell edges and regions in Morton's figures, not tool-interpretable identifiers that a place-and-route system uses to enforce abutment and boundary rules.” Remarks 7. The examiner disagrees. References are evaluated on the basis of what they reasonably disclose and suggest to persons having ordinary skill in the art. Morton illustrates standard cell placements where edges are identified as “U” or “S” so that compatible edges are abutted, which would suggest to persons having ordinary skill in the art to include such indicators in the cell information so that that the cells can be placed correctly. To do otherwise would allow illegal cell placements, in contravention of what Morton has explicitly disclosed. Nevertheless, in the interest of advancing prosecution, Higman is cited to provide further disclosure of the limitations at issue.
Applicant asserts that Ramesh fails to teach “at least one transistor source electrode”, that memory cells are not standard cells, and that memory cells are not part of PNR standard-cell libraries. Remarks 8. However, Applicant cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Here, the claims are rejected over a combination of Morton and Ramesh. As discussed in the rejection, Morton already teaches the first standard cell fabricated based on a place and route library of standard cells and the transistor source electrodes (Figs. 3A-3C; ¶¶8-10), so regardless of whether Ramesh teaches place and route libraries of standard cells, the combination of Morton and Ramesh clearly teaches those features. Furthermore, as also discussed in the rejection, Morton already teaches the transistor source electrode outside of the cell boundary and shared with adjacent cells (Figs. 3A-3C, 4, and 5; ¶¶8-10), analogously to Applicant’s invention. Ramesh teaches that in addition to sharing electrodes at the boundary, shared electrodes can be offset from the boundary and inside the adjacent cell (col. 17, line 55 to col. 18, line 16); thus, Ramesh is directly applicable to Morton’s arrangement of a shared electrode at the cell boundary. The combination of Morton with Ramesh would suggest to persons having ordinary skill in the art to modify Morton’s standard cells’ shared source electrodes so that Morton’s shared electrodes are offset from the cell boundary and inside an adjacent cell.
Standard cells and memory cells are also not as disparate as Applicant asserts; for example, US 7,192,400 to Lien, col. 2, lines 13-15, states “cells of a standard cell library that includes memory cells”; US 2008/0116397 to Yoshida, ¶16, states “The electronic circuit block is a cell in the standard cell library including an inverter, a flip-flop, a logic gate or a memory cell”; and US 3,796,930 to Page, col. 3, lines 9-11, states “The source and drain electrodes, 14 and 16 respectively, may consist of any metal which forms an ohmic contact with the semiconductor material layer 18.” But again, even assuming Applicant was completely correct about the differences between standard cells and memory cells, the rejection applies Ramesh’s teachings of a shared electrode being located in an adjacent cell to Morton’s standard cells having shared electrodes, and does not rely on equating memory cells with standard cells.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
9 March 2026
/ARIC LIN/ Examiner, Art Unit 2851