Prosecution Insights
Last updated: July 17, 2026
Application No. 17/863,920

ELECTRONIC DEVICE INTENDED TO CONNECT A FIRST ELECTRONIC COMPONENT TO A SECOND ELECTRONIC COMPONENT, SYSTEM COMPRISING SUCH A DEVICE AND METHODS MAKING IT POSSIBLE TO OBTAIN SUCH A DEVICE

Final Rejection §102§103
Filed
Jul 13, 2022
Priority
Jul 15, 2021 — FR 2107657
Examiner
WARTALOWICZ, PAUL A
Art Unit
1735
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Commissariat A' L' Energie Atomique Et Aux Energies Alternatives
OA Round
2 (Final)
64%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 64% of resolved cases
64%
Career Allowance Rate
541 granted / 844 resolved
-0.9% vs TC avg
Strong +18% interview lift
Without
With
+18.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
29 currently pending
Career history
871
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
77.6%
+37.6% vs TC avg
§102
1.0%
-39.0% vs TC avg
§112
10.7%
-29.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 844 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 01/29/2026 have been fully considered but they are not persuasive. Applicant argues that that the office actions own assumed material mapping (niobium for the traces; “soft superconducting” tin for adhesion, and a solder bump that may include tin necessarily produces a sequence of SC1/SC2/SC2/SC2/SC1. However, the solder bump of Bunyk does not necessarily include tin. See Bunyk at para. 0143. The solder bump can comprise lead and as such the sequence can include SC1/SC2/SC3/SC2/SC1 as in niobium/tin/lead/tin/niobium. Applicant argues that Bunyk does not disclose a conductor track intentionally formed from a strict SC1/SC2 alternation that produces acoustic mismatch between each adjacent pair of sections as claimed. However, as discussed above, it appears that the disclosure of Bunyk meets the limitation of acoustic mismatch as the adjacent sections comprise different superconducting materials. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 10-11, 14 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Bunyk (US 20140246763). Bunyk teaches an electronic device comprising a first surface and a second surface opposite the first surface (chip module 860 comprises a first and second surface; para. 0059) and intended to connect a first electronic component to a second electronic component located on the first surface by at least one conductor track (the conductive track is formed by elements 828, 838, 848, 834, 824 and internal connections within chips 801, 802 and substrate 870; para. 0059 -0060) the at least one conductor track comprising a plurality of first sections in a first superconducting material and a plurality of second sections in a second superconducting material different from the first superconducting material (the conductive track comprises a plurality of sections arranged one after the other so as to form the conductive track, at least each of the elements 828, 838, 848, 834, 824 is individually such a section; lead solder bump (first superconductor) and niobium layer (second superconductor); para. 0043, 0052, 0059-0060), the track being formed by alternating first and second sections in the track (sections 824, 828, 834, 848 make up the conductive track; fig. 8, para. 0059). Additionally, it appears that there is an acoustic mismatch between the sections as the sections comprise different superconductors (including lead and niobium as described above). Regarding claims 10-11, Bunyk teaches lead solder bump (first superconductor) and niobium layer (second superconductor); para. 0043, 0052, 0059-0060). Both of these superconductors have a critical temperature greater than 4 K. Regarding claim 14, Bunyk teaches two electric components attached to a substrate via a conducting track (fig. 8). Therefore, the two electric components are attached (indirectly through the substrate) via the conductor track. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bunyk (US 20140246763) in view of Quintero Perez (hereinafter “Perez”; US 2023/0147168). Bunyk teaches a product as described above in claim 1, but fails to teach the device comprises an alternating of two types of layers, first soft layer of dielectric having a first young’s modulus and second hard layer of a second dielectric material having a youngs modulus greater than the first youngs modulus. Perez, however, teaches superconductor device (abstract) wherein there are alternating dielectric materials including a first layer of silicon oxide (para. 0153) and a second dielectric layer of aluminum oxide with an electronic formed in the SiO2 (para. 0151-0156). Therefore, it would have been obvious to one of ordinary skill in the art to provide alternating dielectric materials including a first layer of silicon oxide (para. 0153) and a second dielectric layer of aluminum oxide with an electronic formed in the SiO2 in Bunyk in order to provide a configuration known in the art for superconductor electronic devices as taught by Perez. Additionally, SiO2 has a young’s modulus that is less than aluminum oxide such that the first layer is a soft layer and the second layer is a hard layer. Claim(s) 3, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bunyk (US 20140246763) in view of (Lin US 2010/0165585) Bunyk teaches a product as described above in claim 1, but fails to teach the pair includes first superconducting material is niobium and the second superconducting material is titanium nitride. Lin, however, teaches a chip package device comprising a bump pad (abstract; para. 0008) wherein the bump pad comprises titanium nitride for the purpose of providing an adhesion layer to the solder (para. 0256). Therefore, it would have been obvious to one of ordinary skill in the art to provide the bump pad of Bunyk comprises titanium nitride in order to provide an adhesion layer to the solder as taught by Lin. Additionally, it appears that the pair of niobium (Bunyk) and titanium nitride (Lin) meets the claim limitation. Regarding claim 12, as the pair of niobium (Bunyk) and titanium nitride (Lin) is substantially similar as the pair claimed, it appears that the acoustic mismatch would overlap with the claim range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. Claim(s) 13, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bunyk. Bunyk teaches a product as described above in claim 1, but fails to teach that the conductor track comprises at least 100 acoustic mismatching interfaces. However, it would have been obvious to provide multiple interfaces for multiple effect in the absence of unexpected results. See MPEP 2144.04 (VI) (B). Regarding claim 14, Bunyk teaches connecting two electronic devices on different substrates (see fig. 8). However, connecting two devices on a same substrate would be obvious as rearrangement of parts. MPEP 2144.04 (VI) (C). Allowable Subject Matter Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: regarding claim 4, the prior art of record fails to teach or suggest a plurality of routing levels connected by vias, the at least one conductor track being formed on a portion of at least the plurality of routing levels and the material used for the sections of a given routing level being different from the material used for the sections of the routing level immediately above and below, each via being made of one of the materials of the routing level among the two routing levels that it connects in combination with the limitations of claim 1. Regarding claim 5, the prior art fails to teach or suggest the device comprising a plurality of routing levels, the routing levels being connected together by vias, the at least one conductor track being formed on a portion of at least of the plurality of routing levels, the plurality of first sections being formed in a portion at least of the routing levels of the plurality of routing levels, each second section forming a via that connects a first section of the plurality of first sections of a routing level to a first section of the plurality of first sections of a routing level located above or below in combination with the limitations of claim 1. Specifically, US 2013/0026618 teaches routing and vias in a substrate (fig. 6) but fails to specifically teach least one conductor track being formed on a portion of at least of the plurality of routing levels, the plurality of first sections being formed in a portion at least of the routing levels of the plurality of routing levels, each second section forming a via that connects a first section of the plurality of first sections of a routing level to a first section of the plurality of first sections of a routing level located above or below. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A WARTALOWICZ whose telephone number is (571)272-5957. The examiner can normally be reached Monday-Friday 9 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Keith Walker can be reached at 571-272-3458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PAUL A WARTALOWICZ/Primary Examiner, Art Unit 1735
Read full office action

Prosecution Timeline

Jul 13, 2022
Application Filed
Oct 30, 2025
Non-Final Rejection mailed — §102, §103
Jan 29, 2026
Response Filed
Jun 10, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
64%
Grant Probability
82%
With Interview (+18.4%)
3y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 844 resolved cases by this examiner. Grant probability derived from career allowance rate.

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