Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/13/2022, and 02/20/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements mentioned above are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitations of: “internal storage configured to store data to perform a neural network operation”, and “perform an operation between the stored data and main data”. It is unclear if the internal storage is meant to store both the main data and the data referred to as “stored data”, or if the main data is supplied, or generated elsewhere in the circuitry.
Furthermore, claim 1 recites the limitation of: “and a controller configured to control the ALU, the first multiplexer, and the second multiplexer based on the operation control signal, the reset signal, and the phase signal.” It is unclear if each of the components such as the ALU, and the first and second multiplexers are controlled by all three signals, the control signal, reset signal and phase signal, or if the ALU is controlled solely by the operation control signal, the first multiplexer is controlled by the reset signal, and the second multiplexer is controlled by the phase signal. For purposes of examination, the Examiner interprets the limitation as: “and a controller configured to control the ALU, the first multiplexer, and the second multiplexer based on the operation control signal, the reset signal, and the phase signal, respectively.”
Claims 2-9 inherit the deficiencies of claim 1 based on dependence.
Regarding claim 2, claim 2 recites the limitation of: “a first register configured to receive the data from the internal storage and store the received data”. Claim 2 is dependent on claim 1, claim 1 discloses two different sets of data, main data, and data referred to as “stored data”. It is unclear which of the sets of data is meant to be received by the first register, or if it is meant to be understood as both sets of data. For purposes of examination, the Examiner interprets the data of this limitation in claim 2 to be the “stored data” of claim 1.
Regarding claim 4, claim 4 recites the limitation of: “internal storage is further configured to store the data based on a channel index that indicates a position of an output tensor of the data”. Claim 4 is dependent on claim 1, claim 1 discloses two different sets of data, main data and data referred to as “stored data”. It is unclear if the data referred to in this limitation of claim 4 is meant to be understood as the “stored data”, “main data”, or both. For purposes of examination, the Examiner interprets the limitation to be about the data referred to as “stored data”.
Regarding claim 7, claim 7 recites the limitation of: “an adder tree configured to perform an addition of the output of the ALU.” The limitation is unclear what is being added to the ALU output. It is unclear if there is another operand added to the ALU result, or if it is meant to be understood as multiple ALU results over time are put into the adder tree and accumulated.
Claim 8 inherits the deficiency of claim 7 based on dependence.
Regarding claim 9, claim 9 recites the limitation of: “an output of an adder tree which is configured to perform an addition of the output of the ALU.” The limitation is unclear what is being added to the ALU output. It is unclear if there is another operand added to the ALU result, or if it is meant to be understood as multiple ALU results over time are put into the adder tree and accumulated.
Regarding claim 10, claim 10 recites the limitations of: “storing data to perform a neural network operation”, and “generating an operation control signal to determine a type of operation between the stored data and main data”. It is unclear if the storage of data is meant to mean both the main data and the data referred to as “stored data”, or if the main data is supplied, or generated elsewhere in the circuitry.
Claims 11-19 inherit the same deficiency as claim 10 based on dependence.
Regarding claim 13, claim 13 recites the limitation of: “storing of the data comprises storing the data based on a channel index that indicates a position of an output tensor of the data.” It is unclear if the data described in this limitation is meant to be understood as the “stored data”, the “main data”, or both.
Regarding claim 15, claim 15 recites the limitation of: “a second phase signal to output the main data and update an internal storage configured to store the data”. It is unclear if the data being stored in the internal storage in the update is meant to be understood as the “stored data”, the “main data”, or both.
Regarding claim 16, claim 16 recites the limitation of: “performing an addition of the output of the ALU.” The limitation is unclear what is being added to the ALU output. It is unclear if there is another operand added to the ALU result, or if it is meant to be understood as multiple ALU results over time are put into the adder tree and accumulated.
Claim 17 inherits the deficiency of claim 16 based on dependence.
Regarding claim 18, claim 18 recites the limitation of: “an output of an adder tree configured to perform an addition of the output of the ALU.” The limitation is unclear what is being added to the ALU output. It is unclear if there is another operand added to the ALU result, or if it is meant to be understood as multiple ALU results over time are put into the adder tree and accumulated.
Allowable Subject Matter
Claims 1-19 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
With regards to claim 1, the applicant claims an apparatus to perform neural network operations, the apparatus comprising:
an internal storage configured to store data to perform a neural network operation; an arithmetic logical unit (ALU) configured to perform an operation between the stored data and main data based on an operation control signal; an adder configured to add an output of the ALU and an output of a first multiplexer, wherein the first multiplexer is configured to output one of an output of the adder and the output of the ALU based on a reset signal; a second multiplexer configured to output one of the main data and a quantization result of the stored data based on a phase signal; and a controller configured to control the ALU, the first multiplexer, and the second multiplexer based on the operation control signal, the reset signal, and the phase signal.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
With regards to claim 10, the applicant claims a method to perform a neural network operation, the method comprising:
storing data to perform a neural network operation; generating an operation control signal to determine a type of operation between the stored data and main data, a reset signal to select one of an output of an adder and an output of an arithmetic logical unit (ALU), and a phase signal to select one of the main data and a quantization result of the stored data; generating an operation result by performing an operation between the stored data and the main data based on the operation control signal; generating an addition result by performing an addition between the operation result and a result selected from a result of the output of the adder and a result of the output of the ALU; selecting one of the operation result and a result of the addition, and outputting the selected one based on the reset signal; and outputting one of the main data and the quantization result of the stored data based on the phase signal.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Henry et al. (U.S. Patent Application Publication 2018/0267898 A1), disclosed in the applicant’s Information Disclosure Statement dated 02/20/2025, hereinafter, “Henry”, discloses circuitry performing neural network operations (Fig. 1). Henry further discloses multiplexor circuitry, ALU circuitry and accumulator circuitry, with the ALU performing operations on input data and weight data (Fig. 2), and an accumulator accumulating results of the ALU (Fig. 2), with the accumulator result fed back into the ALU adder circuit such that the accumulator value is added with a value computed from a multiplexer (Fig. 2 items 244 (Adder), 208 (mux), 217 (accumulator output). However, Henry fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/J.A.K./Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182