DETAILED ACTION
This action is responsive to the claims filed 6 Nov 2025. Claims 1-22 and 31-33 are pending. Claims 1, 31 and 33 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 6 Nov 2025 has been entered. Claims 1-22 and 31-33 are currently pending in the application.
Allowable Subject Matter
Claims 10, 11, 13 – 15, 20 – 22, and 31 – 33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments filed on 6 Nov 2025 have been fully considered. Applicant’s arguments are not persuasive in regards to the 35 USC § 103 rejections as the claims are currently written. Arguments and corresponding examiner’s responses are shown below for independent Claim 1. Claim 31 has been amended away from claim 1.
Before answering specific arguments, the applicant is reminded that the claims as stated have not been limited to chalcogenide memory cells. Since applicant admits that the claim is not limited to chalcogenide memories, then other memories and their behaviors are also claimed. In this application, the term ‘switches’ and ‘detecting’ a memory cell have been interpreted in their ordinary way: e.g. a cell is turned on using word and bit lines, when turned on by the word and bit lines, this cell “switches on”, then the sense amplifier can detect the memory cell contents, and finally the word / bit lines are turned off and the voltages on the word / bit lines decay in accordance with cell architecture.
If applicant were to include the following limitation into claim 1, then a further search and consideration might find the claim allowable: “after sensing whether a snap back event has occurred at one of the first or second memory cells
Argument 1: The Applicant states “However, paragraph 23 of Veches relates to an entire “memory array 150” being “refreshed.” In contrast, Claim 1 as amended recites that only a partition of the memory array is refreshed.”
Response 1: The Examiner respectfully disagrees. Applicant’s argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., that “ONLY” the affected cells, or ONLY a partition of the memory are refreshed) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). (see MPEP 2145 (VI).)
According to MPEP 2111.03 Transitional Phrases states:
I. COMPRISING The transitional term “comprising”, which is synonymous with “including,” “containing,” or “characterized by,” is inclusive or open-ended and does not exclude additional, unrecited elements or method steps.
In this case, the refreshing operation is not limited in the claims to merely a portion of the memory array. Neither is the refreshing operation sequenced with the previous claim limitations in any way. The claim as written merely requires that at least a portion of a memory array with memory cells are refreshed at some arbitrary time. Veches teaches refreshing cells. Contra to applicant’s assertion, Veches teaches several cases in paragraph 0024-0025 where the cells are refreshed in a sequential manner, or one partition at a time. As such, in keeping with the same general thrust of the previous office action, Veches teaches the claimed limitations.
Argument 2: The Applicant states “As such, claim 31 is submitted to be allowable.” “
Response 2: The Examiner agrees, claims 31 and 33 and their dependent claims have been marked as allowable in this office action.
Allowable Subject Matter
Claims 10, 11, 13 – 15, 20 – 22, and 31 – 33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 7, 9, 12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kurafuji, et al, U.S. Patent Application Publication 2018/0277214 (“Kura”) in view of Veches, et al, U.S. Patent Application Publication 2021/0065796 (“Veches”).
Regarding claim 1, Kura teaches:
(Currently Amended) An apparatus comprising: a memory array comprising memory cell pairs; (Kura, fig 2, paragraph 0032-0040, “[0032] As shown in FIG. 2, the flash memory 100 includes a power supply circuit 101, a write circuit 102, an address buffer 103, … and a memory cell array 110.[0039] The data memory unit 150 is a memory cell area that includes a pair of memory cells composed of a memory cell M1a and a memory cell M1b. The data memory unit 150 stores 1-bit data by the two memory cells: the memory cell M1a and the memory cell M1b. For example, when storing data “0” in the data memory unit 150, the memory cell M1a is set to the high threshold voltage state, and the memory cell M1b is set to the low threshold voltage state,”; a complementary memory cell pair, configured to store a single bit using two memories storing complementary data; that a complementary memory cell pair typically sets one storage cell to a high value and the other storage cell to a low value for comparison by a sense amplifier).
bias circuitry configured to select a first memory cell pair having first and second memory cells, (Kura, fig 2, 4, paragraph 0034, 0054-, “[0034] The WL driver 106 is a circuit that drives the word line WL in accordance with the line predecode signal. [0054] As shown in the graph of FIG. 4, in the complementary read mode, the bit line BL connected to the memory cell M1a and the bit line BL connected to the memory cell M1b are pre-charged to reach a specified voltage by control of the sense amplifier control circuit 108.”; a complementary memory cell pair, that the WL and two BLs are (pre)charged to a voltage in a read operation; that applying power to a memory transistor cell will select a particular memory cell pair, or “switch on” that memory cell pair for reading at the sense amplifiers).
wherein the bias circuitry is further configured to reduce a magnitude of at least one of voltages on first or second bitlines after at least one of the first or second memory cells switches; and (Kura, fig 4, paragraph 0054, “[0054] After that, at specified discharge start timing t1, discharge of the bit line BL by the memory cell current flowing through the memory cell M1a and discharge of the bit line BL by the memory cell current flowing through the memory cell M1b are carried out by control of the sense amplifier control circuit 108. Then, at specified sense timing t2, the sense amplifier SA1 senses a voltage difference between the both bit lines BL and thereby determines the value stored in the data memory unit 150.”; that after t1 shown in figure 4, both of BLs are discharged (i.e. the magnitude of the voltages are reduced) flowing through the two memory cells to a sense amplifier to determine the different resistances of the memory cells; this discharge occurs after the bit lines have been precharged to a threshold voltage, and the voltage on both memory cells begins to decay, or to reduce further; see figure 4; Since the applicant has admited that the cells can be other than chalcogenide, then the limitation”switches” here has been interpreted as a set of switching transistors, or a memory cell, that has been simply being activated, or turned on; in a complementary pair of memory cells at least one cell must “switch” or “turn on” or an error has occurred; as is normal, memory cells are “read” or “programmed” after the initial turn-on; the limitation “after” has been interpreted as any time “after” the sensing reads the complementary cells. It is logical to infer that eventually all bit lines and all word lines will have a reduced voltage “after” a computer is shut off).
Kura does not explicitly teach determine to refresh a partition of the memory array that includes the first memory cell pair..
Veches teaches determine to refresh a partition of the memory array that includes the first memory cell pair. (Veches, paragraph 0023, “[0023] The memory array 150 may be refreshed or maintained as described herein to prevent data loss. … A refresh operation, as described herein, may be initiated by the memory system 190 (e.g., by the host device 108, the memory controller 101, and/or the memory device 100), and may include accessing one or more rows (e.g., WL) and discharging cells of the accessed row to a corresponding SAMP. … In other cases, the write back process may invert the data state of the cell ( e.g., from high to low or low to high), to ameliorate hysteresis shift. … [0024] In one approach, the memory device 100 may be configured to refresh the same row of memory cells in every memory bank of the memory array 150 simultaneously.”; that a memory can have a hysteresis and require refreshing to prevent data loss; that a refresh operation can take each individual memory cell of each individual row and invert the data of that cell; that a portion of the memory array can be refreshed at a time).
In view of the teachings of Veches it would have been obvious for a person of ordinary skill in the art to apply the teachings of Veches to Kura before the effective filing date of the claimed invention in order to teach how to read, program and refresh a memory cells in an array. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Veches in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Veches’s explicit memory refreshing steps for a chalcogenide memory cell and Kura’s programming steps for a generic memory. The two programming methods result in each cell having similar programming states after the refreshing programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 7, Kura, as modified by Veches, teaches (Previously Presented) The apparatus of claim 1.
Kura further teaches wherein the first memory cell is selected using a wordline and the first bitline, and the second memory cell is selected using the wordline and the second bitline. (Kura, fig 2, paragraph 0036, “[0036] Note that, although one pair of bit lines is selected from a plurality of pairs of bit lines by specifying an address and connected to the sense amplifier in an actual configuration, a bit line selection circuit is shown as a switch in a representative manner in FIG. 2 for the sake of simplifying the figure.”; that to read a single “bit” of information, two bit lines with complementary data are selected; that the memory cell is selected with a single word line and two bit lines; and the outputs of two memory cells are interpreted by a sense amplifier).
Regarding claim 9, Kura, as modified by Veches, teaches the apparatus of claim 1.
Veches further teaches further comprising a controller configured to: in response to determining to refresh the partition, invert a logic state of the first and second memory cells. (Veches, paragraph 0023, “[0023] The memory array 150 may be refreshed or maintained as described herein to prevent data loss. … A refresh operation, as described herein, may be initiated by the memory system 190 (e.g., by the host device 108, the memory controller 101, and/or the memory device 100), and may include accessing one or more rows (e.g., WL) and discharging cells of the accessed row to a corresponding SAMP. … In other cases, the write back process may invert the data state of the cell ( e.g., from high to low or low to high), to ameliorate hysteresis shift. … [0024] In one approach, the memory device 100 may be configured to refresh the same row of memory cells in every memory bank of the memory array 150 simultaneously.”; that a memory can have a hysteresis and require refreshing to prevent data loss; that a refresh operation can take each individual memory cell of each individual row and invert the data of that cell; that a portion of the memory array can be refreshed at a time).
In view of the teachings of Veches it would have been obvious for a person of ordinary skill in the art to apply the teachings of Veches to Kura before the effective filing date of the claimed invention in order to teach how to read, program and refresh a memory cells in an array. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Veches in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Veches’s explicit memory refreshing steps for a chalcogenide memory cell and Kura’s programming steps for a generic memory. The two programming methods result in each cell having similar programming states after the refreshing programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 12, Kura, as modified by Veches, teaches the apparatus of claim 9.
Veches further teaches wherein at least a portion of a page of data is stored in the partition, and inverting the logic state is performed as part of an inversion of the page. (Veches, paragraph 0023, “[0023] The memory array 150 may be refreshed or maintained as described herein to prevent data loss. … A refresh operation, as described herein, may be initiated by the memory system 190 (e.g., by the host device 108, the memory controller 101, and/or the memory device 100), and may include accessing one or more rows (e.g., WL) and discharging cells of the accessed row to a corresponding SAMP. While the row is opened (e.g., while the accessed WL is energized), the SAMP may compare the voltage resulting from the discharged cell to a reference. The SAMP may then write back a logic value ( e.g., charge the cell) to a nominal value for the given logic state. … In other cases, the write back process may invert the data state of the cell ( e.g., from high to low or low to high), to ameliorate hysteresis shift.”; that a memory can have a hysteresis and require refreshing to prevent data loss; that a refresh operation can take each individual memory cell of each individual row (or a portion of a memory page), the existing data from the row can be stored in the associated Sensing Amplifiers (SAMP); the system can also invert and write the data of those cells in as inverted data).
In view of the teachings of Veches it would have been obvious for a person of ordinary skill in the art to apply the teachings of Veches to Kura before the effective filing date of the claimed invention in order to teach how to read, program and refresh a memory cells in an array. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Veches in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Veches’s explicit memory refreshing steps for a chalcogenide memory cell and Kura’s programming steps for a generic memory. The two programming methods result in each cell having similar programming states after the refreshing programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 16, Kura, as modified by Veches, teaches (Previously Presented) The apparatus of claim 1.
Kura further teaches wherein at least one of the first or second memory cells switches when sensing circuitry is reading data stored by the first memory cell pair. (Kura, fig 4, paragraph 0054, “[0054] Then, at specified sense timing t2, the sense amplifier SA1 senses a voltage difference between the both bit lines BL and thereby determines the value stored in the data memory unit 150.”; that after time t2, the sense amplifier can sense the different currents at the two memories to determine the state of the memory cells; the limitation “switches” has been given its normal meaning in the art that a memory cell is switched on when an bitline and wordline are activated).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Kura, as modified by Veches, in view of Ryu, et al, U.S. Patent Application Publication 2019/0267084 (“Ryu”).
Regarding claim 2, Kura, as modified by Veches, teaches the apparatus of claim 1.
Kura teaches:
further comprising: a buffer configured to store first data read from the first memory cell pair, wherein the buffer includes a first latch; (Kura, fig 2, paragraph 0042, “[0042] The sense amplifier SA1 is a circuit that determines the value of data stored in the data memory unit 150 by comparing a current (memory cell current) flowing through one memory cell M1a .. and a current … flowing through the other memory cell M1b. … The sense amplifier SA1 outputs the determined data value as a read result to the output driver 109. As a result, the data D31 to D0 are output from the output driver 109.”; latch 109, which operates as a data buffer array which stores the values from reading the memory bank).
change a logic state for each of the first and second memory cells to store the second data. (Kura, paragraph 0029, “[0029] For example, a value of “0” is stored when the flash memory cell 5 is in the high threshold voltage state, and a value of “1” is stored when the flash memory cell 5 is in the low threshold voltage state.”; that desired data from the write command can be stored in two memory cells as Hi-Lo or Lo-Hi, that twin cells in this regard can be treated as two co-located memory cells with the addition of Kura’s sense amplifier).
Kura, as modified by Veches, does not explicitly teach:
a second latch configured to store data to be written to the memory array; and
a controller configured to: receive a write command with second data to be stored; in response to receiving the write command, store the second data in the second latch; compare the first and second data;
determine, based on comparing the first and second data, that the second data is not stored in the memory array; and.
Ryu teaches:
a second latch configured to store data to be written to the memory array; and (Ryu, fig 4, paragraph 0050-0052, “[0050] Referring back to FIG. 4, the control circuit 520 may control write, program, and read operations… In the bank active state, the control circuit 520 enables circuits associated with a bank activated based on the bank address, activates a word line selected in the activated bank by decoding the row address, and performs a read data evaluation operation for reading and latching data of memory cells of the memory cell array 510. [0052] In the first write operation, the control circuit 520 latches write data received together with the write command WR and compares bits of the data read from the memory cell array 510 having the bank active state, to bits of the write data.”; a memory cell that latches data already written to a memory cell and also latches incoming data to be written; that the data can be compared).
a controller configured to: receive a write command with second data to be stored; in response to receiving the write command, store the second data in the second latch; compare the first and second data; (Ryu, fig 7, paragraph 0052-0062, “[0052] In an embodiment, the control circuit 520 performs a first write operation in response to the active command ACT and a write command WR (see FIG. 8). In the first write operation, the control circuit 520 latches write data received together with the write command WR and compares bits of the data read from the memory cell array 510 having the bank active state, to bits of the write data.”; the control circuit which receives a WR command, the circuit latches the desired value of data from the write commands and compares the new data with the data stored in the memory array).
determine, based on comparing the first and second data, that the second data is not stored in the memory array; and (Ryu, paragraph 0061, “[0061] In a write operation of each bank, the write driver and write data latch 560 of the bank may compare the read data latched in the sense amplifier and read data latch 550 to the write data latched in the write driver and write data latch 560. In an exemplary embodiment, the write driver and write data latch 560 program only bits of the write data, which are determined to be different from bits of the read data as a result of the comparison, as set or reset data in memory cells of the memory cell array 510 of the bank.”; that after comparison of the new data and stored data, only different bits are programmed while cells containing the same data are not changed).
In view of the teachings of Ryu it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ryu to Kura before the effective filing date of the claimed invention in order to teach how to read and program a memory cell. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Ryu in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Ryu specific programming steps and Kura’s more generic programming steps. The two programming methods result in each bit having exactly the same state after programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 3, Kura, as modified by Veches and Ryu, teaches the apparatus of claim 2.
Kura further teaches wherein changing the logic state for the first and second memory cells is performed in response to receiving a pre-charge command. (Kura, paragraph 0054, “[0054] As shown in the graph of FIG. 4, in the complementary read mode, the bit line BL connected to the memory cell M1a and the bit line BL connected to the memory cell M1b are pre-charged to reach a specified voltage by control of the sense amplifier control circuit 108.”; that a pre-charge command is part of the read command; that the read command is performed before the write command of claim 2, therefore the pre-charge command is also part of the write command).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kura, as modified by Veches and Ryu, in view of Toda, et al, U.S. Patent Application Publication 2007/0285963 (“Toda”).
Kura, as modified by Veches and Ryu, teaches the apparatus of claim 2.
Kura, as modified by Veches and Ryu, does not explicitly teach:
wherein changing the logic state comprises applying, using the bias circuitry,
at least one pulse to each of the first and second memory cells..
Toda teaches:
wherein changing the logic state comprises applying, using the bias circuitry, (Toda, fig 5, paragraph 0074, “[0074] In FIG. 5, two cell pairs are typically shown as follows: two cells connected to a pair of bit lines BLOO and /BLOO, respectively, with sharing a word line WLOO in the cell array MAO, being constituted to one pair cell, one of which is a true cell “T-cell0” and the other is a complementary cell “C-cell0”;”; that cell pairs are typically driven by two bit lines).
at least one pulse to each of the first and second memory cells. (Toda, fig 20, paragraph 0147-0154, “[0147] Referring to FIG. 20, operations of the write pulse generation circuit 600 will be described bellow.”; that at least one pulse is necessary to write complementary data to a cell pair).
In view of the teachings of Toda it would have been obvious for a person of ordinary skill in the art to apply the teachings of Toda to Kura before the effective filing date of the claimed invention in order to teach how to read and program a memory cell. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Toda in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Toda’s explicit programming steps and Kura’s more general programming steps. The two programming methods result in each bit having exactly the same state after programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kura, as modified by Veches, in view of Toda.
Regarding claim 5, Kura, as modified by Veches, teaches (Previously Presented) The apparatus of claim 1.
Kura teaches … to read first data from the first memory cell pair… from the first memory cell pair by determining a logic state of the first memory cell pair. (Kura, fig 4, paragraph 0054, “[0054] After that, at specified discharge start timing t1, discharge of the bit line BL by the memory cell current flowing through the memory cell M1a and discharge of the bit line BL by the memory cell current flowing through the memory cell M1b are carried out by control of the sense amplifier control circuit 108.”; that after t1 shown in figure 4, the BLs are discharged flowing through the two memory cells to a sense amplifier to determine the different resistances of the memory cells; this discharge occurs after the bit lines have been precharged to a threshold voltage, see figure 4).
Kura, as modified by Veches, does not explicitly teach further comprising a controller configured to: receive an activate command; and in response to receiving the activate command, cause sensing circuitry to read first data from the first memory cell pair by determining a logic state of the first memory cell pair..
Toda teaches further comprising a controller configured to: receive an activate command; and in response to receiving the activate command, cause sensing circuitry to read first data from the first memory cell pair by determining a logic state of the first memory cell pair. (Toda, fig 10, 12,paragraph 0107-0110, “[0107] A sense amp SA shown in FIG. 12… [0110] Drains of sensing NMOS transistors QN61 and QN62 are selectively connected to data lines DL and /DL through NMOS transistors QN31 and QN32, respectively, that are controlled by a read control signal R to turn-on during a read operation.”; a description of figure 12, with multiple controlling lines, that controller generates a read control signal R to turn on the correct memory pair for reading).
In view of the teachings of Toda it would have been obvious for a person of ordinary skill in the art to apply the teachings of Toda to Kura before the effective filing date of the claimed invention in order to teach how to read and program a memory cells. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Toda in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Toda’s explicit programming steps and Kura’s more general programming steps. The two programming methods result in each cell having exactly the same state after programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 6, Kura, as modified by Veches and Toda, teaches (Previously Presented) The apparatus of claim 5.
Kura further teaches further comprising a buffer configured to store first data read from the first memory cell pair, (Kura, fig 4, paragraph 0054, “[0054] After that, at specified discharge start timing t1, discharge of the bit line BL by the memory cell current flowing through the memory cell M1a and discharge of the bit line BL by the memory cell current flowing through the memory cell M1b are carried out by control of the sense amplifier control circuit 108.”; that after t1 shown in figure 4, the BLs are discharged flowing through the two memory cells to a sense amplifier to determine the different resistances of the memory cells; this discharge occurs after the bit lines have been precharged to a threshold voltage, see figure 4).
Toda teaches:
wherein the controller is further configured to: after receiving the activate command, receive a read command; and (Toda, fig 10, 12,paragraph 0107-0110, “[0110] Drains of sensing NMOS transistors QN61 and QN62 are selectively connected to data lines DL and /DL through NMOS transistors QN31 and QN32, respectively, that are controlled by a read control signal R to turn-on during a read operation.”; that a read control signal R is sent over the command bus).
in response to receiving the read command, retrieve the first data from the buffer. (Toda, fig 10, 12,paragraph 0099-0106, “[0099] FIG. 10 shows a schematic layout of the read/write circuit 200 [0100] In parallel with the write pulse signal lines 305 on the global bus region 207, disposed are main data lines 304, on which read out data are transferred.”; that the read out data are transferred after reading on the global bus).
In view of the teachings of Toda it would have been obvious for a person of ordinary skill in the art to apply the teachings of Toda to Kura before the effective filing date of the claimed invention in order to teach how to read and program a memory cell. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Toda in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Toda’s explicit programming steps and Kura’s more general programming steps. The two programming methods result in each cell having exactly the same state after programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kura, as modified by Veches, in view of Mousavi, et al, U.S. Patent Application Publication 2023/0178148 (“Mousavi”).
Kura, as modified by Veches, teaches the apparatus of claim 1.
Kura teaches further comprising a controller configured to: (Kura, fig 2, paragraph 0032-0040, “[0032] As shown in FIG. 2, the flash memory 100 includes a power supply circuit 101, a write circuit 102, an address buffer 103, … and a memory cell array 110.[0039] The data memory unit 150 is a memory cell area that includes a pair of memory cells composed of a memory cell M1a and a memory cell M1b. The data memory unit 150 stores 1-bit data by the two memory cells: the memory cell M1a and the memory cell M1b. For example, when storing data “0” in the data memory unit 150, the memory cell M1a is set to the high threshold voltage state, and the memory cell M1b is set to the low threshold voltage state,”; a complementary memory cell pair, configured to store a single bit using two memories storing complementary data; that a complementary memory cell pair typically sets one storage cell to a high value and the other storage cell to a low value for comparison by a sense amplifier).
Kura, as modified by Veches, does not explicitly teach determine that at least one of the first or second memory cells has switched; and in response to determining that at least one of the first or second memory cells has switched, cause the bias circuitry to reduce the magnitude of the voltages on the first and second bitlines..
Mousavi teaches determine that at least one of the first or second memory cells has switched; and in response to determining that at least one of the first or second memory cells has switched, cause the bias circuitry to reduce the magnitude of the voltages on the first and second bitlines. (Mousavi, fig 6a/b,10, paragraph 0082-0089, “[0007] Memory devices typically store data in memory cells. In some cases, memory cells exhibit non-uniform, variable electrical characteristics … or a drift (e.g., a change in resistance of a chalcogenide alloy), among others. [0082] FIG.10 illustrates an example of a process 1000 for reading a state in a memory cell with a crystalline PM region (e.g., the SET or MLCl states described above). [0085] At 1004,… As another example, in the wordline first algorithm, after the wordline is set and stabilized at -3.3V, the bitline is then ramped to 3. 7V. [0086] At 1006, during the ramping of the second address line at 1004, the memory cell may “snap” once the differential voltage between the address lines reaches a particular voltage (i.e., the threshold or demarcation voltage (VDM)) and the snap is detected. Prior to the snap, current does not flow in the cell; however, once the differential voltage reaches the threshold/demarcation voltage, current begins to flow in the cell, causing a drop in the differential voltage between the two address lines.”; that a chalcogenide memory cell can be used as a memory cell, that each of the memory cells can have the voltages increased (wordline and bitline) in different configurations; that the control can detect a snap; that prior to the snap the voltage can be ramped on the wordlines and bitlines; that after the snap, the voltage inherently falls, and after reading the cells, the voltage decreases to zero for both the wordlines and bitlines).
In view of the teachings of Mousavi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Mousavi to Kura before the effective filing date of the claimed invention in order to teach how to read and program a memory cells in an array. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Mousavi in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Mousavi’s explicit programming steps for a chalcogenide memory cell and Kura’s programming steps for a generic memory. The two programming methods result in each cell having exactly the same state after programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kura, as modified by Veches, in view of Lien, et al, U.S. Patent 10,861,537 (“Lien”).
Kura, as modified by Veches, teaches (Previously Presented) The apparatus of claim 1.
Kura, as modified by Veches, does not explicitly teach wherein the wordline voltage is applied as a ramp of increasing magnitude when reading data stored by the first memory cell pair..
Lien teaches wherein the wordline voltage is applied as a ramp of increasing magnitude when reading data stored by the first memory cell pair. (Lien, fig 10A, column 20, lines 15-25, “(141) FIG. 10A shows that the word line voltage starts to ramp at time t1, and reaches Vread by time t2. At time t3 the word line voltage is reduced to a steady state value, which is reached at time t4. ”; that wordline voltages can be ramped in the read process. Note: All voltages are inherently ramped according to the circuits RC characteristics, Lien is provided as an explicit ramp).
In view of the teachings of Lien it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lien to Kura before the effective filing date of the claimed invention in order to teach how to read and program a memory cell. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Lien in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Lien’s explicitly ramped programming voltage and Kura’s inherent programming voltage rise. The two programming methods result in each bit having exactly the same state after programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kura, as modified by Veches, in view of Muzetto, et al, U.S. Patent Application Publication 2023/0110946 (“Muzetto”).
Kura, as modified by Veches, teaches (Previously Presented) The apparatus of claim 1.
Kura, as modified by Veches, does not explicitly teach further comprising a wordline configured to select the first and second memory cells,wherein: the voltage applied to the first and second bitlines is of a first polarity; and the voltage applied to the wordline is of a second polarity opposite to the first polarity..
Muzetto teaches further comprising a wordline configured to select the first and second memory cells,wherein: the voltage applied to the first and second bitlines is of a first polarity; and the voltage applied to the wordline is of a second polarity opposite to the first polarity. (Muzetto, paragraph 0032, “[0032] A cell thresholds (e.g., it becomes conductive) when a suitable voltage difference is applied between its two terminals; such a voltage difference may be obtained in different ways, for example biasing one terminal, such as a wordline terminal, to a negative voltage (e.g. a selection voltage), and the other terminal, such as a bitline terminal, to a positive voltage (e.g. a reading voltage).”; that opposite polarity voltages can be applied to the wordlines and bitlines in a memory to determine the cell’s logic state).
In view of the teachings of Muzetto it would have been obvious for a person of ordinary skill in the art to apply the teachings of Muzetto to Kura before the effective filing date of the claimed invention in order to teach how to read and program a memory cell. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Muzetto in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Muzetto’s programming with opposite polarity voltages and Kura’s less specified programming voltages. The two programming methods result in each bit having exactly the same state after programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kura, as modified by Veches and Muzetto, in view of Ryu.
Kura, as modified by Veches and Muzetto, teaches (Previously Presented) The apparatus of claim 18.
Kura teaches after receiving the write command, initiate a programming operation to change a logic state of the first and second memory cells to correspond to the second data. (Kura, paragraph 0029, “[0029] For example, a value of “0” is stored when the flash memory cell 5 is in the high threshold voltage state, and a value of “1” is stored when the flash memory cell 5 is in the low threshold voltage state.”; that desired data from the write command can be stored in two memory cells as Hi-Lo or Lo-Hi. Note: in this case, the second data can be the same or different as the first stored data. Kura starts with “erased” memory in paragraph 0004 where all data can be “1” or “0” in the initial state).
Kura, as modified by Veches and Muzetto, does not explicitly teach further comprising a controller configured to: read first data from the first memory cell pair; receive a write command with second data to be stored in the memory array; and.
Ryu teaches further comprising a controller configured to: read first data from the first memory cell pair; receive a write command with second data to be stored in the memory array; and (Ryu, fig 7, paragraph 0052-0062, “[0052] In an embodiment, the control circuit 520 performs a first write operation in response to the active command ACT and a write command WR (see FIG. 8). In the first write operation, the control circuit 520 latches write data received together with the write command WR and compares bits of the data read from the memory cell array 510 having the bank active state, to bits of the write data.”; the control circuit which receives a WR command, the circuit latches the desired value of data from the write commands and compares the new data with the data stored in the memory array).
In view of the teachings of Ryu it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ryu to Kura before the effective filing date of the claimed invention in order to teach how to read and program a memory cell. Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Ryu in the same or in a similar field of endeavor with Kura before the effective filing date of the claimed invention in order to combine Ryu specific programming steps and Kura’s more generic programming steps. The two programming methods result in each bit having exactly the same state after programming and merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825