DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 4, 13, 15 and 18-20 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 4 line 3, “a plurality of stages” should read “the plurality of stages” instead because a plurality of stages is already introduced in claim 1 from which the claim depends.
B. In claim 13 lines 3-4, “an MbyL-Mode” should read “the MbyL-Mode” instead because an MbyL-Mode is already introduced in claim 11 from which the claim depends. Claims 18 and 20 recite a similar limitation and are objected to for the same reason.
C. In claim 15 line 4, “a BR_ Straight-Mode” should “the BR_ Straight-Mode” instead because a BR_ Straight-Mode is already introduced in claim 11 from which the claim depends.
D. In claim 19 line 4, “a BR_ MbyL-Mode” should read “the BR_ MbyL-Mode” instead because a BR_ MbyL-Mode is already introduced in claim 16 from which the claim depends.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a write back MUX mode selected from a group consisting of a Straight-Mode, BR_Straight-Mode, MbyL-Mode or BR_MbyL-Mode” in lines 14-15. A group is normally comprised of more than one members. Therefore, it is unclear whether the group is supposed to consist just one member or consist of all the members. For purposes of examination, this is interpreted as “a write back MUX mode selected from a group consisting of a Straight-Mode, BR_Straight-Mode, MbyL-Mode and BR_MbyL-Mode” consistent with a Markush grouping (“a material selected from the group consisting of A, B, and C”). See 2173.05(h) I and 2117 I for more information. Claims 11 and 16 recite a similar limitation and are rejected for the same reason. Claims 2-10 inherit the same deficiency as claim 1 by reason of dependence. Claims 12-15 inherit the same deficiency as claim 11 by reason of dependence. Claims 17-20 inherit the same deficiency as claim 16 by reason of dependence.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under Step 1, claims 1-20 recite a series of steps and, therefore, is a process.
Under Step 2A prong 1, claim 1 recites
A method for self-ordering Fast Fourier Transform (FFT) for Single Instruction Multiple Data engines comprising:
transforming a plurality of elements comprising first input elements and second input elements with an FFT comprising a plurality of stages comprising at least a first stage and a final stage, wherein transforming the plurality of elements comprises:
performing a butterfly operation on a first input vector and a second input vector to generate a first output vector and a second output vector, wherein the first input vector, the second input vector, the first output vector and the second output vector are each comprised of complex numbers, and a first order of at least three of the complex numbers of the first output vector is non-linear and a second order of at least three of the complex numbers of the second output vector is non-linear; and
reordering and exchanging a combination of complex numbers between the first output vector and the second output vector using a vector multiplexer which permutes the first output vector and the second output vector in accordance with a write back MUX mode selected from a group consisting of a Straight-Mode, BR_Straight-Mode, MbyL-Mode or BR_MbyL-Mode to at least partially linearize the first order of the first output vector and to at least partially linearize the second order of the second output vector.
The above underlined limitations of performing a butterfly operation and reordering elements of the output vectors amounts to processing mathematical calculations and falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. See paragraph [0025] formula 1-2 which defines the butterfly operation in an FFT. Further, the step of “reordering and exchanging” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “SIMD engines”, nothing in the claim element precludes the step from practically being performed in the human mind. For example, but for the “SIMD engines” language, the claim encompasses manually sorting and swapping elements of two output vectors to partially linearize the order of elements in the two output vectors using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: for Single Instruction Multiple Data engines and a vector multiplexer. However, the additional elements of “Single Instruction Multiple Data engines” and “a vector multiplexer” are recited at a high-level of generality (i.e., as generic compute engines which implements the FFT without reciting any specific structural configuration of the engines; and a generic multiplexer for selecting an output based on a selection signal/mode) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 1 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “Single Instruction Multiple Data engines” and “a vector multiplexer” are recited at a high-level of generality (i.e., as generic compute engines which implements the FFT without reciting any specific structural configuration of the engines; and a generic multiplexer for selecting an output based on a selection signal/mode) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 2-10 recite the same abstract idea as claim 1 by reason of dependence. Further, claim 3 recites further abstract idea of “converting a first data type of the first output vector and converting a second data type of the second output vector”; claim 4 recites further details of the abstract idea “wherein the first order and the second order are both linear in the final stage of the FFT, the butterfly operation performed for each of a plurality of stages of the FFT”; claim 5 recites further abstract idea and details of the abstract idea of “performing the butterfly operation on each one of a plurality of stages of a Decimation-In-Frequency FFT”; claim 6 recites further abstract idea of “modifying at least one complex number of the second input vector with a twiddle factor”; claim 7 recites further details of the abstract idea “wherein generating the first output vector by the butterfly operation comprises adding each one of the complex numbers of the first input vector to a corresponding one of the complex numbers of the second input vector”; claim 8 recites further details of the abstract idea “wherein generating the second output vector by the butterfly operation comprises subtracting each one of the complex numbers of the second input vector multiplied by a twiddle factor from a corresponding one of the complex numbers of the first input vector multiplied by the twiddle factor”; claim 10 recites further abstract idea of “converting a data type of the complex numbers of the first input vector” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claims 4-8 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 2 recites the following additional elements: writing back the first output vector to a first storage comprising the first input vector and writing back the second output vector to a second storage comprising the second input vector; claim 3 recites the following additional elements: before writing back to the first storage and before writing back to the second storage; claim 9 recites the following additional elements: loading a first source register with the complex numbers of the first input vector received from a first multiplexer, the first multiplexer configured to multiplex a subset of a line of complex numbers received from a line buffer; claim 10 recites the following additional elements: before loading the first source register. However, the additional elements of “a first storage” and “a second storage” in claims 2 and 3; “a first source register” in claims 9 and 10; and “a first multiplexer” and “a line buffer” in claim 9 are recited at a high-level of generality (i.e., as a generic memory components for storing data; and as a generic multiplexer for receiving and outputting data) such that they amount to no more than merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. At best, the additional elements of ““a first multiplexer” and “a line buffer” in claim 9 are merely generally linking the use of the abstract to a particular technological environment or field of use by limiting the data gathering step of loading the source register to particular data source (complex numbers received from a first multiplexer received from a line buffer). See MPEP 2106.05(h) for more information. The additional elements of “writing back the first output vector to a first storage comprising the first input vector and writing back the second output vector to a second storage comprising the second input vector” in claim 2; “writing back to the first storage and writing back to the second storage” in claim 3; “loading the first source register with the complex numbers of the first input vector” in claim 9; and “loading the first source register” in claim 10 are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claims 2-3 and 9-10 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first storage” and “a second storage” in claims 2 and 3; “a first source register” in claims 9 and 10; and “a first multiplexer” and “a line buffer” in claim 9 are recited at a high-level of generality (i.e., as a generic memory components for storing data; and as a generic multiplexer for receiving and outputting data) such that they amount to no more than merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. At best, the additional elements of ““a first multiplexer” and “a line buffer” in claim 9 are merely generally linking the use of the abstract to a particular technological environment or field of use by limiting the data gathering step of loading the source register to particular data source (complex numbers received from a first multiplexer received from a line buffer). See MPEP 2106.05(h) for more information. The additional elements of “writing back the first output vector to a first storage comprising the first input vector and writing back the second output vector to a second storage comprising the second input vector” in claim 2; “writing back to the first storage and writing back to the second storage” in claim 3; “loading the first source register with the complex numbers of the first input vector” in claim 9; and “loading the first source register” in claim 10 are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea.
Under Step 2A prong 1, claim 11 recites
A method for self-ordering Fast Fourier Transform (FFT) for Single Instruction Multiple Data engines comprising:
transforming an N number of elements comprising first input elements and second input elements with an FFT comprising a plurality of stages, wherein the plurality of stages comprises at least one first stage, at least one second stage and a final stage, and wherein the N number is greater than an M number of a subset of the N number of elements loadable by each of a first storage and a second storage, wherein transforming the N number of elements comprises:
performing for each stage, a butterfly operation on a first input vector and a second input vector to generate a first output vector and a second output vector, wherein the first input vector is comprised of the first input elements, the second input vector is comprised of the second input elements, the first output vector is comprised of first output elements and the second output vector is comprised of second output elements, and a first order of at least three of the first output elements is non-linear and a second order of at least three of the second output elements is non-linear; and
reordering and exchanging, for each stage, a combination of elements between the first output vector and the second output vector using a vector multiplexer which permutes the first output vector and the second output vector in accordance with a write back MUX mode selected from a group consisting of a Straight-Mode, BR_Straight-Mode, MbyL-Mode or BR MbvL- Mode to at least partially linearize the first order of the first output vector and to at least partially linearize the second order of the second output vector.
The above underlined limitations of transforming input elements with an FFT by performing a butterfly operation and reordering elements of the output vectors amounts to processing mathematical calculations and falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. See at least paragraph [0025] formula 1-2 which defines the butterfly operation in an FFT. Further, the step of “reordering and exchanging” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is nothing in the claim element precludes the step from practically being performed in the human mind. For example the claim encompasses manually sorting and swapping elements of two output vectors to partially linearize the order of elements in the two output vectors using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: a first storage, a second storage and a vector multiplexer. However, the additional elements of “a first storage”, “a second storage” and “a vector multiplexer” are recited at a high-level of generality (i.e., as generic storage components for storing data; and as a generic multiplexer for selecting an output based on a selection signal/mode) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 11 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first storage”, “a second storage” and “a vector multiplexer” are recited at a high-level of generality (i.e., as generic storage components for storing data; and as a generic multiplexer for selecting an output based on a selection signal/mode) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 12-15 recite the same abstract idea as claim 11 above. Further, claim 12 recites further details of the abstract idea “wherein the FFT is a Decimation-In-Frequency FFT; claim 13 recite further details of the abstract idea “wherein the plurality of stages comprises a first stage”; claim 14 recites further details of the abstract idea “wherein the plurality of stages comprises a second stage”; claim 15 recites further details of the abstract idea “wherein the plurality of stages comprises a last stage” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claim 12 does not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 13 recites the following additional elements: wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with an MbyL-Mode; claim 14 recites the following additional elements: wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with the Straight-Mode; claim 15 recites the following additional elements: wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with a BR_Straight-Mode. However, the additional elements of “wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with an MbyL-Mode” in claim 13; “wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with the Straight-Mode” in claim 14; and “wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with a BR_Straight-Mode” in claim 15 in claim 19 are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claims 13-15 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with an MbyL-Mode” in claim 13; “wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with the Straight-Mode” in claim 14; and “wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with a BR_Straight-Mode” in claim 15 are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under Step 2A prong 1, claim 16 recites
A method for self-ordering Fast Fourier Transform (FFT) for Single Instruction Multiple Data engines comprising:
transforming an N number of elements comprising first input elements and second input elements with an FFT comprising a plurality of stages, wherein the plurality of stages comprises at least one first stage and a final stage, and wherein the N number is less than or equal to an M number of a subset of the N number of elements loadable by each of a first storage and a second storage;
performing for each stage, a butterfly operation on a first input vector and a second input vector to generate a first output vector and a second output vector, wherein the first input vector is comprised of the first input elements, the second input vector is comprised of the second input elements, the first output vector is comprised of first output elements and the second output vector is comprised of second output elements, and a first order of at least three of the first output elements is non-linear and a second order of at least three of the second output elements is non-linear; and
reordering and exchanging a combination of elements between the first output vector and the second output vector using a vector multiplexer which permutes the first output vector and the second output vector in accordance with a write back MUX mode selected from a group consisting of a Straight-Mode, BR_Straight-Mode, MbyL-Mode or BR_MbyL-Mode to at least partially linearize the first order of the first output vector and to at least partially linearize the second order of the second output vector.
The above underlined limitations of transforming input elements with an FFT, performing a butterfly operation and reordering elements of the output vectors amounts to processing mathematical calculations and falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. See at least paragraph [0025] formula 1-2 which defines the butterfly operation in an FFT. Further, the step of “reordering and exchanging” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is nothing in the claim element precludes the step from practically being performed in the human mind. For example the claim encompasses manually sorting and swapping elements of two output vectors to partially linearize the order of elements in the two output vectors using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: a first storage, a second storage and a vector multiplexer. However, the additional elements of “a first storage”, “a second storage”, and “a vector multiplexer” are recited at a high-level of generality (i.e., as generic storage components for storing data; and as a generic multiplexer for selecting an output based on a selection signal/mode) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 16 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first storage”, “a second storage”, and “a vector multiplexer” are recited at a high-level of generality (i.e., as generic storage components for storing data; and as a generic multiplexer for selecting an output based on a selection signal/mode) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 17-20 recite the same abstract idea as claim 16 above. Further, claim 17 recites further details of the abstract idea “wherein the FFT is a Decimation-In-Frequency FFT; claim 18 recite further details of the abstract idea “wherein the plurality of stages comprises a first stage”; claim 19 recites further details of the abstract idea “wherein the plurality of stages comprises a last stage and the N number is greater than 4”; claim 20 recites further details of the abstract idea “wherein the plurality of stages comprises a last stage and the N number is less than or equal to 4” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claim 17 does not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 18 recites the following additional elements: wherein the at least partially linearized are written back to the respective first storage and second storage with an MbyL-Mode; claim 19 recites the following additional elements: wherein the at least partially linearized are written back to the respective first storage and second storage with a BR_MbyL-Mode; claim 20 recites the following additional elements: wherein the at least partially linearized are written back to the respective first storage and second storage with an MbyL-Mode. However, the additional elements of “wherein the at least partially linearized are written back to the respective first storage and second storage with an MbyL-Mode” in claims 18 and 20; and “wherein the at least partially linearized are written back to the respective first storage and second storage with a BR_MbyL-Mode” in claim 19 are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claims 18-20 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “wherein the at least partially linearized are written back to the respective first storage and second storage with an MbyL-Mode” in claims 18 and 20; and “wherein the at least partially linearized are written back to the respective first storage and second storage with a BR_MbyL-Mode” in claim 19 are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-17 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Sheikh et al. (US 20180336161 A1), hereinafter Sheikh.
Regarding claim 16, Sheikh teaches:
transforming an N number of elements comprising first input elements and second input elements with an FFT comprising a plurality of stages, wherein the plurality of stages comprises at least one first stage and a final stage, and wherein the N number is less than or equal to an M number of a subset of the N number of elements loadable by each of a first storage and a second storage (Sheikh Figs. 2, 4 and 6 and paragraph [039] “FIG. 2 shows signal flow graph 200 illustrating an N=8-point DIF FFT and the corresponding butterfly operations. As shown in FIG. 2, the 8-point FFT operation may be realized in log2 8=3 computation stages with 8/2=4 butterflies computations per stage”; paragraph [0056] “As previously indicated, FFT circuit 300 may additionally be configurable, and accordingly may be easily reconfigured to implement an M-point DFT for M
≤
N for M, N as powers of 2. FIG. 6 shows an example in which FFT circuit 300 realized as an N=8-point FFT may be reconfigured to implement an M=4-point FFT”; plurality of stages - computation stages; first storage – registers 1-4; a second storage – registers 5-7; N = 4; M = 4; paragraph [0035] first input elements and second input elements – elements of the top and bottom halves);
performing for each stage, a butterfly operation on a first input vector and a second input vector to generate a first output vector and a second output vector, wherein the first input vector is comprised of the first input elements, the second input vector is comprised of the second input elements, the first output vector is comprised of first output elements and the second output vector is comprised of second output elements, and a first order of at least three of the first output elements is non-linear and a second order of at least three of the second output elements is non-linear (Sheikh Figs. 1-5 and paragraphs [0035-0038] “The DIF FFT approach may split an input sequence x[n] into halves and subsequently allow for computation of the "even" indices of output sequence X[k] for k=0, 2, 4, ... , N-2 and for the "odd" indices of X[k] for k=1, 3, 5, ... , N-1, thus warranting the "decimation" in frequency title. Assuming an even N, the DIF FFT approach may divide the indices n=O, 1, ... , N-1 of Equation (1) into "top" and "bottom" halves … Accordingly, the even-indexed outputs X[2r] and odd-indexed outputs X[2r+1] of X[k] may each be calculated as N/2-point DFT of xe[n] and xo[n] … Accordingly, an N-point DFT may be split into so-called "butterfly" computations for DIF FFT as depicted by radix-2 butterfly 100 of FIG. 1, where each radix-2 butterfly computation involves two complex additions (one addition and one subtraction amounting to a 2-point DFT due to the simplification of the complex exponential term to ±1) and a complex multiplication”; first input vector and a second input vector – odd and even (or top and bottom) halves; first output vector and a second output vector - even-indexed outputs X[2r] and odd-indexed outputs X[2r+1]; paragraph [0048] “FIG. 5 may be realized as a complex radix-2 bypassable butterfly with e.g. 12 bits each for in-phase (I) and quadrature (Q) components (although various other bit widths are recognized). As shown in FIG. 5, butterfly circuit 500 may include two complex adders and a multiplier”); and
reordering and exchanging a combination of elements between the first output vector and the second output vector using a vector multiplexer which permutes the first output vector and the second output vector in accordance with a write back MUX mode selected from a group consisting of a Straight-Mode, BR_Straight-Mode, MbyL-Mode or BR_MbyL-Mode to at least partially linearize the first order of the first output vector and to at least partially linearize the second order of the second output vector (Fig. 4 and paragraph [0054] “FFT circuit 300 may thus hold output sequence X[k] in intermediate/output registers 310. However, as previously indicated output sequence X[k] may be in bit-reversed order. FFT circuit 300 may implement a final reordering stage (CLK=4 for N=8; CLK=log2 N+1 for general N) with m_sel_2=1 and dsel=11 selected to route the output sequence samples provided by input registers 304 to the correct position within intermediate/output registers 310”; paragraph [0039] “the i=1 output sample corresponds to X4 according to 1
→
001 (binary)
→
100 (inverted)
→
4 (decimal)”).
Regarding claim 17, Sheikh teaches all the limitations of claim 16 as stated above. Further, Sheikh teaches wherein the FFT is a Decimation-In-Frequency FFT (Sheikh Figs. 1-2 and paragraphs [0034 and 0038-0039] “While numerous different FFT algorithms exist, the Decimation in Frequency (DIF) FFT approach will be focused on herein”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sheikh et al. (US 20180336161 A1), hereinafter Sheikh, in view of Shum et al. (US 20070106718 A1), hereinafter Shum. Shum is cited in the IDS submitted on 03/11/2024.
Regarding claim 1, Sheikh teaches a method for self-ordering Fast Fourier Transform (FFT) (Sheikh Figs. 3-4 and paragraph [0041] “FIG. 3 shows FFT circuit 300, which may implement an FFT architecture based on DIF FFT”):
transforming a plurality of elements comprising first input elements and second input elements with an FFT comprising a plurality of stages comprising at least a first stage and a final stage, wherein transforming the plurality of elements comprises (Sheikh Figs. 2, 4 and 6 and paragraph [039] “FIG. 2 shows signal flow graph 200 illustrating an N=8-point DIF FFT and the corresponding butterfly operations. As shown in FIG. 2, the 8-point FFT operation may be realized in log2 8=3 computation stages with 8/2=4 butterflies computations per stage”; paragraph [0056] “As previously indicated, FFT circuit 300 may additionally be configurable, and accordingly may be easily reconfigured to implement an M-point DFT for M
≤
N for M, N as powers of 2. FIG. 6 shows an example in which FFT circuit 300 realized as an N=8-point FFT may be reconfigured to implement an M=4-point FFT”; plurality of stages - computation stages; paragraph [0035] first input elements and second input elements – elements of the top and bottom halves):
performing a butterfly operation on a first input vector and a second input vector to generate a first output vector and a second output vector, wherein the first input vector, the second input vector, the first output vector and the second output vector are each comprised of complex numbers, and a first order of at least three of the complex numbers of the first output vector is non-linear and a second order of at least three of the complex numbers of the second output vector is non-linear (Sheikh Figs. 1-3 and 5 and paragraphs [0035-0038] “The DIF FFT approach may split an input sequence x[n] into halves and subsequently allow for computation of the "even" indices of output sequence X[k] for k=0, 2, 4, ... , N-2 and for the "odd" indices of X[k] for k=1, 3, 5, ... , N-1, thus warranting the "decimation" in frequency title. Assuming an even N, the DIF FFT approach may divide the indices n=O, 1, ... , N-1 of Equation (1) into "top" and "bottom" halves … Accordingly, the even-indexed outputs X[2r] and odd-indexed outputs X[2r+1] of X[k] may each be calculated as N/2-point DFT of xe[n] and xo[n] … Accordingly, an N-point DFT may be split into so-called "butterfly" computations for DIF FFT as depicted by radix-2 butterfly 100 of FIG. 1, where each radix-2 butterfly computation involves two complex additions (one addition and one subtraction amounting to a 2-point DFT due to the simplification of the complex exponential term to ±1) and a complex multiplication”; first input vector and a second input vector – odd and even (or top and bottom) halves; first output vector and a second output vector - even-indexed outputs X[2r] and odd-indexed outputs X[2r+1]; paragraph [0048] “FIG. 5 may be realized as a complex radix-2 bypassable butterfly with e.g. 12 bits each for in-phase (I) and quadrature (Q) components (although various other bit widths are recognized). As shown in FIG. 5, butterfly circuit 500 may include two complex adders and a multiplier”); and
reordering and exchanging a combination of complex numbers between the first output vector and the second output vector using a vector multiplexer which permutes the first output vector and the second output vector in accordance with a write back MUX mode selected from a group consisting of a Straight-Mode, BR_Straight-Mode, MbyL-Mode or BR_MbyL-Mode to at least partially linearize the first order of the first output vector and to at least partially linearize the second order of the second output vector (Fig. 4 and paragraph [0054] “FFT circuit 300 may implement a final reordering stage (CLK=4 for N=8; CLK=log2 N+1 for general N) with m_sel_2=1 and dsel=11 selected to route the output sequence samples provided by input registers 304 to the correct position within intermediate/output registers 310”; paragraph [0039] “the i=1 output sample corresponds to X4 according to 1
→
001 (binary)
→
100 (inverted)
→
4 (decimal)”).
Sheikh does not explicitly teach Single Instruction Multiple Data engines.
However, on the same field of endeavor, Shum discloses implementing an FFT on a SIMD processor (Shum paragraphs [0001, 0003, 0021-0022]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Sheikh using Shum and implement the FFT in a SIMD processor or SIMD processors because SIMD processors are able to efficiently handle large quantities of data in parallel (Sum paragraphs [0003 and 0007]).
Therefore, the combination of Sheikh as modified in view of Shum teaches Single Instruction Multiple Data engines.
Regarding claim 2, Sheikh as modified in view of Shum teaches all the limitations of claim 1 as stated above. Further, Sheikh as modified in view of Shum teaches further comprising writing back the first output vector to a first storage comprising the first input vector and writing back the second output vector to a second storage comprising the second input vector (Sheikh Figs. 3-4 and paragraphs [0043-0044, 0052, 0054] first storage – register 1-4; second storage – register 5-8).
Regarding claim 4, Sheikh as modified in view of Shum teaches all the limitations of claim 1 as stated above. Further, Sheikh as modified in view of Shum teaches wherein the first order and the second order are both linear in the final stage of the FFT, the butterfly operation performed for each of a plurality of stages of the FFT (Sheikh Fig. 4 and paragraphs [0047 and 0053-0054]).
Regarding claim 5, Sheikh as modified in view of Shum teaches all the limitations of claim 1 as stated above. Further, Sheikh as modified in view of Shum teaches further comprising performing the butterfly operation on each one of a plurality of stages of a Decimation-In-Frequency FFT (Sheikh Figs. 1-2 and paragraphs [0034 and 0038-0039] “While numerous different FFT algorithms exist, the Decimation in Frequency (DIF) FFT approach will be focused on herein”).
Regarding claim 6, Sheikh as modified in view of Shum teaches all the limitations of claim 1 as stated above. Further, Sheikh as modified in view of Shum teaches further comprising modifying at least one complex number of the second input vector with a twiddle factor (Sheikh paragraph [0036] “the input xo[n] to the other N/2-point DFT is the difference between the first half of x[n] and the second half of x[n] multiplied by a twiddle factor”).
Regarding claim 7, Sheikh as modified in view of Shum teaches all the limitations of claim 1 as stated above. Further, Sheikh as modified in view of Shum teaches wherein generating the first output vector by the butterfly operation comprises adding each one of the complex numbers of the first input vector to a corresponding one of the complex numbers of the second input vector (Sheikh Figs. 1 and 5 and paragraph [0036] “the input xe[n] to one N/2-point DFT is the sum of the first half of x[n] and the second half of x[n]”; paragraph [0048] “perform the butterfly operation on inputs A and B to produce outputs A+B”).
Regarding claim 8, Sheikh as modified in view of Shum teaches all the limitations of claim 1 as stated above. Further, Sheikh as modified in view of Shum teaches wherein generating the second output vector by the butterfly operation comprises subtracting each one of the complex numbers of the second input vector multiplied by a twiddle factor from a corresponding one of the complex numbers of the first input vector multiplied by the twiddle factor (Sheikh Figs. 1 and 5 and paragraph [0036] “the input xo[n] to the other N/2-point DFT is the difference between the first half of x[n] and the second half of x[n] multiplied by a twiddle factor”; paragraph [0048] “a multiplier (receiving a twiddle factor
W
N
k
as input) to perform the butterfly operation on inputs A and B to produce outputs … (A-B)
W
N
k
”).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sheikh in view of Shum as applied to claim 2 above, and further in view of Kang (US 20040143616 A1).
Regarding claim 3, Sheikh as modified in view of Shum teaches all the limitations of claim 2 as stated above. Further, Sheikh as modified in view of Shum teaches writing back to the first storage and writing back to the second storage (Sheikh Figs. 3-4 and paragraphs [0043-0044, 0052, 0054]).
Sheikh does not explicitly teach further comprising converting a first data type of the first output vector before writing back to the first storage and converting a second data type of the second output vector before writing back to the second storage.
However, on the same field of endeavor, Kang discloses converting a first data type of an output of an FFT operation (Kang Fig. 7 and paragraphs [0060 and 0064]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Sheikh in view of Shum and generalize the teaching of Kang by converting a data type of the first and second output vector before writing back to the first and second storage in order to adjust/minimize the bit length of the output elements which reduces the corresponding storage area and calculation complexity (Kang paragraph [0057]).
Therefore, the combination of Sheikh as modified in view of Shum and Kang teaches further comprising converting a first data type of the first output vector before writing back to the first storage and converting a second data type of the second output vector before writing back to the second storage.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sheikh in view of Shum as applied to claim 1 above, and further in view of Liang et al. (NPL – “Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs”), hereinafter Liang.
Regarding claim 9, Sheikh as modified in view of Shum teaches all the limitations of claim 1 as stated above. Further, Sheikh as modified in view of Shum teaches further comprising loading (Sheikh Fig. 3 and paragraph [0046] “FFT circuit 300 may first read the input sequence at clock cycle CLK=1, e.g. from an input buffer, at each of in1 -inN input gates 302. As shown in signal chart 400, m_sel_1 may be set to 1 in CLK=1, and accordingly input multiplexers 304 may select the input provided by input gates 302 during CLK=1. In the exemplary scenario, an N=S length input sequence x[n] may be provided to FFT circuit 300, and accordingly FFT circuit 300 may receive x[0], x[1], ... , x[N-1] at each of in1 -inN input gates 302, respectively. Input multiplexers 304 may thus provide input samples x[0], x[1], ... , x[N-1] to shuffle network 306 during CLK=1 according to m_sel_l=1”).
Sheikh does not explicitly teach further comprising loading a first source register with the complex numbers of the first input vector received from a first multiplexer, the first multiplexer configured to multiplex a subset of a line of complex numbers received from a line buffer.
However, on the same field of endeavor, Liang discloses using a register and a line buffer (Liang Fig. 3, page 861 section IV.A-B and page 862 section V.B).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Sheikh in view of Shum and generalize the teaching of Liang by configuring the input buffer as a line buffer and including a register downstream of the multiplexer 304 in order to include an input pipeline stage (Sheikh paragraphs [0032, 0040]). Furthermore, one of ordinary skill in the art could have substituted the input buffer for a line buffer, and the results of the substitution would have been predictable because they are both buffers. See MPEP 2141 III.B for more information.
Therefore, the combination of Sheikh as modified in view of Shum and Liang teaches further comprising loading a first source register with the complex numbers of the first input vector received from a first multiplexer, the first multiplexer configured to multiplex a subset of a line of complex numbers received from a line buffer.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sheikh in view of Shum and Liang as applied to claim 9 above, and further in view of Hansen et al. (US 20060095490 A1), hereinafter Hansen.
Regarding claim 9, Sheikh as modified in view of Shum teaches all the limitations of claim 1 as stated above.
Sheikh does not explicitly teach further comprising converting a data type of the complex numbers of the first input vector before loading the first source register.
However, on the same field of endeavor, Hansen discloses converting a data type of input data to a butterfly pipeline (Hansen paragraph [0133]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Sheikh in view of Shum and Liang and generalize the teaching of Hansen by converting a data type of the complex numbers before being loaded to the input registers in order to provide processing flexibility (Hansen paragraph [0133]).
Therefore, the combination of Sheikh as modified in view of Shum, Liang and Hansen teaches further comprising converting a data type of the complex numbers of the first input vector before loading the first source register.
Allowable Subject Matter
Claims 11-15 would be allowable if rewritten to overcome the 35 U.S.C. 101 and 35 U.S.C. 112(b) rejections discussed above.
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 101 and 35 U.S.C. 112(b) rejections discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art references cited, explicitly teach or suggest “reordering and exchanging, for each stage, a combination of elements between the first output vector and the second output vector using a vector multiplexer which permutes the first output vector and the second output vector in accordance with a write back MUX mode selected from a group consisting of a Straight-Mode, BR_Straight-Mode, MbyL-Mode or BR_MbvL-Mode to at least partially linearize the first order of the first output vector and to at least partially linearize the second order of the second output vector” as recited in claim 11; “wherein the plurality of stages comprises a first stage, wherein the at least partially linearized first output vector and the second output are written back to the respective first storage and second storage with an MbyL-Mode” as recited in claim 18; “wherein the plurality of stages comprises a last stage and the N number is greater than 4, wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with a BR_MbyL-Mode” as recited in claim 19; and “wherein the plurality of stages comprises a last stage and the N number is less than or equal to 4, wherein the at least partially linearized first output vector and the second output vector are written back to the respective first storage and second storage with an MbyL-Mode” as recited in claim 20.
Response to Arguments
In view of amendments made, the objection to claims 17-18 has been withdrawn. However, the amendments made raises new objections to the claims as discussed above.
In view of amendments made and Applicant’s arguments, the 35 U.S.C. 112(b) rejection of claims 1-20 has been withdrawn. However, the amendments made raises definiteness issues as discussed above.
Applicant's arguments, see remarks page 8-11, filed 03/02/2026 , with respect to the 35 U.S.C. 101 rejection of claims 1-20 have been fully considered but they are not persuasive.
Applicant argues the following:
1.) While the Fast Fourier Transform (FFT) has a mathematical basis, independent claims 1, 11, and 16 do not recite a formula, an equation, or a calculation. The steps of the “butterfly operation” and “reordering and exchanging” are steps to manipulate vectors of complex numbers within the registers of a SIMD engine to overcome the "shuffling" bottleneck inherent in parallel processing. In a SIMD environment, performing standard FFT butterfly operations often results in “non-linear” ordering of data which requires expensive and time-consuming "shuffling" or "swizzling" operations that consume computational resources and can even stall the processor. Claim 1 addresses this technical bottleneck by identifying specific non-linear orders in output vectors and executing a reordering and exchanging step between vectors to "partially linearize" the data which is not a mathematical calculation but a data management strategy to optimize the memory access and throughput of a SIMD engine. The step of "reordering and exchanging a combination of complex numbers between the first output vector and the second output vector" is a physical manipulation of data structures within a computer's memory/registers which is not a mathematical concept or a mental process that can be performed practically because a SIMD engine requires simultaneous (parallel) operations across multiple data elements in a single clock cycle which includes processing contain 4, 8, or 16+ complex numbers in parallel. The step of “reordering” is a physical optimization of data flow within a processor.
Response: Examiner respectfully disagrees. Applicant is arguing unclaimed features. The claims do not recite any memory and/or register operations and physical manipulation of data structures within a memory or registers. Therefore, any alleged improvement is not reflected in the claims. Furthermore, the step “performing a butterfly operation” recites a mathematical calculation and/or formulas as disclosed paragraph [0025] as Equations 1-2. Further, the step of “reordering and exchanging” recites a mathematical relationship of the input and the output order that flows directly from performing the FFT. Furthermore, reordering and exchanging a combination of complex numbers between a first output vector and a second output vector each having three elements is a mental step that can be performed practically.
In view of amendments made and upon further consideration, the 35 U.S.C. 102 rejection of claims 11-12 has been withdrawn.
Applicant’s arguments, see remarks page 11-13, filed 3/02/2026, with respect to the 35 U.S.C. 102 rejection of claims 16-17 and 35 U.S.C. 102 rejection of claims 1-10 have been fully considered but they are not persuasive.
Applicant amended the claims to recite “reordering and exchanging a combination of complex numbers between the first output vector and the second output vector using a vector multiplexer which permutes the first output vector and the second output vector in accordance with a write back MUX mode selected from a group consisting of a Straight-Mode, BR_Straight-Mode, MbyL-Mode or BR_MbyL-Mode to at least partially linearize the first order of the first output vector and to at least partially linearize the second order of the second output vector” and indicated that these features are identified as allowable subject matter because claims 13-15 and 18-20 did not have any prior art rejection.
Response: Examiner respectfully disagrees. Examiner has not indicated that these features are allowable. Further, examiner would like to point out that the claims 13-15 and 18-20 did not have a prior art rejection because of the 35 U.S.C. 112(b) issues. See MPEP 2173.06 II “where there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, it would not be proper to reject such a claim on the basis of prior art.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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