DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application. Claims 1-5, 7-9, 11-13 and 15-19 are currently amended; claims 6, 10, 14 and 20 are original.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Objections
Claims 2-4, 6, 9 and 16-18 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 2 lines 2-3 “the output floating-point number” should read “the one or more output floating-point numbers” instead for consistency of claim terminologies. Claims 7 and 16 recite a similar limitation in lines 4 and 2-3 respectively and are objected to for the same reason.
B. In claim 3 lines 4-5, “the operation result output floating-point number” should read “the operation result
C. In claim 4 line 3, “has a mantissa bit width is less than” should read “has a mantissa bit width [[is]] less than” instead for better clarity. Claim 18 recites a similar limitation in line 3 and is objected to for the same reason.
D. In claim 6 line 3, “a mantissa bit width” should read “the [[a]] mantissa bit width” instead because a mantissa bit width of the input floating-point number is already introduced in claim 5 from which the claim depends.
E. In claim 9 line 2, “the output floating-point number” should read “the one or more converted s” instead for consistency of claim terminologies. Claims 11-13 recite a similar limitation in lines 4, 4 and 4-5 respectively and are objected to for the same reason.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B. The “when” clause in claims 11-12 are contingent limitations that are not required to be performed if the condition(s) precedent are not met. See MPEP 2111.04 for more information.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 11-12, 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “the input floating-point number” in line 3. There is insufficient antecedent basis for this limitation in the claim. It is unclear whether this is supposed to refer to each floating point number in the first group or to something else. For purposes of examination, this is interpreted to refer to the a corresponding input floating point number in the first group. Claims 11-12 recite a similar limitation in lines 3 and 3 respectively and are rejected for the same reason.
Claim 13 recites “the input floating-point number” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. It is unclear whether this is supposed to refer to each floating point number in the first group or to something else. For purposes of examination, this is interpreted to refer to each floating point number in the first group.
Claim 14 recites “the input floating-point number” in line 1. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted to refer to the each floating point number in the first group.
Further, claim 14 recites “wherein a format of the input floating-point number satisfies the Institute of Electrical and Electronics Engineers (IEEE) binary floating point arithmetic standard, and a format of the output floating-point number does not satisfy the IEEE binary floating point arithmetic standard”. Claim 8 from which recites claim 14 recites in part “converting, by the multiplier accumulator, the operation result floating-point number to an output floating-point number of a selected type, wherein the selected type is one of the N types of floating-point numbers”. It is unclear how the output floating-point number does not satisfy the IEEE binary floating point arithmetic standard when it is of one of the N types of floating-point numbers and a format of each of the floating-point numbers in the first group satisfies the Institute of Electrical and Electronics Engineers (IEEE) binary floating point arithmetic standard. For purposes of examination, this is interpreted as “wherein a format of each floating point number in the first group satisfies the Institute of Electrical and Electronics Engineers (IEEE) binary floating point arithmetic standard, and a format of the one or more converted floating-point numbers does not satisfy the IEEE binary floating point arithmetic standard”.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-7 and 15-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “convert the operation result floating-point number provided by the each adjustment circuit to an output floating point number” in lines 27-28. This limitation lacks written description support because the specification fails to disclose the each adjustment circuit providing or generating the operation result floating-point number. Applicant indicated that support for the amendments to claims 1 and 15 are in paragraphs [00102 and 00154], however, the cited paragraphs do not disclose the each adjustment circuit providing or generating the operation result floating-point number. Furthermore, the claims itself recite that the operation result floating-point number is produced by the multiplier-accumulator in line 26 instead of the each adjustment circuit. Claim 15 recites a similar limitation and is rejected for the same reason. Claims 2-7 inherit the same deficiency as claim 1 by reason of dependence. Claims 16-20 inherit the same deficiency as claim 15 by reason of dependence.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Henry et al. (US 20190042244 A1), hereinafter Henry, in view of Pugh et al. (US 20210042087 A1), hereinafter Pugh, and Lin et al. (US 20200026991 A1), hereinafter Lin.
Regarding claim 8, Henry teaches a floating-point number multiplication calculation method performed by a hardware processor chip comprising a controller and an arithmetic logic unit having (Henry Figs. 4, 7A and 8B and paragraph [0123]; hardware processor chip - processor core 890; controller - front-end unit or decode circuitry; arithmetic logic unit - execution engine or execution unit; multiplier-accumulator - MAC circuits):
sending, by the controller, a first group of floating-point numbers to the arithmetic logic unit (ALU) for a first operation, wherein the controller utilizes N different types of floating-point numbers with N precisions, and the floating-point numbers in the first group are of one or more types of the N types of floating-point numbers (Henry Figs. 4 , 7A and 8B and paragraphs [0092-0093, 0118, 0137] first group of floating-point numbers - values A and/or B; first operation – accumulate operations operation);
receiving, by the ALU, the first group of floating-point numbers from the controller (Henry Figs. 4 , 7A and 8B and paragraphs [0121-0123, 0125, 0138] “At reference 704, the execution circuitry executes the decoded instruction. The execution includes converting values for each operand, each value being converted into a plurality of lower precision values at reference 712 … The execution further includes performing arithmetic operations among lower precision values converted from values for the plurality of the operands at reference 714. The arithmetic operations include the ones shown in FIGS. 1 and 4 and discussed in the related paragraphs herein above”);
converting, (Henry Figs. 4 , 7A and paragraph [0121] “At reference 704, the execution circuitry executes the decoded instruction. The execution includes converting values for each operand, each value being converted into a plurality of lower precision values at reference 712”; paragraph [0093] “Each of the values is then converted into two values in bfloat16 format. At references 404 and 406, the values in A and B in FP32 are approximated with values in bfloat16 format”; paragraph [0050] “The examples provided in this disclosure herein below use conversions from FP32 to bfloat16, and from FP32 to int8. Obviously, the embodiments of the invention are not so limited, and each of the values in one floating-point format ( e.g., a format in Table 2) may be converted (1) to multiple values in a lower precision float-point format ( e.g., another format that has less significand bits in Table 2)”; paragraph [0119] “each of the operand may indicate a vector (ID array), a matrix (2D array) that is in a floating-point format … The floating-point format may be one of standard FP16, FP32, FP64, FP128, or FP256, or a proprietary floating-point format that has its own definition of exponent width, significand
precision, and/or sign bit”; the one or more converted floating-point numbers are all bfloat16 numbers while the input floating-point number can be a combination of different precision in Table 2 (e.g. A can be FP32 while B can be FP16 or FP64);
receiving, by the multiplier-accumulator, a second group of floating-point numbers (Henry Figs. 4 , 7A and paragraph [0123]);
performing, by the multiplier accumulator, a second operation on the second group of floating-point numbers, wherein the second operation corresponds to the first operation, to generate an operation result floating-point number of the operation type (Henry Figs. 4 , 7A and paragraph [0123] “The execution further includes performing arithmetic operations among lower precision values converted from values for the plurality of the operands at reference 714 … For example, when the execution circuitry comprises one or more dedicated multiplier-accumulator (MAC) circuits, and the one or more dedicated MAC circuits are to perform integer multiply-accumulate operations”; paragraph [0125] operation result floating-point number – resulting value);
converting, by the multiplier accumulator, the operation result floating-point number to an output floating-point number of a selected type, wherein the selected type is one of the N types of floating-point numbers (Henry 4, 7 and paragraph [0125] “The execution additionally includes generating a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and storing the floating-point value at reference 716”); and
sending, by the multiplier-accumulator, the output floating-point number (Henry paragraph [0125] “The floating-point value may be stored in a location specified by the instruction ( e.g., memory, cache, or register). In one embodiment, the floating-point value is stored in a location that has stored the input operands”).
Henry does not explicitly teach a hardware processor chip comprising a controller and an arithmetic logic unit having N adjustment circuits and a multiplier-accumulator; receiving, by the ALU, the first group of floating-point numbers from the controller and directing each floating-point number in the first group to a corresponding one of the N adjustment circuits configured to process floating-point numbers of a type of said each floating-point number; converting, by each of the N adjustment circuits, each floating-point number of the first group directed thereto from a type of said each directed floating-point number to one or more converted floating-point numbers of an operation type of the multiplier-accumulator, wherein input floating-point numbers received by adjustment circuits of the N adjustment circuits have differing precisions, and the one or more converted floating-point numbers outputted by the adjustment circuits of the N adjustment circuits have a same precision; receiving, by the multiplier-accumulator, a second group of floating-point numbers from the N adjustment circuits, the second group of floating-point numbers comprising the one or more converted floating-point numbers of the operation type generated by the N adjustment circuits by converting the floating- point numbers of the first group; and sending, by the multiplier-accumulator, the output floating-point number to the controller.
However, on the same field of endeavor, Pugh discloses N adjustment circuits, each of the N adjustment circuits being configured to: obtain an input floating-point number of a corresponding type with a corresponding precision and convert the input floating-point number from the corresponding type to one or more output floating-point numbers of an operation type with an operation precision; provide a group of converted floating-point numbers from the N adjustment circuits as inputs for an operation to a multiplier-accumulator connected to the N adjustment circuits (Pugh Figs. 4-5 and paragraphs [0042, 0045-0047] “Each of the bit remap logics 430A-430D remaps the inputs based on a multiplication mode and byte selection mode input … In a floating-point mode that differs from the floating-point format used by the portion 500, the bit remap logics 430A-430D convert the inputs to a format expected by the portion 500”; N adjustment circuits - bit remap logics 430A-430D).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Henry using Pugh and configure the ALU to include conversion circuitry (i.e., bit remap logics) for each input to be converted in order to convert the inputs to the format expected by the MAC circuits by directing each input to a corresponding bit remap logic then converting each input and sending the converted inputs to the execution engine for the multiply-accumulate operations in order to implement a multiple mode arithmetic circuit that supports different floating point format combinations (Pugh paragraph [0046]).
Therefore, the combination of Henry as modified in view of Pugh teaches a hardware processor chip comprising a controller and an arithmetic logic unit having N adjustment circuits and a multiplier-accumulator; receiving, by the ALU, the first group of floating-point numbers from the controller and directing each floating-point number in the first group to a corresponding one of the N adjustment circuits configured to process floating-point numbers of a type of said each floating-point number; converting, by each of the N adjustment circuits, each floating-point number of the first group directed thereto from a type of said each directed floating-point number to one or more converted floating-point numbers of an operation type of the multiplier-accumulator, wherein input floating-point numbers received by adjustment circuits of the N adjustment circuits have differing precisions, and the one or more converted floating-point numbers outputted by the adjustment circuits of the N adjustment circuits have a same precision; receiving, by the multiplier-accumulator, a second group of floating-point numbers from the N adjustment circuits, the second group of floating-point numbers comprising the one or more converted floating-point numbers of the operation type generated by the N adjustment circuits by converting the floating- point numbers of the first group; and sending, by the multiplier-accumulator, the output floating-point number.
Henry as modified in view of Pugh does not explicitly teach sending, by the multiplier-accumulator, the output floating-point number to the controller.
However, on the same field of endeavor, Lin discloses outputting an output value from a multiply-accumulate unit to a controller (Lin Fig. 10 and paragraph [0070] “The multiplier and accumulator unit 1010 receives weights stored for the Nth synaptic layer from the memory system 502 to compute sum-of-products. The multiplier and accumulator unit provides the sum-of-products to the controller 504 as the output for the Nth synaptic layer”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Henry in view of Pugh using Lin and provide the output floating-point number to the controller such that the controller can store the output floating-point number to a location specified in the instruction (Henry paragraph [0125]).
Therefore, the combination of Henry as modified in view of Pugh and Lin teaches sending, by the ALU, the output floating-point number to the controller.
Regarding claim 9, Henry as modified in view of Pugh and Lin teaches all the limitations of claim 8 as stated above. Further, Henry as modified in view of Pugh and Lin teaches wherein for each of the N adjustment circuits an exponent bit width of the output floating-point number is greater than an exponent bit width of the input floating-point number (Pugh paragraph [0046] “an example, the portion 500 expects floating-point values with a 15-bit mantissa, a one-bit sign, and an 8-bit exponent. In this example, the multiple mode arithmetic circuit supports inputs and outputs using various combinations of 16-bit mantissas, 10-bit mantissas, 12-bit mantissas, 8-bit exponents, 6-bit exponents, and 5-bit exponents”; paragraph [0077]).
Regarding claim 10, Henry as modified in view of Pugh teaches all the limitations of claim 8 as stated above. Further, Henry as modified in view of Pugh teaches
wherein the multiplier-accumulator comprises an operation subcircuit and (Henry paragraph [0094, 0123] “the execution circuitry comprises one or more dedicated multiplier-accumulator (MAC) circuits, and the one or more dedicated MAC circuits are to perform integer multiply-accumulate operations”; operation subcircuit – MAC circuits);
(Henry Fig. 4 and Fig. 7A and paragraph [0125] “The execution additionally includes generating a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and storing the floating-point value at reference 716. The generation of the floating-point value includes the reconstructions shown in FIGS. 1 and 4 and discussed in the related paragraphs herein above”).
Henry does not explicitly teach wherein the multiplier-accumulator comprises an operation subcircuit and a format processing subcircuit, wherein the operation subcircuit performs the second operation on the second group of floating-point numbers of the operation type, and the method further comprises: receiving, by the format processing subcircuit, a mode signal indicating the selected type; wherein the format processing subcircuit converts the operation result floating-point number to the output floating-point number of the selected type based on the mode signal.
However, on the same field of endeavor, Pugh discloses a multiplier-accumulator that comprises a format processing subcircuit is configured to: receive a mode signal indicating an output type of floating-point numbers and convert the operation result floating-point number to the output floating point number of the selected type based on the mode signal (Pugh Fig. 8 and paragraph [0072] “In a floating-point mode that differs from the floating-point format used by the portions 500-700, the logics 850A-850B convert the intermediate outputs to a format expected by the FPGA … Based on the output format and the format operated on the portions 500-700, the logics 850A-850B convert the output values”; format processing subcircuit – logic block 850A/850B).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Henry using Pugh and configure the execution circuitry to include output format circuitry to convert the internal floating-point format used by the MAC circuits back to the floating-point format (Pugh paragraph [0072]). As discussed, Henry discloses converting the resulting value from the arithmetic operations back into the floating-point format. Therefore, it would be obvious to provide a circuitry for implementing the conversion process.
Therefore, the combination of Henry as modified in view of Pugh teaches wherein the multiplier-accumulator comprises an operation subcircuit and a format processing subcircuit, wherein the operation subcircuit performs the second operation on the second group of floating-point numbers of the operation type, and the method further comprises: receiving, by the format processing subcircuit, a mode signal indicating the selected type; wherein the format processing subcircuit converts the operation result floating-point number to the output floating-point number of the selected type based on the mode signal.
Regarding claim 11, Henry as modified in view of Pugh and Lin teaches all the limitations of claim 8 as stated above. Further, Henry as modified in view of Pugh and Lin teaches wherein the step of converting by each of the N adjustment circuits comprises: when a mantissa bit width of the input floating-point number is less than or equal to a mantissa bit width of the output floating-point number of the operation type, converting the input floating- point number to one output floating-point number, wherein a value represented by the input floating-point number is equal to a value represented by the one output floating-point number (Pugh paragraphs [0046-0047] “In a floating-point mode that differs from the floating-point format used by the portion 500, the bit remap logics 430A-430D convert the inputs to a format expected by the portion 500. In an example, the portion 500 expects floating-point values with a 15-bit mantissa, a one-bit sign, and an 8-bit exponent. In this example, the multiple mode arithmetic circuit supports inputs and outputs using various combinations of 16-bit mantissas, 10-bit mantissas, 12-bit mantissas, 8-bit exponents, 6-bit exponents, and 5-bit exponents. Based on the input format and the format expected by the portion 500, the bit remap logics 430A-430D convert the input values. In this example, selection of the input floating-point format is in response to a mode selection input. The bit remap logics 430A-430D, in some example embodiments, perform sign extension. As a result, operands that are smaller than the size of the input values accepted by the arithmetic blocks (e.g., the multipliers 520A-520H) are routed using only the routing resources necessary for the operands and sign-extended by the bit remap logics 430A-430D prior to use by the arithmetic blocks”).
Regarding claim 12, Henry as modified in view of Pugh and Lin teaches all the limitations of claim 8 as stated above. Further, Henry as modified in view of Pugh and Lin teaches wherein the step of converting by each of the N adjustment circuits comprises: when a mantissa bit width of the input floating-point number is greater than a mantissa bit width of the output floating-point number of the operation type, converting the input floating-point number into a plurality of output floating-point numbers, wherein a value represented by the input floating-point number is same as a value represented by a sum of the plurality of output floating-point numbers (Henry Figs. 4-5 and paragraph [0093] “At references 404 and 406, the values in A and B in FP32 are approximated with values in bfloat16 format. Values of A1 and B1 (in bfloat16 format) are approximation of the ones of A and B (in FP32 format) and have lower precision than the ones of A and B because the bfloat16 has less mantissa bits than FP32 (8 bits vs. 24 bits). A1 and B1 has values represented by the most significant 8-bit mantissa of the ones in A and B as shown at references 412 and 416. At references 414 and 416, the reminders of A and B after subtracting A1 and B1 are approximated in bfloat16 format as A2 and B2, respectively”; paragraphs [0116-0117] “One may also split each FP32 value into three Bfloat16 … Three bfloat16 have 24-bit significand precision in total, thus conversion from a FP32 value (which as 24-bit significand precision also) to three bloat16 values does not lose accuracy”).
Regarding claim 13, Henry as modified in view of Pugh and Lin teaches all the limitations of claim 8 as stated above. Further, Henry as modified in view of Pugh and Lin teaches wherein in the step of converting by each of the N adjustment circuits a quantity of output floating-point numbers corresponding to the input floating-point number is determined based on a mantissa bit width of an input floating-point number and a mantissa bit width of the output floating-point number of the operation type (Henry paragraph [0017] “Three bfloat16 have 24-bit significand precision in total, thus conversion from a FP32 value (which as 24-bit significand precision also) to three bloat16 values does not lose accuracy”; paragraph [0122] “The number of the converted lower precision values per value may depend on the additional operand for the QoS requirement in on embodiment. For example, when the accuracy of the arithmetic operations is expected to be high, each value may be converted to more lower precision values ( e.g., each A may be converted into A1, A2, and A3, instead”).
Regarding claim 14, Henry as modified in view of Pugh and Lin teaches all the limitations of claim 8 as stated above. Further, Henry as modified in view of Pugh and Lin teaches wherein a format of the input floating-point number satisfies the Institute of Electrical and Electronics Engineers (IEEE) binary floating point arithmetic standard, and a format of the output floating-point number does not satisfy the IEEE binary floating point arithmetic standard (Henry Fig. 4 and paragraph [0094] “The floating-point arithmetic operation hardware circuits (e.g., MAC and/or FMA circuits) implementing such accumulation/accumulators do not comply with the present IEEE standards, but the mixed-precision decomposition of operations allows embodiments of the invention to perform arithmetic operations with a higher precision”).
Allowable Subject Matter
Claims 1-7 and 15-20 would be allowable if rewritten to overcome the 35 U.S.C. 112(a) rejection discussed above.
None of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claim, the feature of “convert the operation result floating-point number provided by the each adjustment circuit to an output floating point number” as recited in claims 1 and 15.
Response to Arguments
In view of amendments made, the objection to the drawings, the specification and the claims has been withdrawn. However, the amendments made raises new objections to the specification and the claims as discussed above.
The amendments made to claims 13-14 do not overcome the 35 U.S.C. 112(b) rejection.
Applicant's arguments filed 07/21/2026, see remarks page 17-18, with respect to the 35 U.S.C. 103 rejection of claims 8-14 have been fully considered but they are not persuasive.
Applicant argues the following:
1.) the combination of Henry, Pugh, and Lin does not disclose input floating-point numbers received by adjustment circuits of the N adjustment circuits have differing precisions, and the output floating-point numbers outputted by the adjustment circuits of the N adjustment circuits have a same precision.
Response: Examiner respectfully disagrees. Figure 4 and paragraph [0092-0093] discloses that the output of the conversion are bfloat16. Therefore, the output floating-point numbers have a same precision. Furthermore, paragraph [0050] discloses that the input operands A or B can be in any floating-point format disclosed in Table 2 and paragraph [0119] discloses that each input operand A and B may be one of standard FP16, FP32, FP64, FP128, or FP256, or a proprietary floating-point format that has its own definition of exponent width, significand precision, and/or sign bit. Therefore, A and B can have different precisions. On the other hand, Pugh discloses N adjustment circuits each configured to: obtain an input floating-point number of a corresponding type with a corresponding precision and convert the input floating-point number to one or more output floating-point numbers of an operation type with an operation precision in Figures 4-5 and paragraphs [0042, 0045-0047]. It would be obvious to combine Henry and Pugh in order to implement a multiple mode arithmetic circuit that supports different floating point format combinations (Pugh paragraph [0046]). Therefore, the combination of Henry and Pugh teaches input floating-point numbers received by adjustment circuits of the N adjustment circuits have differing precisions, and the output floating-point numbers outputted by the adjustment circuits of the N adjustment circuits have a same precision.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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