DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Request for Continued Examination, filed 25 July 2025.
Acknowledgment is made of applicant’s amendment, filed on 25 June 2025. The changes and remarks disclosed therein have been considered.
Claims 1-20 are pending in the application. Claims 1, 14 and 20 are currently amended. Claims 1, 14 and 20 are independent claims.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to because in fig. 3C reference character “15” should be replaced with reference character --24--.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In para. [0100] ll. 2-3, “the first and third switching electrodes 21 and 22” should be replaced with --the first and third switching electrodes 21 and 23--.
In para. [0108] ll. 3-4, 8 and 11-12, “the second tie-down contact 42” should be replaced with --the second tie-down contact 43--.
In para. [0108] ll. 3, “the second switching electrode 22” should be replaced with --the third switching electrode 23--.
Appropriate correction is required.
Applicant is advised to thoroughly review the specification and correct any other errors that may be present.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 20 recites “A static random access memory (SRAM), comprising: a first active pattern having a letter H planar shape; a second active pattern having a letter H planar shape and being spaced apart from the first active pattern in a first direction; a first switching electrode vertically overlapping the first active pattern, the first switching electrode extending in the first direction on the first active pattern; a second switching electrode that vertically overlaps the first active pattern and the second active pattern, the second switching electrode being spaced apart from the first switching electrode in the first direction, and extending in the first direction on the first active pattern and the second active pattern; a third switching electrode that vertically overlaps the first active pattern and the second active pattern, the third switching electrode being spaced apart from the first switching electrode in a second direction perpendicular to the first direction, and extending in the first direction on the first active pattern and the second active pattern; a fourth switching electrode that vertically overlaps the second active pattern, the fourth switching electrode being spaced apart from the third switching electrode in the first direction, and extending in the first direction on the second active pattern; and a buried oxide layer disposed directly on a substrate, wherein a top surface plane of the first switching electrode is coplanar with: a top surface plane of a first electrode of a pass transistor of the first active pattern, a top surface plane of a second electrode of the pass transistor, a top surface plane of a first electrode of a pull-down transistor of the first active pattern, a top surface plane of a second electrode of the pull-down transistor, a top surface plane of a first electrode of a pull-up transistor of the second active pattern, and a top surface plane of a second electrode of the pull-up transistor, wherein a bottom surface plane of the first switching electrode is coplanar with: a bottom surface plane of the first electrode of the pass transistor, a bottom surface plane of the second electrode of the pass transistor, a bottom surface plane of the first electrode of the pull-down transistor, a bottom surface plane of the second electrode of the pull-down transistor, a bottom surface plane of the first electrode of the pull-up transistor, and a bottom surface plane of the second electrode of the pull-up transistor, and wherein the first switching electrode, the first electrode and the second electrode of the first pass transistor, the first electrode and the second electrode of the first pull-down transistor, and the first electrode and the second electrode of the first pull-up transistor are disposed directly on top of a top surface of the buried oxide layer” (emphasis added).
There is no support in the specification regarding a first switching electrode (i.e. a gate electrode) that overlaps a first active region and is coplanar with:
first and second electrodes (i.e. source and drain regions) of the pass transistor (PG1);
first and second electrodes (i.e. source and drain regions) of the pull-down transistor (PD1);
first and second electrodes (i.e. source and drain regions) of the pull-up transistor (PU1).
How can the gate electrode overlap the active region in which the source and drain regions are disposed and also be coplanar with bottom and top surfaces of the source and drain regions? The specification discloses that a gate insulating layer may be disposed between the first switching electrode and the active region. How can there be a gate insulating layer between the first switching electrode and the active region and also have the first switching electrode coplanar with the active region (i.e. the first and second electrodes of PG1, PD1, PU1)? The specification is silent regarding these limitations. There are no drawings supporting these limitations. Clarification in the claim is required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites “A static random access memory (SRAM), comprising: a first active pattern having a letter H planar shape; a second active pattern having a letter H planar shape and being spaced apart from the first active pattern in a first direction; a first switching electrode vertically overlapping the first active pattern, the first switching electrode extending in the first direction on the first active pattern; a second switching electrode that vertically overlaps the first active pattern and the second active pattern, the second switching electrode being spaced apart from the first switching electrode in the first direction, and extending in the first direction on the first active pattern and the second active pattern; a third switching electrode that vertically overlaps the first active pattern and the second active pattern, the third switching electrode being spaced apart from the first switching electrode in a second direction perpendicular to the first direction, and extending in the first direction on the first active pattern and the second active pattern; a fourth switching electrode that vertically overlaps the second active pattern, the fourth switching electrode being spaced apart from the third switching electrode in the first direction, and extending in the first direction on the second active pattern; and a buried oxide layer disposed directly on a substrate, wherein a top surface plane of the first switching electrode is coplanar with: a top surface plane of a first electrode of a pass transistor of the first active pattern, a top surface plane of a second electrode of the pass transistor, a top surface plane of a first electrode of a pull-down transistor of the first active pattern, a top surface plane of a second electrode of the pull-down transistor, a top surface plane of a first electrode of a pull-up transistor of the second active pattern, and a top surface plane of a second electrode of the pull-up transistor, wherein a bottom surface plane of the first switching electrode is coplanar with: a bottom surface plane of the first electrode of the pass transistor, a bottom surface plane of the second electrode of the pass transistor, a bottom surface plane of the first electrode of the pull-down transistor, a bottom surface plane of the second electrode of the pull-down transistor, a bottom surface plane of the first electrode of the pull-up transistor, and a bottom surface plane of the second electrode of the pull-up transistor, and wherein the first switching electrode, the first electrode and the second electrode of the first pass transistor, the first electrode and the second electrode of the first pull-down transistor, and the first electrode and the second electrode of the first pull-up transistor are disposed directly on top of a top surface of the buried oxide layer” (emphasis added).
It is unclear how a first switching electrode (i.e. a gate electrode) can overlap a first active region and also be coplanar with bottom and top surfaces of:
first and second electrodes (i.e. source and drain regions) of the PG;
first and second electrodes (i.e. source and drain regions) of the PD1;
first and second electrodes (i.e. source and drain regions) of the PU1.
How can the gate electrode overlap the active region in which the source and drain regions are disposed and also be coplanar with bottom and top surfaces of the source and drain regions? The specification is silent regarding these limitations. There are no drawings supporting these limitations. Accordingly, this claim is vague and indefinite. Clarification in the claim is required.
Claim 20 recites the limitations "the first pass transistor…the first pull-down transistor…the first pull-up transistor". There is insufficient antecedent basis for these limitations in the claim. It is suggested that “first” be deleted.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 14 Jule 2022. The information therein was considered.
Allowable Subject Matter
Claims 1-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 1, an integrated circuit, comprising: a first n-type metal oxide semiconductor (NMOS) region comprising a first electrode of a first pass transistor, a second electrode of the first pass transistor, a first electrode of a first pull- down transistor, and a second electrode of the first pull-down transistor; a second NMOS region comprising a first electrode of a second pass transistor, a second electrode of the second pass transistor, a first electrode of a second pull-down transistor, and a second electrode of the second pull-down transistor; a first p-type MOS (PMOS) region between the first NMOS region and the second NMOS region, and comprising a first electrode of a first pull-up transistor and a second electrode of the first pull-up transistor; a second PMOS region between the first PMOS region and the second NMOS region, and comprising a first electrode of a second pull-up transistor and a second electrode of the second pull-up transistor; a first active bridge extending in a first direction and coupling the first NMOS region to the first PMOS region; and a buried oxide layer disposed directly on a substrate, wherein each of the first NMOS region, the second NMOS region, the first PMOS region, and the second PMOS region extends in a second direction perpendicular to the first direction, and wherein a top surface plane of the first active bridge is coplanar with: a top surface plane of the first electrode of the first pass transistor, a top surface plane of the second electrode of the first pass transistor, a top surface plane of the first electrode of the first pull-down transistor, a top surface plane of the second electrode of the first pull-down transistor, a top surface plane of the first electrode of the first pull-up transistor, and a top surface plane of the second electrode of the first pull-up transistor, wherein a bottom surface plane of the first active bridge is coplanar with: a bottom surface plane of the first electrode of the first pass transistor, a bottom surface plane of the second electrode of the first pass transistor, a bottom surface plane of the first electrode of the first pull-down transistor, a bottom surface plane of the second electrode of the first pull-down transistor, a bottom surface plane of the first electrode of the first pull-up transistor, and a bottom surface plane of the second electrode of the first pull-up transistor, and wherein the first active bridge, the first electrode and the second electrode of the first pass transistor, the first electrode and the second electrode of the first pull-down transistor, and the first electrode and the second electrode of the first pull-up transistor are disposed directly on top of a top surface of the buried oxide layer; and as recited in independent claim 14, an integrated circuit, comprising: a substrate comprising a first well region doped with a first p-type dopant and a second well region doped with a first n-type dopant; a buried oxide layer disposed directly on the substrate and comprising an insulating material; and an active layer separated from the substrate by the buried oxide layer, the buried oxide layer being between the substrate and the active layer, wherein the active layer comprises: a first electrode of a first pass transistor doped with a second n-type dopant; a second electrode of the first pass transistor doped with a third n-type dopant; a first electrode of a first pull-down transistor doped with a fourth n-type dopant; a second electrode of the first pull-down transistor doped with a fifth n-type dopant; a first electrode of a first pull-up transistor doped with a second p-type dopant; a second electrode of the first pull-up transistor doped with a third p-type dopant; and an active bridge configured to electrically couple the first electrode of the first pass transistor, the second electrode of the first pull-down transistor, and the second electrode of the first pull-up transistor, wherein a top surface plane of the active bridge is coplanar with: a top surface plane of the first electrode of the first pass transistor, a top surface plane of the second electrode of the first pass transistor, a top surface plane of the first electrode of the first pull-down transistor, a top surface plane of the second electrode of the first pull-down transistor, a top surface plane of the first electrode of the first pull-up transistor, and a top surface plane of the second electrode of the first pull-up transistor, wherein a bottom surface plane of the active bridge is coplanar with: a bottom surface plane of the first electrode of the first pass transistor, a bottom surface plane of the second electrode of the first pass transistor, a bottom surface plane of the first electrode of the first pull-down transistor, a bottom surface plane of the second electrode of the first pull-down transistor, a bottom surface plane of the first electrode of the first pull-up transistor, and a bottom surface plane of the second electrode of the first pull-up transistor, and wherein the active bridge, the first electrode and the second electrode of the first pass transistor, the first electrode and the second electrode of the first pull-down transistor, and the first electrode and the second electrode of the first pull-up transistor are disposed directly on top of a top surface of the buried oxide layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liaw US 7,176,125 teaches an SRAM cell including storage nodes implemented using local interconnects.
Hirano et al. US 2008/0179676 teach a SRAM cell formed in a SOI board, electrical coupling between a drain region of a driver transistor and a source/drain region of an access transistor, and a drain region of a load transistor, are established by wiring structures including a PN junction.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 05/05/2026
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