DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 5 of Fig. 8 in the reply filed on 09/11/2025 is acknowledged. The traversal is on the ground(s) that at least claim 11 is generic to Species 1-7, and Species 7 being identified as claim 17 is inappropriate. These are minor issues and can be corrected easily. The following are the statements of corrections:
The term “Species 7 of claim 17” on the pages 2-4 of the Requirement of Restriction mailed on 07/16/2025 is corrected as “Species 7 of the embodiment of paragraph [0009] of the specification.”
The term “none is generic” on the page 3 of the Requirement of Restriction mailed on 07/16/2025 is corrected as “claim 11 is generic.”
Claim 17 is claiming the embodiment of paragraph [0009] of the specification. There is no change on the content of the restriction after the corrections.
The requirement is still deemed proper and is therefore made FINAL.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 09/11/2025.
Claim 17 does not read on the elected Species 5 of Fig. 8. Claim 17 states in the 4th to 7th lines of the claim: “a first wiring structure inside the first trench and including an upper surface coplanar with an upper surface of the interlayer insulating film; and a second wiring structure placed inside the second trench and including an upper surface lower than the upper surface of the interlayer insulating film”, which reads on Fig. 8 of first wiring structure of 110, the first trench of the trench of 150 filled with 110, the second wiring structure of 210, and the second trench of the trench of 150 filled with 210. Fig. 8 shows that the first trench of the trench of 150 filled with 110 has a width of a bottom surface being larger than a width of a bottom surface of a width of a bottom surface of the second trench of the trench of 150 filled with 210 (emphasis added), which is opposite what is claimed in 2nd to 3rd lines of claim 17: “a width of a bottom surface of the first trench being smaller than a width of a bottom surface of the second trench” (emphasis added). Thus, claim 17 does not read on Fig. 8, and claim 17 and its dependent claims are withdrawn from consideration.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/18/2022 and 09/16/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-6, 9, 11 and 13-15 is/are rejected under 35 U.S.C. 102(a)(1)(a)(2) as being anticipated by Naganuma et al. (US 2011/0180307 A1).
Regarding claim 1, Naganuma et al. teach a semiconductor device (rigid sections 110; Fig. 30A, [115]) comprising: a first wiring structure (filled conductor 14; Fig. 30A, [0133]) which includes a first material (the material of 14), and has a first width (the horizontal width of the lowest surface of 14) in a first direction (the horizontal direction in Fig. 30A), the first width (the horizontal width of the lowest surface of 14) on a lowest surface of the first wiring structure (14); and a second wiring structure (filled conductor 12; Fig. 30A, [0133]) which includes a second material (the material of 12), is spaced apart from the first wiring structure (14) in the first direction (the horizontal direction in Fig. 30A), and has a second width (the horizontal width of the lowest surface of 12) in the first direction (the horizontal direction in Fig. 30A) that is less than the first width (the horizontal width of the lowest surface of 14), the second width (the horizontal width of the lowest surface of 12) on a lowest surface of the second wiring structure (12) wherein a highest surface of the first wiring structure (14) has a third width (the horizontal width of the highest surface of 14) in the first direction (the horizontal direction in Fig. 30A) that is less than the first width (the horizontal width of the lowest surface of 14), and a highest surface of the second wiring structure (12) has a fourth width (the horizontal width of the highest surface of 12) in the first direction (the horizontal direction in Fig. 30A) that is less than the second width (the horizontal width of the lowest surface of 12).
Regarding claim 3, Naganuma et al. teach the semiconductor device of claim 1, wherein the highest surface of the second wiring structure (the highest surface of 12) is lower than the highest surface of the first wiring structure (the highest surface of 14).
Regarding claim 5, Naganuma et al. teach the semiconductor device of claim 1, wherein a lowest surface of the first wiring structure (the lowest surface of 14) and a lowest surface of the second wiring structure (the lowest surface of 12) are coplanar (see Fig. 30A).
Regarding claim 6, Naganuma et al. teach the semiconductor device of claim 1, further comprising: an upper wiring line (the top portion of 34 above the top surface of 30a; Fig. 30A, [0133, 0116]) on (above) the first wiring structure (14) and the second wiring structure (12) and extending in the first direction (the horizontal direction in Fig. 30A); and an upper via (the bottom portion of 34 below the top surface of 30a; Fig. 30A, [0133, 0116]) on the first wiring structure (14), and connecting (physically with intervening layer) the first wiring structure (14) with the upper wiring line (the top portion of 34 above the top surface of 30a).
Regarding claim 9, Naganuma et al. teach the semiconductor device of claim 1, wherein the first wiring structure (14) and the second wiring structure (12) extend in a second direction (the vertical direction in Fig. 30A) intersecting the first direction (the horizontal direction in Fig. 30A).
Regarding claim 11, Naganuma et al. teach a semiconductor device (rigid sections 110; Fig. 30A, [115]) comprising: a first wiring structure (filled conductor 14; Fig. 30A, [0133]) which includes a first material (the material of 14), and has a first width (the horizontal width of the lowest surface of 14) in a first direction (the horizontal direction in Fig. 30A) on a lowest surface (the lowest surface of 14); a second wiring structure (filled conductor 12; Fig. 30A, [0133]) which includes a second material (the material of 12), is spaced apart from the first wiring structure (14) in the first direction (the horizontal direction in Fig. 30A), and has a second width (the horizontal width of the lowest surface of 12) in the first direction (the horizontal direction in Fig. 30A) less than the first width (the horizontal width of the lowest surface of 14) on a lowest surface (the lowest surface of 12); and an upper via (the bottom portion of 34 below the top surface of 30a; Fig. 30A, [0133, 0116]) connected (physically with intervening layer) with the first wiring structure (14), wherein the lowest surface of the first wiring structure (the lowest surface of 14) and the lowest surface of the second wiring structure (the lowest surface of 12) are coplanar, and a highest surface of the first wiring structure (the highest surface of 14) is above a highest surface of the second wiring structure (the highest surface of 12).
Regarding claim 13, Naganuma et al. teach the semiconductor device of claim 11, further comprising: a wiring capping film (20a; Fig. 30A, [0118]) on the highest surface of the second wiring structure (the highest surface of 12).
Regarding claim 14, Naganuma et al. teach the semiconductor device of claim 11, wherein the highest surface of the first wiring structure (the highest surface of 14) has a third width (the horizontal width of the highest surface of 14; Fig. 30A) in the first direction (the horizontal direction in Fig. 30A) that is smaller than the first width (the horizontal width of the lowest surface of 14), and the highest surface of the second wiring structure (the highest surface of 12) has a fourth width (the horizontal width of the highest surface of 12; Fig. 30A) in the first direction (the horizontal direction in Fig. 30A) that is less than the second width (the horizontal width of the lowest surface of 12).
Regarding claim 15, Naganuma et al. teach the semiconductor device of claim 11, wherein a width of the first wiring structure (the horizontal width of 14) in the first direction (the horizontal direction in Fig. 30A) decreases going away from the lowest surface of the first wiring structure (the lowest surface of 14; Fig. 30A), and a width of the second wiring structure (the horizontal width of 12) in the first direction (the horizontal direction in Fig. 30A) decreases going away from the lowest surface of the second wiring structure (the lowest surface of 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naganuma et al. as applied to claims 1 and 11 above, and further in view of Bao et al. (US 20210167006 A1).
Regarding claim 4, Naganuma et al. teach the semiconductor device of claim 1, wherein the first material (the material of 14) includes copper (Cu) ([0174]), and the second material (the material of 12).
Naganuma et al. do not teach the second material includes ruthenium (Ru).
In the same field of endeavor of semiconductor manufacturing, Bao et al. teach the second material (the material of the narrow metal line 102; Fig. 1B, [0032]) includes ruthenium (Ru) ([0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Naganuma et al. and Bao et al., and to have the second wiring structure 12 of Naganuma et al. made of Ru, because the second wiring structure 12 of Naganuma et al. is narrower than the first wiring structure 14 of Naganuma et al. (see Fig. 30A of Naganuma et al.) and Bao et al. teach that Ru has a lower resistance than Cu at the narrow line width ([0035]).
Regarding claim 12, Naganuma et al. teach the semiconductor device of claim 11, wherein the first material (the material of 14) includes copper (Cu) ([0174]), and the second material (the material of 12).
Naganuma et al. do not teach the second material includes ruthenium (Ru).
In the same field of endeavor of semiconductor manufacturing, Bao et al. teach the second material (the material of the narrow metal line 102; Fig. 1B, [0032]) includes ruthenium (Ru) ([0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Naganuma et al. and Bao et al., and to have the second wiring structure 12 of Naganuma et al. made of Ru, because the second wiring structure 12 of Naganuma et al. is narrower than the first wiring structure 14 of Naganuma et al. (see Fig. 30A of Naganuma et al.) and Bao et al. teach that Ru has a lower resistance than Cu at the narrow line width ([0035]).
Claim(s) 7-8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naganuma et al. as applied to claims 1 and 11 above, and further in view of Yang et al. (US 20210257299 A1).
Regarding claim 7, Naganuma et al. teach the semiconductor device of claim 1, wherein the first wiring structure (14).
Naganuma et al. do not teach the first wiring structure includes a barrier film, and a filling film on the barrier film, wherein the filling film includes the first material.
In the same field of endeavor of semiconductor manufacturing, Yang et al. teach the first wiring structure (17L/18L/20L/22S; Fig. 6, [0037]) includes a barrier film (17L; Fig. 6, [0037]), and a filling film (22S; Fig. 6, [0037]) on the barrier film (17L), wherein the filling film (22S) includes the first material (copper; [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Naganuma et al. and Yang et al., and to substitute the first wiring structure 14 of Naganuma et al. with the first wiring structure 17L/18L/20L/22S of Yang et al., because the first wiring structure 17L/18L/20L/22S of Yang et al. can preserve the reliability of the copper-containing electrically conductive structure as taught by Yang et al. ([0037]).
Regarding claim 8, Naganuma et al. teach the semiconductor device of claim 1, wherein the first wiring structure (14), and the second wiring structure (12).
Naganuma et al. do not teach the first wiring structure includes a barrier film on a side part, and the second wiring structure does not include barrier film on a side part.
In the same field of endeavor of semiconductor manufacturing, Yang et al. teach the first wiring structure (17L/18L/20L/22S; Fig. 6, [0037]) includes a barrier film (17L; Fig. 6, [0037]) on a side part (the left side surface), and the second wiring structure (16L/18S; Fig. 6, [0035]) does not include barrier film (16L; Fig. 6, [0035]) on a side part (the top side surface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Naganuma et al. and Yang et al., and to substitute the first wiring structure 14 of Naganuma et al. with the first wiring structure 17L/18L/20L/22S of Yang et al., and substitute the second wiring structure 12 of Naganuma et al. with the second wiring structure 16L/18S of Yang et al., because the first wiring structure 17L/18L/20L/22S of Yang et al. can preserve the reliability of the copper-containing electrically conductive structure and the second wiring structure 16L/18S of Yang et al. can prevents a conductive material from diffusing there through as taught by Yang et al. ([0037, 0027]).
Regarding claim 16, Naganuma et al. teach the semiconductor device of claim 11, further comprising: an interlayer insulating film (30a; Fig. 30A, [0116]) on the first wiring structure (14) and the second wiring structure (12), wherein the first wiring structure (14).
Naganuma et al. do not teach the first wiring structure includes a barrier film, a liner film placed on the barrier film, and a filling film on the liner film and including the first material.
In the same field of endeavor of semiconductor manufacturing, Yang et al. teach the first wiring structure (17L/18L/20L/22S; Fig. 6, [0037]) includes a barrier film (17L; Fig. 6, [0037]), a liner film (18L; Fig. 6, [0037]) placed on the barrier film (17L), and a filling film (22S; Fig. 6, [0037]) on the liner film (18L) and including the first material (copper; [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Naganuma et al. and Yang et al., and to substitute the first wiring structure 14 of Naganuma et al. with the first wiring structure 17L/18L/20L/22S of Yang et al., because the first wiring structure 17L/18L/20L/22S of Yang et al. can preserve the reliability of the copper-containing electrically conductive structure as taught by Yang et al. ([0037]).
Allowable Subject Matter
Claims 2 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of " a wiring capping film on the second wiring structure, the highest surface of the wiring capping film and the highest surface of the first wiring structure are coplanar " as recited in claim 2 and “an interlayer insulating film on the first wiring structure and the second wiring structure, wherein a highest surface of the first wiring structure is coplanar with an upper surface of the interlayer insulating film, and a highest surface of the second wiring structure is below the upper surface of the interlayer insulating film” as recited in claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Li et al. (US 20230352406 A1) teach in Fig. 6 wiring structures 30 having the horizontal width of the lowest surface wider than the horizontal width of the highest surface .
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 12/22/2025