Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is nonfinal and is in response to claims filed on 07/18/2022. Claims 1-10, 12, 14-20 and 25-26 are pending for examination.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 07/18/2022 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “a delay element chain”. It is unclear if the “delay element chain” of claim 2 is the same delay elements as the “plurality of second delay elements connected to each other in series” of claim 1. For examination purposes, examiner has interpreted them to be the same delay elements.
Claims 3-7 are rejected for being dependent on an above rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 20 rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20200174752 A1) hereinafter Huang in view of Vasyltsov et al. (“Fast Digital TRNG Based on Metastable Ring Oscillator”) hereinafter Vasyltsov.
With regards to claim 1, Huang teaches A random number generating circuit comprising: (Huang [0007]: The true random number generator according to the embodiment of the present disclosure includes)
an oscillation circuit comprising a plurality of first delay elements connected to each other in series to generate an oscillation signal; (Huang [0022]: A D terminal of a D flip-flop receives a high-frequency oscillation signal generated by a high-frequency oscillator; Huang [0017]: FIG. 3 is a schematic structural diagram of a high-frequency oscillation loop; Huang Fig. 3: shows the oscillation circuit as a plurality of delay elements in series)
a sampling circuit comprising a plurality of second delay elements connected to each other in series to generate a plurality of sampling signals (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop; Huang Fig. 2: Shows a plurality of delay elements connected in series generating a plurality of sampling signals using the flip-flops)
by sampling the oscillation signal at a plurality of sampling points in time based on the plurality of second delay elements; (Huang [0036]: Further, in each of the random entropy source circuits 200, the input terminal of each of the flip-flops 202 is connected to the output terminal of the inverter Inv corresponding to the flip-flop 202, the clock input terminal of each of the flip-flops 202 receives the sampling clock signal fs outputted by the low-frequency sampling oscillation loop Sample OSC, and output terminals of the flip-flops 202 are respectively connected to different input terminals of the XOR unit 201. One entropy source sampling process is performed at the output terminal of each of the inverters in the random entropy source circuit 200; (therefore the oscillation signal is sampled at multiple points in time))
and a random number determining circuit configured to generate a random number based on a target sampling point in time associated with a target sampling signal (Huang [0033]: Output terminals of the multiple random entropy source circuits 200 are respectively connected to different input terminals of the XOR circuit 100. A random number sequence is outputted from an output terminal of the XOR circuit 100)
[in which a first logic level transition occurs] from among the plurality of sampling signals, wherein the plurality of sampling points comprises the target sampling point (Huang [0022]: A D terminal of a D flip-flop receives a high-frequency oscillation signal generated by a high-frequency oscillator, and a clock signal terminal of the D flip-flop receives a low-frequency clock signal, and an output terminal of the D flip-flop outputs a random sequence. The high-frequency oscillation signal is sampled by using the low-frequency clock signal with jitter, or the high-frequency oscillation signal with jitter is sampled by using the low-frequency clock signal, to obtain a true random number).
Huang fails to teach in which a first logic level transition occurs [from among the plurality of sampling signals, wherein the plurality of sampling points comprises the target sampling point]
However, Vasyltsov teaches in which a first logic level transition occurs [from among the plurality of sampling signals, wherein the plurality of sampling points comprises the target sampling point] (Vasyltsov Page 13 Paragraph 2: We measured the time of the first transition of the signal starting from 30 ns to 40 ns after switching to generation mode).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Huang with the first transition as taught by Vasyltsov. One of ordinary skill in the art would be motivated to make this combination because the main advantage of the proposed method is the significant decrease in the latency of TRNG due to earlier sampling times as taught by Vasyltsov (Vasyltsov Page 6 paragraph 3).
With regards to claim 20, Huang teaches A method of operating a random number generating circuit for generating a random number based on a plurality of sampling signals, the method comprising: generating an oscillation signal by a ring oscillator; (Huang [0022]: A D terminal of a D flip-flop receives a high-frequency oscillation signal generated by a high-frequency oscillator; Huang [0017]: FIG. 3 is a schematic structural diagram of a high-frequency oscillation loop; Huang Fig. 3: shows the oscillation circuit as a ring oscillator)
generating the plurality of sampling signals by sampling the oscillation signal at different sampling points in time; (Huang [0036]: Further, in each of the random entropy source circuits 200, the input terminal of each of the flip-flops 202 is connected to the output terminal of the inverter Inv corresponding to the flip-flop 202, the clock input terminal of each of the flip-flops 202 receives the sampling clock signal fs outputted by the low-frequency sampling oscillation loop Sample OSC, and output terminals of the flip-flops 202 are respectively connected to different input terminals of the XOR unit 201. One entropy source sampling process is performed at the output terminal of each of the inverters in the random entropy source circuit 200; (therefore the oscillation signal is sampled at multiple points in time))
determining a sampling point associated with a target sampling signal [in which a first logic level transition occurs,] from among the plurality of sampling signals; (Huang [0022]: A D terminal of a D flip-flop receives a high-frequency oscillation signal generated by a high-frequency oscillator, and a clock signal terminal of the D flip-flop receives a low-frequency clock signal, and an output terminal of the D flip-flop outputs a random sequence. The high-frequency oscillation signal is sampled by using the low-frequency clock signal with jitter, or the high-frequency oscillation signal with jitter is sampled by using the low-frequency clock signal, to obtain a true random number)
and generating the random number based on the sampling point of the target sampling signal (Huang [0033]: Output terminals of the multiple random entropy source circuits 200 are respectively connected to different input terminals of the XOR circuit 100. A random number sequence is outputted from an output terminal of the XOR circuit 100).
Huang fails to teach [determining a sampling point associated with a target sampling signal] in which a first logic level transition occurs, [from among the plurality of sampling signals]
However, Vasyltsov teaches [determining a sampling point associated with a target sampling signal] in which a first logic level transition occurs, [from among the plurality of sampling signals]
(Vasyltsov Page 13 Paragraph 2: We measured the time of the first transition of the signal starting from 30 ns to 40 ns after switching to generation mode).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Huang with the first transition as taught by Vasyltsov. One of ordinary skill in the art would be motivated to make this combination because the main advantage of the proposed method is the significant decrease in the latency of TRNG due to earlier sampling times as taught by Vasyltsov (Vasyltsov Page 6 paragraph 3).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Lee et al. (US 20160147505 A1) hereinafter Lee.
With regards to claim 12, Huang teaches A random number generator comprising: a first delay element chain comprising a plurality of first delay elements connected to each other in series to generate an oscillation signal; (Huang [0007]: The true random number generator according to the embodiment of the present disclosure includes; Huang [0022]: A D terminal of a D flip-flop receives a high-frequency oscillation signal generated by a high-frequency oscillator; Huang [0017]: FIG. 3 is a schematic structural diagram of a high-frequency oscillation loop; Huang Fig. 3: shows the oscillation circuit as a plurality of delay elements in series)
a second inverter chain comprising a plurality of second inverters connected to each other in series to generate a plurality of delay signals delayed by different delay times [from a clock signal;] (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop; Huang Fig. 2: Shows a plurality of delay elements connected in series generating a plurality of sampling signals using the flip-flops)
a sampling chain configured to generate a plurality of sampling signals of the oscillation signal based on the plurality of delay signals; (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop; Huang Fig. 2: Shows a plurality of delay elements connected in series generating a plurality of sampling signals using the flip-flops)
and a random number output circuit configured to: determine a sampling signal having a logic level that is different from a logic level of a previous sampling signal, from among the plurality of sampling signals, as a target sampling signal, (Huang [00034]: a random number sequence is obtained after the XOR unit 201 and the XOR circuit 100 perform the XOR processing on the sampling results)
and generate a random number based on a sampling order of the target sampling signal from among the plurality of sampling signals (Huang [00033]: Output terminals of the multiple random entropy source circuits 200 are respectively connected to different input terminals of the XOR circuit 100. A random number sequence is outputted from an output terminal of the XOR circuit 100; Huang [00034]: a random number sequence is obtained after the XOR unit 201 and the XOR circuit 100 perform the XOR processing on the sampling results).
Huang fails to teach [a second inverter chain comprising a plurality of second inverters connected to each other in series to generate a plurality of delay signals delayed by different delay times] from a clock signal.
However, Lee teaches [a second inverter chain comprising a plurality of second inverters connected to each other in series to generate a plurality of delay signals delayed by different delay times] from a clock signal; (Lee [0018]: The delay circuit 130 receives an alternating current signal SAC (e.g. a square wave) and the second control signals SC2 to generate a random delay sampling signal SRD).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Huang with the clock signal as taught by Lee. One of ordinary skill in the art would be motivated to make this combination because a delay time for the delay circuit delaying the alternating current signal is controlled based on the second control signals. In this way, the randomness of the random sequence may be improved. Namely, randomness of random codes may be improved as taught by Lee (Lee [0009]).
Claims 2-6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Vasyltsov further in view of Lee.
With regards to claim 2, Huang in view of Vasyltsov teaches all of the limitations of claim 1 above. Huang further teaches wherein the sampling circuit comprises a delay element chain [configured to receive a clock signal,] (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop; Huang Fig. 2: Shows a plurality of delay elements connected in series generating a plurality of sampling signals using the flip-flops)
and generate a plurality of delay signals that are delayed by different delay times [with respect to the clock signal] (Huang [0036]: Further, in each of the random entropy source circuits 200, the input terminal of each of the flip-flops 202 is connected to the output terminal of the inverter Inv corresponding to the flip-flop 202, the clock input terminal of each of the flip-flops 202 receives the sampling clock signal fs outputted by the low-frequency sampling oscillation loop Sample OSC, and output terminals of the flip-flops 202 are respectively connected to different input terminals of the XOR unit 201. One entropy source sampling process is performed at the output terminal of each of the inverters in the random entropy source circuit 200; (therefore the delay signals are delayed by different delay times)).
Huang fails to teach [wherein the sampling circuit comprises a delay element chain] configured to receive a clock signal, [and generate a plurality of delay signals that are delayed by different delay times] with respect to the clock signal.
However, Lee teaches [wherein the sampling circuit comprises a delay element chain] configured to receive a clock signal, (Lee [0018]: The delay circuit 130 receives an alternating current signal SAC (e.g. a square wave) and the second control signals SC2 to generate a random delay sampling signal SRD)
[and generate a plurality of delay signals that are delayed by different delay times] with respect to the clock signal (Lee [0018]: The delay circuit 130 receives an alternating current signal SAC (e.g. a square wave) and the second control signals SC2 to generate a random delay sampling signal SRD).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Huang in view of Vasyltsov with the clock signal as taught by Lee. One of ordinary skill in the art would be motivated to make this combination because a delay time for the delay circuit delaying the alternating current signal is controlled based on the second control signals. In this way, the randomness of the random sequence may be improved. Namely, randomness of random codes may be improved as taught by Lee (Lee [0009]).
With regards to claim 3, Huang in view of Vasyltsov further in view of Lee teaches all of the limitations of claim 2 above. Huang further teaches wherein an interval between two sampling points of the plurality of sampling points is less than a period of the oscillation signal (Huang [0024]: In view of this, a true random number generator is provided according to an embodiment of the present disclosure. By performing multiple sampling processes on a loop oscillator generating a high-frequency oscillation signal, a high-frequency oscillation loop having a single output signal is changed to a high-frequency oscillation loop having multiple output signals, and a phase deviation between the multiple output signals of the high-frequency oscillation loop is smaller than a phase deviation of the overall output of the loop oscillator having the single output signal. In this way, the required period of the low-frequency clock signal can be reduced, and the sampling frequency and the true random number generation rate can be increased, such that the random number generation rate of the true random number generator can meet the requirements of the high-frequency system).
With regards to claim 4, Huang in view of Vasyltsov further in view of Lee teaches all of the limitations of claim 2 above. Huang further teaches wherein the sampling circuit comprises a flip-flop circuit comprising a plurality of flip-flops connected to each other in parallel, (Huang [0036]: Further, in each of the random entropy source circuits 200, the input terminal of each of the flip-flops 202 is connected to the output terminal of the inverter Inv corresponding to the flip-flop 202, the clock input terminal of each of the flip-flops 202 receives the sampling clock signal fs outputted by the low-frequency sampling oscillation loop Sample OSC, and output terminals of the flip-flops 202 are respectively connected to different input terminals of the XOR unit 201. One entropy source sampling process is performed at the output terminal of each of the inverters in the random entropy source circuit 200)
each flip-flop of the plurality of flip-flops being configured to: receive the oscillation signal and one of the plurality of delay signals, and generate a sampling signal of the oscillation signal at [a clock edge time point of the one of the plurality of delay signals] (Huang [0036]: Further, in each of the random entropy source circuits 200, the input terminal of each of the flip-flops 202 is connected to the output terminal of the inverter Inv corresponding to the flip-flop 202, the clock input terminal of each of the flip-flops 202 receives the sampling clock signal fs outputted by the low-frequency sampling oscillation loop Sample OSC, and output terminals of the flip-flops 202 are respectively connected to different input terminals of the XOR unit 201. One entropy source sampling process is performed at the output terminal of each of the inverters in the random entropy source circuit 200).
Huang fails to teach [each flip-flop of the plurality of flip-flops being configured to: receive the oscillation signal and one of the plurality of delay signals, and generate a sampling signal of the oscillation signal at] a clock edge time point of the one of the plurality of delay signals.
However, Lee teaches [each flip-flop of the plurality of flip-flops being configured to: receive the oscillation signal and one of the plurality of delay signals, and generate a sampling signal of the oscillation signal at] a clock edge time point of the one of the plurality of delay signals (Lee [0019]: An input end D of the D flip-flop DFF of the logic operation circuit 140 receives the random clock signal SRCK, and a trigger end of the D flip-flop DFF receives the random delay sampling signal SRD. The D flip-flop DFF captures a logic level of the random clock signal SRCK according to the random delay sampling signal SRD).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Huang in view of Vasyltsov further in view of Lee with the clock edge as taught by Lee. One of ordinary skill in the art would be motivated to make this combination because a delay time for the delay circuit delaying the alternating current signal is controlled based on the second control signals. In this way, the randomness of the random sequence may be improved. Namely, randomness of random codes may be improved as taught by Lee (Lee [0009]).
With regards to claim 5, Huang in view of Vasyltsov further in view of Lee teaches all of the limitations of claim 4 above. Huang further teaches wherein the delay element chain comprises a plurality of inverters connected in series to each other, (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop; Huang Fig. 2: Shows a plurality of inverters connected in series)
the delay element chain being configured to: generate the plurality of delay signals [as the clock signal] propagates through the plurality of inverters, (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop; Huang Fig. 2: Shows a plurality of delay elements connected in series generating a plurality of sampling signals using the flip-flops)
and provide a corresponding delay signal of the plurality of delay signals to a corresponding flip-flop of the plurality of flip-flops (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop).
Huang fails to teach [the delay element chain being configured to: generate the plurality of delay signals] as the clock signal [propagates through the plurality of inverters].
However, Lee teaches [the delay element chain being configured to: generate the plurality of delay signals] as the clock signal [propagates through the plurality of inverters] (Lee [0018]: The delay circuit 130 receives an alternating current signal SAC (e.g. a square wave) and the second control signals SC2 to generate a random delay sampling signal SRD).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Huang in view of Vasyltsov further in view of Lee with the clock signal as taught by Lee. One of ordinary skill in the art would be motivated to make this combination because a delay time for the delay circuit delaying the alternating current signal is controlled based on the second control signals. In this way, the randomness of the random sequence may be improved. Namely, randomness of random codes may be improved as taught by Lee (Lee [0009]).
With regards to claim 6, Huang in view of Vasyltsov further in view of Lee teaches all of the limitations of claim 5 above. Huang further teaches wherein the flip- flop circuit comprises: a first flip-flop circuit configured to generate the sampling signal by receiving a first delay signal having a phase [corresponding to the clock signal;] (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop; Huang Fig. 4: Shows a flip-flop receiving a signal with a normal phase and a second flip-flop receiving a signal with an inverted phase)
and a second flip-flop circuit configured to generate the sampling signal by receiving a second delay signal having an inverted phase [with respect to the clock signal] (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop; Huang Fig. 4: Shows a flip-flop receiving a signal with a normal phase and a second flip-flop receiving a signal with an inverted phase).
Huang fails to teach [wherein the flip- flop circuit comprises: a first flip-flop circuit configured to generate the sampling signal by receiving a first delay signal having a phase] corresponding to the clock signal; [and a second flip-flop circuit configured to generate the sampling signal by receiving a second delay signal having an inverted phase] with respect to the clock signal.
However, Lee teaches [wherein the flip- flop circuit comprises: a first flip-flop circuit configured to generate the sampling signal by receiving a first delay signal having a phase] corresponding to the clock signal; (Lee [0018]: The delay circuit 130 receives an alternating current signal SAC (e.g. a square wave) and the second control signals SC2 to generate a random delay sampling signal SRD)
[and a second flip-flop circuit configured to generate the sampling signal by receiving a second delay signal having an inverted phase] with respect to the clock signal (Lee [0018]: The delay circuit 130 receives an alternating current signal SAC (e.g. a square wave) and the second control signals SC2 to generate a random delay sampling signal SRD).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Huang in view of Vasyltsov further in view of Lee with the clock signal as taught by Lee. One of ordinary skill in the art would be motivated to make this combination because a delay time for the delay circuit delaying the alternating current signal is controlled based on the second control signals. In this way, the randomness of the random sequence may be improved. Namely, randomness of random codes may be improved as taught by Lee (Lee [0009]).
With regards to claim 14, Huang in view of Lee teaches all of the limitations of claim 12 above. Huang further teaches wherein the random number output circuit is configured to determine the sampling signal as the target sampling signal in which [a first-in-time logic level transition occurs] from among the plurality of sampling signals, (Huang [0009]: the number of the flip-flops in each of the multiple of random entropy source circuits is N. In each of the multiple of random entropy source circuits, the flip-flops correspond to the inverters one to one; and an input terminal of each of the flip-flops is connected to an output terminal of the inverter corresponding to the flip-flop; (This would cause the first transition-in-time to be the target sample)
and the plurality of sampling signals correspond to a plurality of sampling points (Huang [0036]: Further, in each of the random entropy source circuits 200, the input terminal of each of the flip-flops 202 is connected to the output terminal of the inverter Inv corresponding to the flip-flop 202, the clock input terminal of each of the flip-flops 202 receives the sampling clock signal fs outputted by the low-frequency sampling oscillation loop Sample OSC, and output terminals of the flip-flops 202 are respectively connected to different input terminals of the XOR unit 201. One entropy source sampling process is performed at the output terminal of each of the inverters in the random entropy source circuit 200; (therefore the oscillation signal is sampled at multiple points in time)).
Huang fails to teach [wherein the random number output circuit is configured to determine the sampling signal as the target sampling signal in which] a first-in-time logic level transition occurs [from among the plurality of sampling signals,].
However, Vasyltsov teaches [wherein the random number output circuit is configured to determine the sampling signal as the target sampling signal in which] a first-in-time logic level transition occurs [from among the plurality of sampling signals,] (Vasyltsov Page 13 Paragraph 2: We measured the time of the first transition of the signal starting from 30 ns to 40 ns after switching to generation mode).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Huang in view of Lee with the first transition as taught by Vasyltsov. One of ordinary skill in the art would be motivated to make this combination because the main advantage of the proposed method is the significant decrease in the latency of TRNG due to earlier sampling times as taught by Vasyltsov (Vasyltsov Page 6 paragraph 3).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Vasyltsov further in view of Lee further in view of Cao et al. (Machine Translation of WO 2022027325 A1) hereinafter Cao.
With regards to claim 7, Huang in view of Vasyltsov further in view of Lee teaches all of the limitations of claim 4 above. Huang further teaches wherein the delay element chain comprises a plurality of inverters arranged as a plurality of inverter groups, (Huang [0007]: Each of the multiple random entropy source circuits includes: a low-frequency sampling oscillation loop, an XOR unit, N inverters, and at least two flip-flops, where N is an odd number greater than 1; Huang Fig. 2: shows the delay element chain with 2 inverter groups)
the delay element chain being configured to: generate the plurality of delay signals having the same phase from each inverter group of the plurality of inverter groups, (Huang [0007]: The N inverters are connected end to end to form a high-frequency oscillation loop. In each of the multiple random entropy source circuits, an input terminal of each of the at least two flip-flops is connected to an output terminal of one of the N inverters corresponding to the flip-flop; Huang Fig. 2: shows that when N = 3, the phase of the outputs of the inverters would be the same)
and provide a corresponding delay signal of the plurality of delay signals to a corresponding flip-flop of the plurality of flip-flops (Huang [0007]: The N inverters are connected end to end to form a high-frequency oscillation loop. In each of the multiple random entropy source circuits, an input terminal of each of the at least two flip-flops is connected to an output terminal of one of the N inverters corresponding to the flip-flop).
Huang fails to teach each inverter group including two inverters from among the plurality of inverters.
However, Cao teaches each inverter group including two inverters from among the plurality of inverters (Cao page 9 paragraph 7: An implementation of a ring oscillator, the ring oscillator also includes m ordinary inverters (that is, in FIG. 8 and FIG. 7, the ordinary inverters that are cascaded with the above-mentioned inverter group; Cao Fig. 9: shows the clock path with two inverters per flip-flop).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Huang in view of Vasyltsov further in view of Lee with the two inverters per a group as taught by Cao. One of ordinary skill in the art would be motivated to make this combination because it would allow for the phase of the delay signals to always be the same. Also, the circuit has the best performance in terms of power consumption, area, and efficiency of generating random numbers as taught by Cao (Cao page 6 paragraph 2).
Allowable Subject Matter
Claims 8-10, 15-19, and 25-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With regards to claims 8, 15, and 25, while prior art teaches of generating multiple random numbers, prior art fails to teach the specifics of generating one random number when the order of the target sampling signal is even and another random number when the order of the target sampling signal is odd.
With regards to claims 10, 19, and 26, while prior art teaches of a random number being a code, it fails to teach of a random number being a code mapped in response to an order of the target sampling signal.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151