DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 and 5-23 are pending in this application. Claims 1, 5-7, 10, 12-14 and 16-17 are currently amended; claims 8-9, 11, 15, and 18-20 are original; claims 21-23 are new; claims 2-4 are canceled.
Remarks
Claim 23 recites “wherein the ring counter includes a plurality of flip-flops coupled in a ring configuration, each flip-flop having an output coupled to a clock input terminal of a respective register and to an input of a next flip-flop in the ring configuration”. Perhaps Applicant may want to amend the claims to recite “wherein
Claim Objections
Claims 1 and 5-16 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 1 line 11, “a convolution coefficients” should read “convolution coefficients” instead for better clarity. Claim 10 recites a similar limitation in line 11 and is objected to for the same reason. Claims 5-9 inherit the same deficiency as claim 1 by reason of dependence. Claims 11-16 inherit the same deficiency as claim 10 by reason of dependence.
B. In claim 6 line 3, “the convolution operator” should read “the respective convolution operator” instead for better clarity and consistency of claim terminologies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7-23 are rejected under 35 U.S.C. 103 as being unpatentable over Shinde (US 6181733 B1), in view of Bal et al. (US 20130110898 A1), hereinafter Bal.
Regarding claim 1, Shinde teaches
a filter input (Shinde Fig. 4 and col 9 lines 19-22 “A digital signal … is inputted to the signal input terminal 201”; filter input - signal input terminal 201);
a plurality of registers each having (Shinde Fig. 4 and col 9 lines 26-28 “Data input terminals D of the first to eighth flip-flop sets 211-218 constituting the storage section 210 are applied with the digital signal”; plurality of registers – 211-218):
a data input terminal coupled to the filter input (Shinde Fig. 4 data input terminal - Data input terminal D);
a data output terminal (Shinde Fig. 4 data output terminal - Data output terminal Q); and
a clock input terminal (Shinde Fig. 4 clock input terminal - clock input terminal C); and
a ring counter coupled to the clock input terminals of the registers (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively”; ring counter - write selection circuit 220);
a plurality of convolution operators each coupled to the data output terminal of a respective register (Shinde Fig. 4 and col 10 lines 13-17 “In the first to eighth multipliers 241-248, multiplication operations of output signals (6 bits) of the first to eighth flip-flop sets 211-218 by the despreading codes (1 bit) outputted from the first to eighth despreading code flip-flops 231-238 are carried out, respectively”; plurality of convolution operators - first to eighth multipliers 241-248).
Shinde does not explicitly teach a first plurality of multiplexers each coupled to a respective convolution operator, wherein each first multiplexer receives a same set of a convolution coefficients in a different respective order and outputs one of the convolution coefficients to the respective convolution operator.
However, on the same field of endeavor, Bal discloses a FIR filter comprising a first plurality of multiplexers each coupled to a respective convolution operator wherein each multiplexer is connected to a respective memory bank storing a plurality of filter coefficients and selects one of the plurality of filter coefficients to provide to the respective convolution operator (Bal Fig. 2(a) and paragraph [0032-0033] “each of the memory banks 204 stores a plurality of filter coefficients and is required to select one of the plurality of filter coefficients for its operation with respect to every input sample … The input count 216-1 provided by the first counter 202-1 is provided to coefficient multiplexers 218-1, 218-2 ... 218-M, collectively known as coefficient multiplexers 218, coupled with a respective memory bank of the memory banks 204-1, 204-2 ... 204-M. In one embodiment, the input count 216-1 is provided through a control unit 220. The coefficient multiplexer 218 is configured to select one of the filter coefficients stored in each of the memory banks 204, based on the output of the control unit 220, for multiplying the selected filter coefficient with an input sample” paragraph [0038] “The MAC units 206 compute the product of the selected filter coefficient with the received input sample”; first plurality of multiplexers - coefficient multiplexers 218; respective convolution operator - MAC units 206 or multipliers 208).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shinde using Bal and configure the filter to include a plurality of memory banks storing the plurality of filer coefficients C0-C7 and a first plurality of multiplexers each coupled to receive and select one filter coefficient from a respective memory bank and output the selected one filter coefficient to a respective convolution operator (i.e., multiplier) in order to select and provide the proper coefficient to each of the multipliers (Bal paragraph [0030]), for example, by replacing or implementing the block 230 of Shinde using a plurality of multiplexers. Further, as shown in Fig. 5 and discussed in col 10 lines 27 to col 13 line 7 of Shinde, each multiplier is provided a different filter coefficient in each operation state. Therefore, it would be obvious to configure each memory bank to store the filter coefficients in an order on which each filter coefficient is provided to each multiplier. That is, configure the first memory bank 204-1 to store the filter coefficient in the order C0, C7, C6, C5, C4, C3, C2, C1 similar to the arrangement of the register 230 in the first operation state. Configure the second memory bank 204-2 to store the filter coefficient in the order C1, C0, C7, C6, C5, C4, C3, C2 similar to the arrangement of the register 230 in the second operation state and so on until an eight memory bank 204-8 which stores the filter coefficient in the order C7, C6, C5, C4, C3, C2, C1, C0 similar to the arrangement of the register 230 in the eight operation state in order to use a single selection signal to the plurality of coefficient multiplexers consistent with Fig. 2a and paragraphs [0032-0033] of Bal which discloses using the same selection signal to plurality of coefficient multiplexers.
Therefore, the combination of Shinde as modified in view of Bal teaches a first plurality of multiplexers each coupled to a respective convolution operator, wherein each first multiplexer receives a same set of a convolution coefficients in a different respective order and outputs one of the convolution coefficients to the respective convolution operator.
Regarding claim 7, Shinde as modified in view of Bal teaches all the limitations of claim 1 as stated above. Further, Shinde as modified in view of Bal teaches further comprising a summer coupled to the convolution operators (Shinde Fig. 4; summer – adders 251-257).
Regarding claim 8, Shinde as modified in view of Bal teaches all the limitations of claim 7 as stated above. Further, Shinde as modified in view of Bal teaches wherein the summer is configured to sum output signals of the convolution operators (Shinde Fig. 4 and col 13 lines 8-35).
Regarding claim 9, Shinde as modified in view of Bal teaches all the limitations of claim 1 as stated above. Further, Shinde as modified in view of Bal teaches wherein the ring counter includes a plurality of flip- flops coupled in a ring configuration, each flip-flop having an output coupled to a clock input terminal of a respective register and to an input of a next flip-flop in the ring configuration (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively”; plurality of flip-flops - eighth write selecting flip-flops 221-228).
Regarding claim 10, Shinde teaches
n registers each including (Shinde Fig. 4 and col 9 lines 26-28 “Data input terminals D of the first to eighth flip-flop sets 211-218 constituting the storage section 210 are applied with the digital signal”; n registers – 211-218):
a data input terminal (Shinde Fig. 4 data input terminal - Data input terminal D);
a data output terminal (Shinde Fig. 4 data output terminal - Data output terminal Q); and
a clock input terminal (Shinde Fig. 4 clock input terminal - clock input terminal C); and
a ring counter including n flip-flops coupled in a ring configuration and each coupled to a clock input of a respective register (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively”; ring counter - write selection circuit 220; n flip-flops - eighth write selecting flip-flops 221-228);
a plurality of convolution operators each coupled to the data output terminal of a respective register (Shinde Fig. 4 and col 10 lines 13-17 “In the first to eighth multipliers 241-248, multiplication operations of output signals (6 bits) of the first to eighth flip-flop sets 211-218 by the despreading codes (1 bit) outputted from the first to eighth despreading code flip-flops 231-238 are carried out, respectively”; plurality of convolution operators - first to eighth multipliers 241-248).
Shinde does not explicitly teach a first plurality of multiplexers each coupled to a respective convolution operator, wherein the each first multiplexer receives a same set of a convolution coefficients in a different respective order and outputs one of the convolution coefficients to the respective convolution operator.
However, on the same field of endeavor, Bal discloses a FIR filter comprising a first plurality of multiplexers each coupled to a respective convolution operator wherein each multiplexer is connected to a respective memory bank storing a plurality of filter coefficients and selects one of the plurality of filter coefficients to provide to the respective convolution operator (Bal Fig. 2(a) and paragraph [0032-0033] “each of the memory banks 204 stores a plurality of filter coefficients and is required to select one of the plurality of filter coefficients for its operation with respect to every input sample … The input count 216-1 provided by the first counter 202-1 is provided to coefficient multiplexers 218-1, 218-2 ... 218-M, collectively known as coefficient multiplexers 218, coupled with a respective memory bank of the memory banks 204-1, 204-2 ... 204-M. In one embodiment, the input count 216-1 is provided through a control unit 220. The coefficient multiplexer 218 is configured to select one of the filter coefficients stored in each of the memory banks 204, based on the output of the control unit 220, for multiplying the selected filter coefficient with an input sample” paragraph [0038] “The MAC units 206 compute the product of the selected filter coefficient with the received input sample”; first plurality of multiplexers - coefficient multiplexers 218; respective convolution operator - MAC units 206 or multipliers 208).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shinde using Bal and configure the filter to include a plurality of memory banks storing the plurality of filer coefficients C0-C7 and a first plurality of multiplexers each coupled to receive and select one filter coefficient from a respective memory bank and output the selected one filter coefficient to a respective convolution operator (i.e., multiplier) in order to select and provide the proper coefficient to each of the multipliers (Bal paragraph [0030]), for example, by replacing or implementing the block 230 of Shinde using a plurality of multiplexers. Further, as shown in Fig. 5 and discussed in col 10 lines 27 to col 13 line 7 of Shinde, each multiplier is provided a different filter coefficient in each operation state. Therefore, it would be obvious to configure each memory bank to store the filter coefficients in an order on which each filter coefficient is provided to each multiplier. That is, configure the first memory bank 204-1 to store the filter coefficient in the order C0, C7, C6, C5, C4, C3, C2, C1 similar to the arrangement of the register 230 in the first operation state. Configure the second memory bank 204-2 to store the filter coefficient in the order C1, C0, C7, C6, C5, C4, C3, C2 similar to the arrangement of the register 230 in the second operation state and so on until an eight memory bank 204-8 which stores the filter coefficient in the order C7, C6, C5, C4, C3, C2, C1, C0 similar to the arrangement of the register 230 in the eight operation state in order to use a single selection signal to the plurality of coefficient multiplexers consistent with Fig. 2a and paragraphs [0032-0033] of Bal which discloses using the same selection signal to plurality of coefficient multiplexers.
Therefore, the combination of Shinde as modified in view of Bal teaches a first plurality of multiplexers each coupled to a respective convolution operator, wherein the each first multiplexer receives a same set of a convolution coefficients in a different respective order and outputs one of the convolution coefficients to the respective convolution operator.
Regarding claim 11, Shinde as modified in view of Bal teaches all the limitations of claim 10 as stated above. Further, Shinde as modified in view of Bal teaches further comprising a filter input coupled to the data input terminal of each register (Shinde Fig. 4 and col 9 lines 19-28 “A digital signal … is inputted to the signal input terminal 201 … Data input terminals D of the first to eighth flip-flop sets 211-218 constituting the storage section 210 are applied with the digital signal”; filter input - signal input terminal 201).
Regarding claim 12, Shinde as modified in view of Bal teaches all the limitations of claim 11 as stated above. Further, Shinde as modified in view of Bal teaches wherein the filter input is configured to pass input data values to the data input terminal of each register in accordance with a filter clock signal having a first frequency (Shinde Fig. 4 and col 9 lines 19-25 “A digital signal Io generated by sampling an analog signal (for example, a spectrum spread signal) at a sampling frequency of 4.096 MHz is inputted to the signal input terminal 201. The digital signal Io is a 6-bit digital signal in terms of two's complement which is synchronous with a clock CLK of 4.096 MHz inputted to the clock input terminal 202”; input data values - digital signal Io; filter clock – clock CLK; first frequency - 4.096 MHz).
Regarding claim 13, Shinde as modified in view of Bal teaches all the limitations of claim 12 as stated above. Further, Shinde as modified in view of Bal teaches wherein each flip-flop outputs a respective register clock signal with a second frequency to the clock input terminal of the respective register (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively”; second frequency – 1/8 of the clock CLK frequency).
Regarding claim 14, Shinde as modified in view of Bal teaches all the limitations of claim 13 as stated above. Further, Shinde as modified in view of Bal teaches wherein the second frequency is equal to the first frequency divided by n (Shinde Fig. 4 and col 9 lines 28-55 the second frequency is 1/8 of the first frequency where n=8).
Regarding claim 15, Shinde as modified in view of Bal teaches all the limitations of claim 14 as stated above. Further, Shinde as modified in view of Bal teaches wherein each of the register clock signals are out of phase with each other (Shinde Fig. 4 and col 9 lines 28-55 “In the initial state, desired one of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220 is written with "1" (high level in logical value), and the other write selecting flip-flops are written with "0", (low level in logical value)”; only 1 register clock is high at a time).
Regarding claim 16, Shinde as modified in view of Bal teaches all the limitations of claim 14 as stated above. Further, Shinde as modified in view of Bal teaches wherein only one of the register clock signals is high at each cycle of the filter clock signal (Shinde Fig. 4 and col 9 lines 28-55 “In the initial state, desired one of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220 is written with "1" (high level in logical value), and the other write selecting flip-flops are written with "0", (low level in logical value)”).
Regarding claim 17, Shinde teaches
passing data values from a filter input of a finite impulse response (FIR) filter to data input terminals of each of a plurality of registers (Shinde Fig. 4 and col 9 lines 5-28 “A digital matched filter according to a first embodiment of the present invention is an eight-times spread 8-order digital matched filter constructed by using an FIR digital filter … A digital signal … is inputted to the signal input terminal 201 … Data input terminals D of the first to eighth flip-flop sets 211-218 constituting the storage section 210 are applied with the digital signal”; filter input - signal input terminal 201; plurality of registers – 211-218); data input terminals - Data input terminals D; FIR filter - 8-order digital matched filter constructed by using an FIR digital filter);
passing a pulse through a ring counter coupled to the registers and including a plurality of flip-flops coupled in a ring configuration (Shinde Fig. 4 and col 9 lines 28-55 ring counter - write selection circuit 220; plurality of flip-flops coupled in a ring configuration - eighth write selecting flip-flops 221-228; pulse – the “1” (high level in logical value) that is subsequently shifted to the flip-flops 221-228);
controlling clock input terminals of the registers with the ring counter based on the pulse (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively … so that the digital signal Io is sequentially fetched and held in the first to eighth flip-flop sets 211-218 in synchronism with the clock CLK”); and
(Shinde Fig. 4 and col 10 lines 13-17 “In the first to eighth multipliers 241-248, multiplication operations of output signals (6 bits) of the first to eighth flip-flop sets 211-218 by the despreading codes (1 bit) outputted from the first to eighth despreading code flip-flops 231-238 are carried out, respectively”; plurality of convolution operators - first to eighth multipliers 241-248).
Shinde does no explicitly teach receiving, with each of a plurality of multiplexers each coupled to a respective convolution operator, a same set of convolution coefficients in a different respective order; and outputting, with each of the multiplexers, one of the convolution coefficients to the respective convolution operator.
However, on the same field of endeavor, Bal discloses a FIR filter comprising a first plurality of multiplexers each coupled to a respective convolution operator wherein each multiplexer is connected to a respective memory bank storing a plurality of filter coefficients and selects one of the plurality of filter coefficients to provide to the respective convolution operator (Bal Fig. 2(a) and paragraph [0032-0033] “each of the memory banks 204 stores a plurality of filter coefficients and is required to select one of the plurality of filter coefficients for its operation with respect to every input sample … The input count 216-1 provided by the first counter 202-1 is provided to coefficient multiplexers 218-1, 218-2 ... 218-M, collectively known as coefficient multiplexers 218, coupled with a respective memory bank of the memory banks 204-1, 204-2 ... 204-M. In one embodiment, the input count 216-1 is provided through a control unit 220. The coefficient multiplexer 218 is configured to select one of the filter coefficients stored in each of the memory banks 204, based on the output of the control unit 220, for multiplying the selected filter coefficient with an input sample” paragraph [0038] “The MAC units 206 compute the product of the selected filter coefficient with the received input sample”; first plurality of multiplexers - coefficient multiplexers 218; respective convolution operator - MAC units 206 or multipliers 208).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shinde using Bal and configure the filter to include a plurality of memory banks storing the plurality of filer coefficients C0-C7 and a first plurality of multiplexers each coupled to receive and select one filter coefficient from a respective memory bank and output the selected one filter coefficient to a respective convolution operator (i.e., multiplier) in order to select and provide the proper coefficient to each of the multipliers (Bal paragraph [0030]), for example, by replacing or implementing the block 230 of Shinde using a plurality of multiplexers. Further, as shown in Fig. 5 and discussed in col 10 lines 27 to col 13 line 7 of Shinde, each multiplier is provided a different filter coefficient in each operation state. Therefore, it would be obvious to configure each memory bank to store the filter coefficients in an order on which each filter coefficient is provided to each multiplier. That is, configure the first memory bank 204-1 to store the filter coefficient in the order C0, C7, C6, C5, C4, C3, C2, C1 similar to the arrangement of the register 230 in the first operation state. Configure the second memory bank 204-2 to store the filter coefficient in the order C1, C0, C7, C6, C5, C4, C3, C2 similar to the arrangement of the register 230 in the second operation state and so on until an eight memory bank 204-8 which stores the filter coefficient in the order C7, C6, C5, C4, C3, C2, C1, C0 similar to the arrangement of the register 230 in the eight operation state in order to use a single selection signal to the plurality of coefficient multiplexers consistent with Fig. 2a and paragraphs [0032-0033] of Bal which discloses using the same selection signal to plurality of coefficient multiplexers.
Therefore, the combination of Shinde as modified in view of Bal teaches receiving, with each of a plurality of multiplexers each coupled to a respective convolution operator, a same set of convolution coefficients in a different respective order; and outputting, with each of the multiplexers, one of the convolution coefficients to the respective convolution operator.
Regarding claim 18, Shinde as modified in view of Bal teaches all the limitations of claim 17 as stated above. Further, Shinde as modified in view of Bal teaches further comprising providing a respective data value from the filter input on each clock cycle of a filter clock signal (Shinde Fig. 4 and col 9 lines 19-25 “A digital signal Io generated by sampling an analog signal (for example, a spectrum spread signal) at a sampling frequency of 4.096 MHz is inputted to the signal input terminal 201. The digital signal Io is a 6-bit digital signal in terms of two's complement which is synchronous with a clock CLK of 4.096 MHz inputted to the clock input terminal 202”; filter clock signal – clock CLK).
Regarding claim 19, Shinde as modified in view of Bal teaches all the limitations of claim 18 as stated above. Further, Shinde as modified in view of Bal teaches further comprising processing each data value with only one of the registers (Shinde Fig. 4 and col 9 lines 28-55 “the "1" is sequentially applied to the clock input terminals C of the first to eighth flip-flop sets 211-218 constituting the storage section 210 in synchronism with the clock CLK, so that the digital signal Io is sequentially fetched and held in the first to eighth flip-flop sets 211-218 in synchronism with the clock CLK”; only one register receives a “1” applied to its clock input terminal C).
Regarding claim 20, Shinde as modified in view of Bal teaches all the limitations of claim 19 as stated above. Further, Shinde as modified in view of Bal teaches further comprising processing each data value with only one of the registers based on the pulse (Shinde Fig. 4 and col 9 lines 28-55 “the "1" is sequentially applied to the clock input terminals C of the first to eighth flip-flop sets 211-218 constituting the storage section 210 in synchronism with the clock CLK, so that the digital signal Io is sequentially fetched and held in the first to eighth flip-flop sets 211-218 in synchronism with the clock CLK”; only one register receives a “1” applied to its clock input terminal C).
Regarding claim 21, Shinde as modified in view of Bal teaches all the limitations of claim 17 as stated above. Further, Shinde as modified in view of Bal teaches where a summer is coupled to the convolution operators (Shinde Fig. 4; summer – adders 251-257).
Regarding claim 22, Shinde as modified in view of Bal teaches all the limitations of claim 21 as stated above. Further, Shinde as modified in view of Bal teaches further comprising summing output signal of the convolution operators with the summer (Shinde Fig. 4 and col 13 lines 8-35).
Regarding claim 23, Shinde as modified in view of Bal teaches all the limitations of claim 21 as stated above. Further, Shinde as modified in view of Bal teaches wherein the ring counter includes a plurality of flip-flops coupled in a ring configuration, each flip-flop having an output coupled to a clock input terminal of a respective register and to an input of a next flip-flop in the ring configuration (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively”; plurality of flip-flops - eighth write selecting flip-flops 221-228).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Shinde in view of Bal as applied to claim 1 above, and further in view of Gunwani et al. (US 8612503 B2), hereinafter Gunwani.
Regarding claim 5, Shinde as modified in view of Bal teaches all the limitations of claim 1 as stated above.
Shinde does not explicitly teach further comprising a second plurality of multiplexers each coupled a respective convolution operator.
However, on the same field of endeavor, Gunwani discloses a second multiplexer coupled to a convolution operator (Gunwani Figs. 3 and 5 second multiplexer – data selection mux 530).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shinde and generalize the teaching of Gunwani by configuring the filter to include a second plurality of multiplexers each coupled a respective convolution operator by duplicating the arrangement similar to Fig. 5 of Gunwani as many times as the number of multipliers (i.e., 8 times one for each multipliers 241-248) for selecting which data from registers 211-218 is to be provided to each respective multiplier to allow for a more efficient and flexible mapping of filter algorithms to an array of multipliers/convolution operators of the filter (Gunwani col 9 lines 5-35]).
Therefore, the combination of Shinde as modified in view of Bal and Gunwani teaches further comprising a second plurality of multiplexers each coupled a respective convolution operator.
Regarding claim 6, Shinde as modified in view of Bal and Gunwani teaches all the limitations of claim 5 as stated above. Further, Shinde as modified in view of Bal and Gunwani teaches wherein each second multiplexer receives output signals from the plurality of the registers and outputs one of the output signals to the convolution operator (Gunwani Fig. 5 and col 8 line 62 to col 9 line 20 “A shift register 520 includes serially connected shift registers wherein each register may provide an input to a data selection multiplexer 530 … Selection of which input to present on the output of the multiplexer 530 is controlled by a configurable counter 540”).
Response to Arguments
In view of amendments made and Applicant’s arguments, the 35 U.S.C. 112(b) rejection of claims 12-16 has been withdrawn.
Applicant’s arguments, see remarks page 6-7, filed 03/09/2026, with respect to the rejection(s) of claims 1-2 and 7-20 under 35 U.S.C. 102(a)(1) and (a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of amendments made and previously cited prior art references.
Applicant amended independent claim 1 to include the limitations of “a plurality of convolution operators each coupled to the data output terminal of a respective register; and a first plurality of multiplexers each coupled to a respective convolution operator, wherein each first multiplexer receives a same set of a convolution coefficients in a different respective order and outputs one of the convolution coefficients to the respective convolution operator” and argues that none of the prior art references cited, taken alone or in combination, teach or suggest these features.
Response: Examiner agrees in part. Examiner agrees that Shinde does not explicitly teach “a first plurality of multiplexers each coupled to a respective convolution operator, wherein each first multiplexer receives a same set of a convolution coefficients in a different respective order and outputs one of the convolution coefficients to the respective convolution operator”. Therefore, the 35 U.S.C. 102(a)(1) and (a)(2) rejection of the claims has been withdrawn. However, this limitation is disclosed by the combination of Shinde and Bal. Bal discloses a FIR filter comprising a first plurality of multiplexers each coupled to a respective convolution operator wherein each multiplexer is connected to a respective memory bank of a plurality of memory banks storing a plurality of filter coefficient. Further, each multiplexer is configured to select and output one of the plurality of filter coefficient to the respective convolution operator. Furthermore, a same selection signal (i.e., input count) is provided to each of the multiplexers to select and output one of the plurality of filter coefficient to the respective convolution operator. On the other hand, Shinde Fig. 5 and discussed in col 10 lines 27 to col 13 line 7 discloses each multiplier is provided a different filter coefficient in each operation state. Accordingly, it would be obvious to configure the filter to include a plurality of memory banks each storing the plurality of filer coefficients C0-C7 and a first plurality of multiplexers each coupled a respective memory bank to receive the plurality of filer coefficients C0-C7 and select one filter coefficient to output the respective convolution operator. Furthermore, it is also obvious to configure each memory bank to store the filter coefficients in an order on which each respective filter coefficient is provided to each respective multiplier by configuring a first memory bank coupled to a first multiplexer and the first multiplier 241 to store the filter coefficient in the order C0, C7, C6, C5, C4, C3, C2, C1 similar to the arrangement of the register 230 in the first operation state. Configure a second memory bank coupled to a second multiplexer and the second multiplier 242 to store the filter coefficient in the order C1, C0, C7, C6, C5, C4, C3, C2 similar to the arrangement of the register 230 in the second operation state and so on until an eight memory bank coupled to an eight multiplexer and the eight multiplier 248 stores the filter coefficient in the order C7, C6, C5, C4, C3, C2, C1, C0 similar to the arrangement of the register 230 in the eight operation state in order to use a single selection signal (i.e., input count) for the plurality of coefficient multiplexers consistent with Fig. 2a and paragraphs [0032-0033] of Bal. Therefore, the combination of Shinde and Bal teaches “a plurality of convolution operators each coupled to the data output terminal of a respective register; and a first plurality of multiplexers each coupled to a respective convolution operator, wherein each first multiplexer receives a same set of a convolution coefficients in a different respective order and outputs one of the convolution coefficients to the respective convolution operator”.
Regarding independent claims 10 and 17, Applicant relied on same argument as claim 1. The rejection of claims 10 and 17 has been modified for at least the same reason as claim 1 discussed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
Prosecution Insights