DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application, 17867496 filed 07/18/2022 claims Priority from Provisional Application 63227129, filed 07/29/2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/18/2022 and 08/06/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 6 and 10-16 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 6 line 2, “a plurality of the registers” should read “the plurality of registers” instead for better clarity and consistency of claim terminologies.
B. In claim 10 line 1, “finite impulse response filter” should read “finite impulse response (FIR) filter” instead to clarify the meaning of the term “FIR” in the preamble of dependent claims 11-16. Claim 11-16 inherit the same deficiency as claim 10 by reason of dependence.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites “the data input terminals” in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 10 recites each register comprises an data input terminal and not a plurality of data input terminals. For purposes of examination, this is interpreted as the data input terminal. Claims 13-16 inherit the same deficiency as claim 12 by reason of dependence.
Claim 13 recites “the corresponding register” in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted to refer to the respective register. Claims 14-16 inherit the same deficiency as claim 13 by reason of dependence.
The term “approximately” in claim 14 is a relative term which renders the claim indefinite. The term “approximately” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Therefore, the phrase “approximately equal” is indefinite because it is unclear what specific range is covered by the phrase. Claims 15-16 inherit the same deficiency as claim 14 by reason of dependence.
Claim 16 recites “the filter clock” in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted to refer to the filter clock signal instead.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 7-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Shinde (US 6181733 B1).
Regarding claim 1, Shinde teaches
a filter input (Shinde Fig. 4 and col 9 lines 19-22 “A digital signal … is inputted to the signal input terminal 201”; filter input - signal input terminal 201);
a plurality of registers each having (Shinde Fig. 4 and col 9 lines 26-28 “Data input terminals D of the first to eighth flip-flop sets 211-218 constituting the storage section 210 are applied with the digital signal”; plurality of registers – 211-218):
a data input terminal coupled to the filter input (Shinde Fig. 4 data input terminal - Data input terminal D);
a data output terminal (Shinde Fig. 4 data output terminal - Data output terminal Q); and
a clock input terminal (Shinde Fig. 4 clock input terminal - clock input terminal C); and
a ring counter coupled to the clock input terminals of the registers (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively”; ring counter - write selection circuit 220).
Regarding claim 2, Shinde teaches all the limitations of claim 1 as stated above. Further, Shinde teaches further comprising a plurality of convolution operators each coupled to the data output terminal of a respective register (Shinde Fig. 4 and col 10 lines 13-17 “In the first to eighth multipliers 241-248, multiplication operations of output signals (6 bits) of the first to eighth flip-flop sets 211-218 by the despreading codes (1 bit) outputted from the first to eighth despreading code flip-flops 231-238 are carried out, respectively”; plurality of convolution operators - first to eighth multipliers 241-248).
Regarding claim 7, Shinde teaches all the limitations of claim 2 as stated above. Further, Shinde teaches further comprising a summer coupled to the convolution operators (Shinde Fig. 4; summer – adders 251-257).
Regarding claim 8, Shinde teaches all the limitations of claim 7 as stated above. Further, Shinde teaches wherein the summer is configured to sum output signals of the convolution operators (Shinde Fig. 7 and col 13 lines 8-35).
Regarding claim 9, Shinde teaches all the limitations of claim 1 as stated above. Further, Shinde teaches wherein the ring counter includes a plurality of flip- flops coupled in a ring configuration, each flip-flop having an output coupled to a clock input terminal of a respective register and to an input of a next flip-flop in the ring configuration (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively”; plurality of flip-flops - eighth write selecting flip-flops 221-228).
Regarding claim 10, Shinde teaches
n registers each including (Shinde Fig. 4 and col 9 lines 26-28 “Data input terminals D of the first to eighth flip-flop sets 211-218 constituting the storage section 210 are applied with the digital signal”; n registers – 211-218):
a data input terminal (Shinde Fig. 4 data input terminal - Data input terminal D);
a data output terminal (Shinde Fig. 4 data output terminal - Data output terminal Q); and
a clock input terminal (Shinde Fig. 4 clock input terminal - clock input terminal C); and
a ring counter including n flip-flops coupled in a ring configuration and each coupled to a clock input of a respective register (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively”; ring counter - write selection circuit 220; n flip-flops - eighth write selecting flip-flops 221-228).
Regarding claim 11, Shinde teaches all the limitations of claim 10 as stated above. Further, Shinde teaches further comprising a filter input coupled to the data input terminal of each register (Shinde Fig. 4 and col 9 lines 19-28 “A digital signal … is inputted to the signal input terminal 201 … Data input terminals D of the first to eighth flip-flop sets 211-218 constituting the storage section 210 are applied with the digital signal”; filter input - signal input terminal 201).
Regarding claim 12, Shinde teaches all the limitations of claim 11 as stated above. Further, Shinde teaches wherein the filter input is configured to pass input data values to the data input terminals of each register in accordance with a filter clock signal having a first frequency (Shinde Fig. 4 and col 9 lines 19-25 “A digital signal Io generated by sampling an analog signal (for example, a spectrum spread signal) at a sampling frequency of 4.096 MHz is inputted to the signal input terminal 201. The digital signal Io is a 6-bit digital signal in terms of two's complement which is synchronous with a clock CLK of 4.096 MHz inputted to the clock input terminal 202”; input data values - digital signal Io; filter clock – clock CLK; first frequency - 4.096 MHz).
Regarding claim 13, Shinde teaches all the limitations of claim 12 as stated above. Further, Shinde teaches wherein each flip-flop outputs a respective register clock signal with a second frequency to the clock input terminal of the corresponding register (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively”; second frequency – 1/8 of the clock CLK frequency).
Regarding claim 14, Shinde teaches all the limitations of claim 13 as stated above. Further, Shinde teaches wherein the second frequency is approximately equal to the first frequency divided by n (Shinde Fig. 4 and col 9 lines 28-55 the second frequency is 1/8 of the first frequency where n=8).
Regarding claim 15, Shinde teaches all the limitations of claim 14 as stated above. Further, Shinde teaches wherein each of the register clock signals are out of phase with each other (Shinde Fig. 4 and col 9 lines 28-55 “In the initial state, desired one of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220 is written with "1" (high level in logical value), and the other write selecting flip-flops are written with "0", (low level in logical value)”; only 1 register clock is high at a time).
Regarding claim 16, Shinde teaches all the limitations of claim 14 as stated above. Further, Shinde teaches wherein only one of the register clock signals is high at each cycle of the filter clock (Shinde Fig. 4 and col 9 lines 28-55 “In the initial state, desired one of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220 is written with "1" (high level in logical value), and the other write selecting flip-flops are written with "0", (low level in logical value)”).
Regarding claim 17, Shinde teaches
passing data values from a filter input of a finite impulse response (FIR) filter to data input terminals of each of a plurality of registers (Shinde Fig. 4 and col 9 lines 5-28 “A digital matched filter according to a first embodiment of the present invention is an eight-times spread 8-order digital matched filter constructed by using an FIR digital filter … A digital signal … is inputted to the signal input terminal 201 … Data input terminals D of the first to eighth flip-flop sets 211-218 constituting the storage section 210 are applied with the digital signal”; filter input - signal input terminal 201; plurality of registers – 211-218); data input terminals - Data input terminals D; FIR filter - 8-order digital matched filter constructed by using an FIR digital filter);
passing a pulse through a ring counter coupled to the registers and including a plurality of flip-flops coupled in a ring configuration (Shinde Fig. 4 and col 9 lines 28-55 ring counter - write selection circuit 220; plurality of flip-flops coupled in a ring configuration - eighth write selecting flip-flops 221-228; pulse – the “1” (high level in logical value) that is subsequently shifted to the flip-flops 221-228); and
controlling clock input terminals of the registers with the ring counter based on the pulse (Shinde Fig. 4 and col 9 lines 28-55 “Clock input terminals C of the first to eighth flip-flop sets 211-218 are applied with output signals of the first to eighth write selecting flip-flops 221-228 constituting the write selection circuit 220, respectively … so that the digital signal Io is sequentially fetched and held in the first to eighth flip-flop sets 211-218 in synchronism with the clock CLK”).
Regarding claim 18, Shinde teaches all the limitations of claim 17 as stated above. Further, Shinde teaches further comprising providing a respective data value from the filter input on each clock cycle of a filter clock signal (Shinde Fig. 4 and col 9 lines 19-25 “A digital signal Io generated by sampling an analog signal (for example, a spectrum spread signal) at a sampling frequency of 4.096 MHz is inputted to the signal input terminal 201. The digital signal Io is a 6-bit digital signal in terms of two's complement which is synchronous with a clock CLK of 4.096 MHz inputted to the clock input terminal 202”; filter clock signal – clock CLK).
Regarding claim 19, Shinde teaches all the limitations of claim 18 as stated above. Further, Shinde teaches further comprising processing each data value with only one of the registers (Shinde Fig. 4 and col 9 lines 28-55 “the "1" is sequentially applied to the clock input terminals C of the first to eighth flip-flop sets 211-218 constituting the storage section 210 in synchronism with the clock CLK, so that the digital signal Io is sequentially fetched and held in the first to eighth flip-flop sets 211-218 in synchronism with the clock CLK”; only one register receives a “1” applied to its clock input terminal C).
Regarding claim 20, Shinde teaches all the limitations of claim 19 as stated above. Further, Shinde teaches further comprising processing each data value with only one of the registers based on the pulse (Shinde Fig. 4 and col 9 lines 28-55 “the "1" is sequentially applied to the clock input terminals C of the first to eighth flip-flop sets 211-218 constituting the storage section 210 in synchronism with the clock CLK, so that the digital signal Io is sequentially fetched and held in the first to eighth flip-flop sets 211-218 in synchronism with the clock CLK”; only one register receives a “1” applied to its clock input terminal C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Shinde as applied to claim 2 above, and further in view of Bal et al. (US 20130110898 A1), hereinafter Bal.
Regarding claim 3, Shinde teaches all the limitations of claim 2 as stated above.
Shinde does not explicitly teach further comprising a first plurality of multiplexers each coupled to a respective convolution operator.
However, on the same field of endeavor, Bal discloses a FIR filter comprising a first plurality of multiplexers each coupled to a respective convolution operator (Bal Fig. 2(a) and paragraph [0033] “The input count 216-1 provided by the first counter 202-1 is provided to coefficient multiplexers 218-1, 218-2 ... 218-M, collectively known as coefficient multiplexers 218, coupled with a respective memory bank of the memory banks 204-1, 204-2 ... 204-M. In one embodiment, the input count 216-1 is provided through a control unit 220. The coefficient multiplexer 218 is configured to select one of the filter coefficients stored in each of the memory banks 204, based on the output of the control unit 220, for multiplying the selected filter coefficient with an input sample” paragraph [0038] “The MAC units 206 compute the product of the selected filter coefficient with the received input sample”; first plurality of multiplexers - coefficient multiplexers 218; respective convolution operator - MAC units 206 or multipliers 208).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shinde using Bal and configure the filter to include a first plurality of multiplexers each coupled to a respective convolution operator (i.e., multiplier) in order to select and provide the proper coefficient to each of the multipliers (Bal paragraph [0030]), for example, by replacing or implementing the block 320 of Shinde using a plurality of multiplexers.
Therefore, the combination of Shinde as modified in view of Bal teaches further comprising a first plurality of multiplexers each coupled to a respective convolution operator.
Regarding claim 4, Shinde as modified in view of Bal teaches all the limitations of claim 3 as stated above. Further, Shinde as modified in view of Bal teaches wherein the each first multiplexer receives a plurality of convolution coefficients and outputs one of the convolution coefficients to the respective convolution operator (Bal Fig. 2a and paragraph [0033]).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Shinde as applied to claim 2 above, and further in view of Gunwani et al. (US 8612503 B2), hereinafter Gunwani.
Regarding claim 5, Shinde teaches all the limitations of claim 2 as stated above.
Shinde does not explicitly teach further comprising a second plurality of multiplexers each coupled a respective convolution operator.
However, on the same field of endeavor, Gunwani discloses a second multiplexer coupled a convolution operator (Gunwani Figs. 3 and 5 second multiplexer – data selection mux 530).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shinde and generalize the teaching of Gunwani by configuring the filter to include a second plurality of multiplexers each coupled a respective convolution operator by duplicating the arrangement similar to Fig. 5 of Gunwani as many times as the number of multipliers (i.e., 8 times one for each multipliers 631-638) for selecting which data from registers 211-218 is to be provided to each respective multiplier to allow for a more efficient and flexible mapping of filter algorithms to an array of multipliers/convolution operators of the filter (Gunwani col 9 lines 5-35]).
Therefore, the combination of Shinde as modified in view of Gunwani teaches further comprising a second plurality of multiplexers each coupled a respective convolution operator.
Regarding claim 6, Shinde as modified in view of Gunwani teaches all the limitations of claim 5 as stated above. Further, Shinde as modified in view of Gunwani teaches wherein each second multiplexer receives output signals from a plurality of the registers and outputs one of the output signals to the convolution operator (Gunwani Fig. 5 and col 8 line 62 to col 9 line 20 “A shift register 520 includes serially connected shift registers wherein each register may provide an input to a data selection multiplexer 530 … Selection of which input to present on the output of the multiplexer 530 is controlled by a configurable counter 540”).
Conclusion
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767