DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Joint Inventors
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Amendments
Applicant’s amendment filed 01/09/2026 has been considered and entered.
The objection to the claims set forth in the office action received 09/11/2025 is withdrawn in view of the applicant’s amendments.
The rejection under 35 USC 112(b) set forth in the office action received 09/11/2025 is withdrawn in view of the applicant’s amendments.
Response to Arguments
The applicant’s arguments received 01/09/2026 have been fully considered but are moot in view of modified grounds for rejection. Amended limitations relating to the “…connector comprising a female receptacle to receive a male portion of the FAU…” of claims 1 and 11 and the “…male portion inside the female receptacle of the connector…” of claim 20 are taught by Butler [US 10345535 B2] (See the 35 USC 103 section of this office action).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Mayukh (US 20230367087 A1) in view of Butler (US 10345535 B2).
With regards to claim 1, Mayukh discloses an integrated circuit device comprising:
a glass core layer (Mayukh/Fig3/Core 310; Paragraph 34);
one or more build-up layers on the glass core layer (Fig3; Paragraph 35);
a photonics integrated circuit (PIC) at least partially within a cavity of the glass core layer (Fig3/PIC 320); and
an optical path between the PIC and an end of the integrated circuit device (Fig3), and
a connector (Fig3/Connector 330b) to direct light to the optical path.
Mayukh is silent regarding the connector coupling with a pluggable fiber array unit (FAU), the connector comprising a female receptacle to receive a male portion of the FAU. However, the practice of coupling a pluggable FAU with a male portion to a connector with a female portion exists in the art as exemplified by Butler.
Mayukh and Butler are considered to be analogous in the field of optical devices. Mayukh discloses an optical path between a PIC and a connector to direct light to the optical path. Butler teaches a pluggable FAU with a male portion which pluggably interfaces with a female portion of a connector (Butler/Fig23/Connector 150, Female portion 10, FAU 400, and male portion 702). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the connector of Mayukh such that it couples to a pluggable FAU via respective female and male portions as suggested by Butler since doing so would facilitate precise optical alignment and offer greater structural stability.
With regards to claim 2, Mayukh and Butler together disclose the integrated circuit device of claim 1, wherein the optical path includes a waveguide formed in the glass core layer (Paragraph 36/Lines 10-22).
With regards to claim 5, Mayukh and Butler together disclose the integrated circuit device of claim 1, wherein the optical path includes a microlens (Paragraph 36/Lines 10-22).
With regards to claim 6, Mayukh and Butler together disclose the integrated circuit device of claim 1, further comprising an electronic integrated circuit (EIC) in electrical connection with the PIC (Fig3/EIC 325; Paragraph 37).
With regards to claim 7, Mayukh and Butler together disclose the integrated circuit device of claim 6, wherein the EIC is at least partially embedded in the one or more build-up layers (Fig3; Paragraph 35/ “…the substrate 305 may itself be a glass substrate comprising one or more layers…”).
With regards to claim 8, Mayukh and Butler together disclose the integrated circuit device of claim 6, wherein the EIC is on the build-up layers (Fig3 [PIC 320 is located on top of multiple layers comprising substrate 305]).
Claims 9-12 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Mayukh (US 20230367087 A1) as applied to claim 6 above, in view of Lin (US 20210167053 A1) and Butler (US 10345535 B2).
With regards to claim 9, Mayukh and Butler together disclose the integrated circuit device of claim 6. Mayukh and Butler disclose a die in electrical connection with the EIC (Figs2-3; Paragraph 31), but is silent regarding a processor. However, the practice of configuring an integrated circuit package such that it includes a processor exists in the art as exemplified by Lin.
Mayukh, Butler, and Lin are considered to be analogous in the field of integrated circuit packages. Lin teaches an integrated circuit package with a processor die (Lin/Fig1/Paragraph 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the integrated circuit package disclosed by Mayukh and Butler such that it included a processor die as suggested by Lin since doing so would allow for on-package processing capabilities (forgo a need for an additional external processor to be linked to the package).
With regards to claim 10, Mayukh, Butler, and Lin together disclose the integrated circuit device of claim 9, wherein the one or more build-up layers include at least one redistribution layer to electrically connect the processor and the EIC (Mayukh/Paragraph 35).
With regards to claim 11, Mayukh discloses an integrated circuit package (Fig3/Semiconductor package 300) comprising:
a package substrate (Fig3/Substrate 305) comprising a glass core layer (Fig3/Core 310);
an optical path at least partially in the glass core layer (Fig3; Paragraph 36);
a photonics integrated circuit (PIC) (Fig3/PIC 320) at least partially embedded in the glass core layer and in optical connection with the optical path; and
an electronic integrated circuit (EIC) (Fig3/EIC 325) in electrical connection with the PIC (Paragraph 37), and
a connector (Fig3/Connector 330b) to direct light to the optical path.
Mayukh discloses a die in electrical connection with the EIC (Figs2-3; Paragraph 31), but is silent regarding a processor and regarding the connector coupling with a pluggable fiber array unit (FAU), the connector comprising a female receptacle to receive a male portion of the FAU. However, the practice of configuring an integrated circuit package such that it includes a processor and the practice of coupling a pluggable FAU with a male portion to a connector with a female portion exists in the art as exemplified by Lin and Butler respectively.
Mayukh and Lin are considered to be analogous in the field of integrated circuit packages. Lin teaches an integrated circuit package with a processor die (Lin/Fig1/Paragraph 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the integrated circuit package disclosed by Mayukh such that it included a processor die as suggested by Lin since doing so would allow for on-package processing capabilities (forgo a need for an additional external processor to be linked to the package).
Mayukh, Lin, and Butler are considered to be analogous in the field of optical devices. Mayukh and Lin disclose an optical path between a PIC and a connector to direct light to the optical path. Butler teaches a pluggable FAU with a male portion which pluggably interfaces with a female portion of a connector (Butler/Fig23/Connector 150, Female portion 10, FAU 400, and male portion 702). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the connector of Mayukh and Lin such that it couples to a pluggable FAU via respective female and male portions as suggested by Butler since doing so would facilitate precise optical alignment and offer greater structural stability.
With regards to claim 12, Mayukh, Lin, and Butler together disclose the integrated circuit package of claim 11, wherein the optical path includes a waveguide in the glass core layer (Mayukh/Paragraph 36/Lines 10-22).
With regards to claim 15, Mayukh, Lin, and Butler together disclose the integrated circuit package of claim 11, wherein the optical path includes a microlens (Mayukh/Paragraph 36/Lines 10-22).
With regards to claim 16, Mayukh, Lin, and Butler together disclose the integrated circuit package of claim 11, wherein the EIC is at least partially embedded in package substrate (Mayukh/Fig3; Paragraph 35).
With regards to claim 17, Mayukh, Lin, and Butler together disclose the integrated circuit package of claim 11, wherein the EIC is on the package substrate (Mayukh/Fig3).
With regards to claim 18, Mayukh, Lin, and Butler together disclose the integrated circuit package of claim 17, wherein the package substrate comprises at least one redistribution layer to electrically connect the processor and the EIC (Mayukh/Paragraph 35).
With regards to claim 19, Mayukh, Lin, and Butler together disclose the integrated circuit package of claim 17, wherein the package substrate comprises bridge circuitry to electrically connect the processor and the EIC (Mayukh/Paragraph 35 [Copper interconnects]).
Claims 20-22 and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Mayukh (US 20230367087 A1) in view of Lin (US 20210167053 A1) and Butler (US 10345535 B2).
With regards to claim 20, Mayukh discloses a system comprising:
an integrated circuit package comprising:
a substrate (Substrate 305) comprising a glass core layer (Core 310);
an optical path at least partially in the glass core layer (Fig3);
a photonics integrated circuit (PIC) (PIC 320) at least partially embedded in the glass core layer and in optical connection with the optical path (Fig3); and
an electronic integrated circuit (EIC) (EIC 325) in electrical connection with the PIC (Paragraph 37), and
a connector (Fig3/Connector 330b).
Mayukh discloses a die in electrical connection with the EIC (Figs2-3; Paragraph 31) and a fiber optic coupler (Fig3/FOC 330b), but is silent regarding a processor and a pluggable FAU wherein the pluggable FAU comprising a male portion inside a female receptacle of the connector. However, the practices of configuring an integrated circuit package such that it includes a processor and a pluggable FAU with a male portion inside a female receptacle of the connector exist in the art as exemplified by Lin and Butler respectively.
Mayukh and Lin are considered to be analogous in the field of integrated circuit packages. Lin teaches an integrated circuit package with a processor die (Lin/Fig1/Paragraph 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the integrated circuit package disclosed by Mayukh such that it included a processor die as suggested by Lin since doing so would allow for on-package processing capabilities (forgo a need for an additional external processor to be linked to the package).
Mayukh, Lin, and Butler are considered to be analogous in the field of integrated circuit packages. Butler teaches a pluggable FAU with a male portion which pluggably interfaces with a female portion of a connector (Butler/Fig23/Connector 150, Female portion 10, FAU 400, and male portion 702). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the connector of Mayukh such that it couples to a pluggable FAU via respective female and male portions as suggested by Butler since doing so would facilitate precise optical alignment and offer greater structural stability.
With regards to claim 21, Mayukh, Lin, and Butler together disclose the system of claim 20, wherein the optical path includes a waveguide in the glass core layer (Mayukh/Paragraph 36/Lines 10-22).
With regards to claim 22, Mayukh, Lin, and Butler together disclose the system of claim 20, wherein the optical path includes a microlens (Mayukh/Paragraph 36/Lines 10-22).
With regards to claim 24, Mayukh, Lin, and Butler together disclose the system of claim 20, wherein the EIC is at least partially embedded in the package substrate (Mayukh, Fig3).
With regards to claim 25, Mayukh Lin, and Butler together disclose the system of claim 20, wherein the EIC is on the package substrate (Mayukh, Fig3).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marc E Manheim whose telephone number is (703)756-1873. The examiner can normally be reached 6:30am - 5pm E.T., Monday - Tuesday and Thursday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARC E MANHEIM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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