DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The claim objections regarding to claims 1 and 19 is withdrawn.
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f): (FP 7.30.03)
(f) ELEMENT IN CLAIM FOR A COMBINATION-An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35
112, sixth paragraph, is invoked.
As explained in MPEP 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as "configured to" or "so that"; and
the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. (FP 7.30.05)
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: a quantum circuit distributor, a multi-quantum register controller in claim 1, a quantum circuit analyzer in claim 3, an operation resource distributor in claim 5, a quantum operator in claim 10, a quantum noise generator in claim 16.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. (FP 7.30.06)
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-19 are rejected under 35 U.S.C. 101
because the claimed invention is directed to an abstract idea without significantly
more.
When considering subject matter eligibility under 35 U.S.C. 101, it must be
determined whether the claim is directed to one of the four statutory categories of
invention, i.e., process, machine, manufacture, or composition of matter (Step 1). If the
claim does fall within one of the statutory categories, the second step in the analysis is
to determine whether the claim is directed to a judicial exception (Step 2A). The Step 2A
analysis is broken into two prongs. In the first prong (Step 2A, Prong 1), it is determined
whether or not the claims recite a judicial exception (e.g., mathematical concepts,
mental processes, certain methods of organizing human activity). If it is determined in
Step 2A, Prong 1 that the claims recite a judicial exception, the analysis proceeds to the
second prong (Step 2A, Prong 2), where it is determined whether or not the claims
integrate the judicial exception into a practical application. If it is determined at step 2A,
Prong 2 that the claims do not integrate the judicial exception into a practical
application, the analysis proceeds to determining whether the claim is a patent-eligible
application of the exception (Step 2B). If an abstract idea is present in the claim, any
element or combination of elements in the claim must be sufficient to ensure that the
claim integrates the judicial exception into a practical application, or else amounts to
significantly more than the abstract idea itself. Applicant is advised to consult the 2019
PEG for more details of the analysis.
Step 1
According to the first part of the analysis, in the instant case, claims 1-18, 19 are directed to an apparatus and method of quantum simulation. Thus, each of the claims falls within one of the four statutory categories (i.e. process, machine, manufacture, or composition of matter). Step 2A,
Step 2A, Prong 1
Following the determination of whether or not the claims fall within one of the four
categories (Step 1), it must be determined if the claims recite a judicial exception (e.g.
mathematical concepts, mental processes, certain methods of organizing human
activity) (Step 2A, Prong 1). In this case, the claims are determined to recite a judicial
exception as explained below.
Regarding Claims 19 and 1 these claims recite
receiving a plurality of quantum circuits;
distributing the plurality of quantum circuits in multi-quantum registers;
configuring a reduced quantum state space with respect to the quantum circuits distributed in the multi-quantum registers; and
controlling execution of the multi-quantum registers in which the reduced quantum state space is configured, wherein the configuring of the reduced quantum state space with respect to the quantum circuits distributed into the multi-quantum registers includes configuring the reduced quantum state space with respect to a real quantum state having a physical reality with an amplitude value that is not 0 in a wide-area quantum state space, and wherein each multi-quantum register maintains a quantum index for each real quantum state to preserve its logical position in the wide-area quantum state space.
The claims recite a mental process. As set forth in MPEP 2106.04(a)(2)(III)(C), “Claims can recite a mental process even if they are claimed as being performed on a computer”. These are recited at a high level and disclosed as a human user performing these functions, simply using a computer as a tool-see spec, [0048-0054], Fig. 3, etc. Thus, the claim recites abstract ideas.
Step 2A, Prong 2
Following the determination that the claims recite a judicial exception, it must be
determined if the claims recite additional elements that integrate the exception into a
practical application of the exception (Step 2A, Prong 2). In this case, after considering
all claim elements individually and as an ordered combination, it is determined that the
claims do not include additional elements that integrate the exception into a practical
application of the exception as explained below.
In Prong Two, a claim is evaluated as a whole to determine whether the recited judicial exception is integrated into a practical application of that exception. A claim is not “directed to” a judicial exception, and thus is patent eligible, if the claim as a whole integrates the recited judicial exception into a practical application of that exception. A claim that integrates a judicial exception into a practical application will apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that the claim is more than a drafting effort designed to monopolize the judicial exception. MPEP 2106.04(d). The claims recite an abstract idea and further the claims as a whole does not integrate the recited judicial exception into a practical application of the exception. A claim that integrates a judicial exception into a practical application will apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that the claim is more than a drafting effort designed to monopolize the judicial exception. MPEP 2106.04(d).
Regarding Claims 1, 19 these claims
Mere Instructions to Apply an Exception. Do the additional element(s) amount to merely the words “apply it” (or an equivalent) or are mere instructions to implement an abstract idea or other exception on a computer? (Yes)
This limitation is understood to be generic computer equipment and mere instructions to implement an abstract idea on a computer, or merely the words “apply it” (or an equivalent) or merely uses a computer as a tool to perform an abstract idea -which is not indicative of integration into a practical application. MPEP 2106.05(f).)
Step 2B
Based on the determination in Step 2A of the analysis that the claims are
directed to a judicial exception, it must be determined if the claims contain any element
or combination of elements sufficient to ensure that the claim amounts to significantly
more than the judicial exception (Step 2B). In this case, after considering all claim
elements individually and as an ordered combination, it is determined that the claims do
not include additional elements that are sufficient to amount to significantly more than
the judicial exception for the same reasons given above in the Step 2A, Prong 2
analysis. Furthermore, each additional element identified above as being insignificant
extra-solution activity is also well-known, routine, conventional as described below.
Claims 1, 19: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components and field of use/technological environment which do not amount to significantly more than the abstract idea. The underlying concept merely receives information, analyzes it, and store the results of the analysis – this concept is not meaningfully different than concepts found by the courts to be abstract (see Electric Power Group, collecting information, analyzing it, and displaying certain results of the collection and analysis; see Cybersource, obtaining and comparing intangible data; see Digitech, organizing information through mathematical correlations; see Grams, diagnosing an abnormal condition by performing clinical tests and thinking about the results; see Cyberfone, using categories to organize store and transmit information; see Smartgene, comparing new and stored information and using rules to identify options). The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. For example, claim 1 recites the additional elements of “receiving…”, “distributing…”, configuring”, controlling…and wherein each multi-quantum register maintains a quantum index for each real quantum state to preserve its logical position in the wide-area quantum state space. These elements are recited at a high level of generality and are well-understood, routine, and conventional activities in the computer art. Generic computers performing generic computer functions, without an inventive concept, do not amount to significantly more than the abstract idea. Looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims do not amount to significantly more than the abstract idea itself.
Step 2A/2B Prong 2 Dependent Claims
Regarding to claim 2
Claim 2 merely recite other additional elements that define qubits which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 3-4
Claim 3-4 merely recite other additional elements that predict an execution complexity which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 5
Claim 5 merely recite other additional elements that distribution operation resources based on the predicted execution complexity which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 6
Claim 6 merely recite other additional elements that form the reduced quantum state space which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 7-8
Claim 7-8 merely recite other additional elements that define quantum register which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 9
Claim 9 merely recite other additional elements that define matrix operation to the quantum state vector which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 10
Claim 10 merely recite other additional elements that define quantum operator which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 11-12
Claim 11-12 merely recite other additional elements that calculate an amplitude value which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 13
Claim 13 merely recite other additional elements that define remove the quantum state if amplitude value is 0 which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 14
Claim 14 merely recite other additional elements that define update the amplitude if amplitude value is not 0 which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 15
Claim 15 merely recite other additional elements that define objective matric operation based on the control qubit state which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Regarding to claim 16-18
Claim 16-18 merely recite other additional elements that define noise generator with types of errors and rate of errors which performing generic functions that when looking at the elements as a combination does not add anything more than the elements analyzed individually. Therefore, these claims also do not amount to significantly more than the abstract idea itself. These claims are not patent eligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Doi US 2020/0218787 in view of Haener et al. (Haener) US 2021/0374307 and Liang et al. (Liang) US 2021/0271477
In regard to claim 1, Doi disclose A quantum simulation apparatus comprising: ([0004][0025-[0027] a quantum computing simulation computer system)
a quantum circuit distributor configured to receive and transfer a plurality of quantum circuits; (Fig. 1, [0031]- [0040] 104 receive from 120 and transferred to 150 based on the configurations) and
a multi-quantum register controller configured to control independent allocation and execution of the plurality of quantum circuits into multi-quantum registers supporting a reduced quantum state space, (Fig. 1, [0031]-[0040] [0063][0106][0118] 150 has a memory allocator that allocates memory space for simulating n qubit system, “The quantum circuit may begin by preparing the qubits in well-defined states (e.g., the ground state), then executing a series of one- and two-qubit gates in time, followed by a measurement of the qubits.” and the quantum register declaration corresponding to designation of qubits n, and using hierarchical index table to reduce the overheads.
wherein the multi-quantum registers provide the reduced quantum state space with respect to a real quantum state having the amplitude value in a wide-area quantum state space. (Fig.3, [0045]- [0055-[0063] [0070]-[0072] [0106][0118] each device memory registers provide space to store qubits’ states and amplitudes which are complex numbers in the multiple computing nodes and each node has device memory to store qubits with vector space, the quantum state has an amplitude)
But Doi fail to explicitly disclose “the real quantum state having a physical reality with an amplitude value that is not 0.”
Haener disclose the real quantum state having a physical reality with the n amplitude value that is not 0. ([0063]-[0069] [0102]-[0104] the quantum state having the adjusted amplitude and the amplitude can be adjusted and controlled so it can be not 0 based on the change of the quantum state.)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Haener‘s quantum state simulation into Doi’s invention as they are related to the same field endeavor of quantum simulation. The motivation to combine these arts, as proposed above, at least because Haener‘s quantum state simulation with adjustable amplitude would help to provide more controlled quantum states into Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more controlled quantum states with adjusted amplitude would help to improve quantum state simulation and facilitate the system to handle a broader range of quantum circuits.
But Doi and Haener fail to explicitly disclose “and wherein each multi-quantum register maintains a quantum index for each real quantum state to preserve its logical position in the wide-area quantum state space.”
Jiang disclose and wherein each multi-quantum register maintains a quantum index for each real quantum state to preserve its logical position in the wide-area quantum state space. ([0003][0016]-[0018][0040]-[0045][0051]-[0056] “a register of log L qubits is prepared, … and where each register basis state indexes a corresponding quantum state computational basis state,.. for each index 1 to L, control, transformation of the register state for the index to the corresponding computational basis state for the index, its state is mapped to a superposition of basis states which corresponding to index L. Note: please further define how the amplitude not 0 related to the quantum index, how the quantum state space is reduced, how the logical position is preserved, what is the logical position etc. to help move forward the prosecution. Call to discuss if necessary)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Jiang‘s preparing superpositions of computational basis states on a quantum computer into Haener and Doi’s invention as they are related to the same field endeavor of quantum simulation. The motivation to combine these arts, as proposed above, at least because Jiang‘s preparing superpositions of computational basis states using index would help to provide more controlled quantum states into Haener and Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more controlled quantum states using index would help to improve quantum state simulation and facilitate the system to handle a broader range of quantum circuits.
In regard to claim 2, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 1,
Doi disclose wherein as the quantum circuits are allocated, the multi-quantum registers are configured to manage the reduced quantum state space composed of independent qubits, but not to allow information exchange among the respective quantum registers. (Fig. 1, [0031]-[0040] [0047] [0054]-[0063][0106]-[0109] [0118] [0129]-[0131] 150 has a memory allocator that allocates memory space for simulating n qubit system, “The quantum circuit may begin by preparing the qubits in well-defined states (e.g., the ground state)” allocate n qubits on the system, avoided data exchange in gate operation)
In regard to claim 3, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 1,
Doi disclose further comprising a quantum circuit analyzer configured to predict an execution complexity for the input quantum circuits, wherein the quantum circuit distributor is configured to transfer the quantum circuits and the predicted execution complexity of the quantum circuits to the multi-quantum register controller. (Fig. 1, [0031]-0048] analyze the complexity of the circuits with n qubits (the complex vector space of an n qubits) with gate operation and transfer the n qubit system to the 150)
In regard to claim 4, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 3,
Doi disclose wherein the quantum circuit analyzer is configured to predict the execution complexity by applying specific weight values to the number of qubits of the quantum circuits, the number of gate operations applied to the quantum circuits, and depth information of the quantum circuit. (Fig. 1, [0031]-0048] analyze the complexity of the circuits with n qubits (the complex vector space of an n qubits) with states and including the weighted sum or difference of the multiple states corresponding to superposition, etc. with a series quantum gates operations and corresponding 2 level of the vectors corresponding to the gate for the n qubits)
In regard to claim 5, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 3,
Doi disclose further comprising an operation resource distributor configured to distribute computing resources for the multi-quantum registers based on the predicted execution complexity, wherein the operation resource distributor is configured to distribute the computing resources to the corresponding quantum registers in accordance with a ratio of the execution complexity of the individual quantum circuit to the total execution complexity of the plurality of quantum circuits with respect to the entire computing resources. (Fig. 3, [0045]-[0060] distributing computer memory based on the problem complexity and distributing the memory based on the ratio of unit, process and the total problem calculation complexity)
In regard to claim 6, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 1,
Doi disclose wherein each multi-quantum register is configured to form the reduced quantum state space by allocating a quantum index representing a position in 2N wide-area quantum state spaces composed of N qubits to the real quantum state configuring the reduced quantum state space. (Fig. 3, [0045]-[0060] 2N qubit states vector with N qubits’ states with index number for each qubit)
In regard to claim 7, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 6,
Doi disclose wherein the quantum register comprises a plurality of index containers for parallel processing of quantum state tracking and quantum operations, and wherein real quantum states are stored in the order of quantum indexes in the index container. (Fig. 7, [0034]-[0040] [0046] [0074]-[0087] the vector include indexes for representing the processes and units for parallel processing of gate operations and state measurements)
In regard to claim 9, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 1,
Doi disclose wherein the multi-quantum register controller is configured to apply a matrix operation only in case that an amplitude of at least one of quantum state vectors constituting a quantum state pair in case of applying the matrix operation in accordance with performing of a quantum gate operation in the reduced quantum state space. ([0046] [0055]-[0072] [0074]-[0087] simulating to perform gate operation (CNOT) for the allocated memory block when the vector include paired quantum amplitudes apply the CNOT operation which is a matrix operation based on the control qubit, for example)
In regard to claim 10, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 1,
Doi disclose further comprising a quantum operator configured to provide at least one of a 1-qubit gate operation rule and a 2-qubit gate operation rule to the quantum register. ([0037]-[0038] [0069] gate operation include single-qubit gates and two-qubits gates operation)
In regard to claim 11, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 10,
Doi disclose wherein in case that the 1-qubit gate operation rule is applied to the quantum operator, the multi-quantum register controller is configured to: calculate an amplitude value of the quantum state pairs corresponding to a quantum state given to the multi-quantum state register, calculate a new amplitude value by applying the matrix operation for the amplitude value of the quantum state pair, and then update the quantum register with the amplitude value calculated as the result of the matrix operation. ([0037]-[0038][0046] [0055]-[0072] [0074]-[0087] simulating to perform 1-qubit gate operation, and calculating the amplitude value of the quantum state pairs corresponding to the quantum state and calculate the amplitudes by apply the gate operation for the quantum state pair and update the vector with the amplitudes)
In regard to claim 12, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 11,
Doi disclose wherein the multi-quantum register controller is configured to calculate the amplitude value of the quantum state pairs by using a stored amplitude if the quantum state pair exists in the quantum register ([0037]-[0038][0046] [0055]-[0072] [0074]-[0087] calculate the amplitudes with the stored quantum state pair when it inter-unit calculation)
But Doi, Jiang fail to explicitly disclose “and by initializing the amplitude value to 0 if the quantum state pair does not exist in the quantum register.”
Haener disclose and by initializing the amplitude value to 0 if the quantum state pair does not exist in the quantum register. ([0018][0044][0058]-[0063] [0103] initializing the amplitude value to 0 when the state pair does not exist yet)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Haener‘s quantum state simulation into Jiang and Doi’s invention as they are related to the same field endeavor of quantum simulation. The motivation to combine these arts, as proposed above, at least because Haener‘s quantum state simulation with zeroing amplitude would help to provide more controlled quantum states into Jiang and Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more controlled quantum states with zeroed amplitude would help to improve quantum state simulation and facilitate the system to handle a broader range of quantum circuits.
In regard to claim 13, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 11,
But Doi, Jiang fail to explicitly disclose “wherein in case that the amplitude value to be updated is 0, the multi- quantum register controller is configured to remove the quantum state from the quantum register if the quantum state corresponding to the quantum state pair exists in the quantum register.”
Haener disclose wherein in case that the amplitude value to be updated is 0, the multi- quantum register controller is configured to remove the quantum state from the quantum register if the quantum state corresponding to the quantum state pair exists in the quantum register. ([0018][0044][0058]-[0063] [0103] initializing the amplitude value to 0 and if removing the quantum qubit and the amplitude corresponding to the qubit state is adjusted pursuant to the deallocation from the quantum register)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Haener‘s quantum state simulation into Jiang and Doi’s invention as they are related to the same field endeavor of quantum simulation. The motivation to combine these arts, as proposed above, at least because Haener‘s quantum state simulation with zeroing amplitude would help to provide more controlled quantum states into Jiang and Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more controlled quantum states with zeroed amplitude would help to improve quantum state simulation and facilitate the system to handle a broader range of quantum circuits.
In regard to claim 14, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 11,
But Doi , Jiang fail to explicitly disclose “wherein in case that the amplitude value to be updated is not 0, the multi-quantum register controller is configured to: update the amplitude value of the quantum state with the amplitude value to be updated if the quantum state corresponding to the quantum state pair exists in the quantum register, and allocate a new quantum state as a data storage item and add the new quantum state to the quantum register if the quantum state corresponding to the quantum state pair does not exist.”
Haener disclose wherein in case that the amplitude value to be updated is not 0, the multi-quantum register controller is configured to: update the amplitude value of the quantum state with the amplitude value to be updated if the quantum state corresponding to the quantum state pair exists in the quantum register, and allocate a new quantum state as a data storage item and add the new quantum state to the quantum register if the quantum state corresponding to the quantum state pair does not exist. ([0018][0044]-[0058] [0073] [0103] when it is not at initialized state, adjust the amplitude of the quantum state if the quantum state pair exists and allocate a new state for the qubit in the memory and add the new state to the quantum register of the qubit is the state pair do not exist)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Haener‘s quantum state simulation into Jiang and Doi’s invention as they are related to the same field endeavor of quantum simulation. The motivation to combine these arts, as proposed above, at least because Haener‘s quantum state simulation with zeroing amplitude would help to provide more controlled quantum states into Jiang and Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more controlled quantum states with zeroed amplitude would help to improve quantum state simulation and facilitate the system to handle a broader range of quantum circuits.
In regard to claim 15, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 10,
Doi disclose wherein in case that the 2-qubit gate operation rule is applied in the quantum operator, the multi-quantum register controller is configured to: sequentially traverse the real quantum states stored in the quantum register, and select only a case where the quantum state of a control qubit is a |1> state as an objective matrix operation application target, and apply an objective matrix operation to the quantum state pairs corresponding to the objective qubit. (Fig. 7, [0031]-[0039][0046] [0055]-[0072] [0074]-[0087] simulating to perform two-qubit gate operation wits a sequence of operations and select a control qubit is a |1> state as an object operation target (may dominate whether all the amplitudes within a predetermined range are targeted or not) based on the offset of an dress between paired two elements and apply the gate operation to the state pairs corresponding to the target qubit)
In regard to claim 19, A method performed by a quantum simulation apparatus comprising: ([0004][0025-[0027] method of performed by a computing node for simulating quantum computing )
receiving a plurality of quantum circuits; (Fig. 1, [0031]- [0040] 104 receive from 120 and transferred to 150 based on the configurations) and
distributing the plurality of quantum circuits in multi-quantum registers; (Fig. 1, [0031]-[0040] [0063][0106][0118] transfer 104 to 150 based on the configurations, 150 has a memory allocator that allocates memory space for simulating n qubit system)
configuring a reduced quantum state space with respect to the quantum circuits distributed in the multi-quantum registers; (Fig. 1, [0031]-[0040] [0063][0106][0118] 150 has a memory allocator that allocates memory space for simulating n qubit system, “The quantum circuit may begin by preparing the qubits in well-defined states (e.g., the ground state), then executing a series of one- and two-qubit gates in time, followed by a measurement of the qubits.” and the quantum register declaration corresponding to designation of qubits n, and using hierarchical index table to reduce the overheads) and
controlling execution of the multi-quantum registers in which the reduced quantum state space is configured, (Fig. 1, [0031]-[0040] [0063][0106][0118] executing a series of one- and two-qubit gates stored in the memory registers in time, followed by a measurement of the qubits. and the quantum register declaration corresponding to designation of qubits n, and using hierarchical index table to reduce the overheads)
wherein the configuring of the reduced quantum state space with respect to the quantum circuits distributed into the multi-quantum registers includes configuring the reduced quantum state space with respect to the amplitude value in a wide-area quantum state space. (Fig.3, [0045]- [0055-[0063] [0072] [0106][0118] each device memory registers provide space to store qubits’ states and amplitudes which are complex numbers in the multiple computing nodes and each node has device memory to store qubits with vector space, the amplitudes within a predetermined range can be determined, that means amplitude value 0 can be ruled out)
But Doi fail to explicitly disclose “a real quantum state having a physical reality with the amplitude value that is not 0”
Haener disclose the real quantum state having a physical reality with the n amplitude value that is not 0. ([0063]-[0069] [0102]-[0104] the quantum state having the adjusted amplitude and the amplitude can be adjusted and controlled so it can be not 0 based on the change of the quantum state)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Haener‘s quantum state simulation into Doi’s invention as they are related to the same field endeavor of quantum simulation. The motivation to combine these arts, as proposed above, at least because Haener‘s quantum state simulation with adjustable amplitude would help to provide more controlled quantum states into Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more controlled quantum states with adjusted amplitude would help to improve quantum state simulation and facilitate the system to handle a broader range of quantum circuits.
But Doi and Haener fail to explicitly disclose “and wherein each multi-quantum register maintains a quantum index for each real quantum state to preserve its logical position in the wide-area quantum state space.”
Jiang disclose and wherein each multi-quantum register maintains a quantum index for each real quantum state to preserve its logical position in the wide-area quantum state space. ([0003][0016]-[0018][0040]-[0045][0051]-[0056] “a register of log L qubits is prepared, … and where each register basis state indexes a corresponding quantum state computational basis state,.. for each index 1 to L, control, transformation of the register state for the index to the corresponding computational basis state for the index, its state is mapped to a superposition of basis states which corresponding to index L)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Jiang‘s preparing superpositions of computational basis states on a quantum computer into Haener amd Doi’s invention as they are related to the same field endeavor of quantum simulation. The motivation to combine these arts, as proposed above, at least because Jiang‘s preparing superpositions of computational basis states using index would help to provide more controlled quantum states into Haener and Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more controlled quantum states using index would help to improve quantum state simulation and facilitate the system to handle a broader range of quantum circuits.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Doi US 2020/0218787, Haener et al. (Haener) US 2021/0374307, and Liang et al. (Liang) US 2021/0271477 as applied to claim 1, further in view of Rathke et al. (Rathke) US 2017/0329635
In regard to claim 8, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 7,
Doi disclose wherein the index container comprises a metadata area for managing the number of quantum states included in an index container area, and a data area for storing attribute information including quantum index and amplitude values of the real quantum states. (Fig. 7, [0034]-[0040] [0046] [0074]-[0087] the vector area include indexes for storing quantum states and section including quantum index and amplitudes of the quantum states)
But Doi and Haener, Jiang fail to explicitly disclose “and lock information supporting parallel processing of the quantum operations,”
Rathke disclose and lock information supporting parallel processing of the quantum operations. ([0007]-[0012] [0104] [0105] lock information in the metadata for synchronization processing)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Rathke‘s distributed computing into Jiang, Haener and Doi’s invention as they are related to the same field endeavor of distributed computing. The motivation to combine these arts, as proposed above, at least because Rathke‘s distributed computing with lock information for synchronization processing help to provide more controlled distributed computing into Jiang, Haener and Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more controlled distributed computing with lock information would help to reduce synchronization overhead and improve performance while maintaining consistency for the emulation computation.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Doi US 2020/0218787, Haener et al. (Haener) US 2021/0374307 and Liang et al. (Liang) US 2021/0271477 as applied to claim 1, further in view of Zheng et al. (Zheng) US 2021/0399743
In regard to claim 16, Doi and Haener, Jiang disclose The quantum simulation apparatus of claim 1,
But Doi and Haener, Jiang fail to explicitly disclose “further comprising a quantum noise generator configured to inject a quantum error to which at least one of a quantum error application target quantum register defined by a user with respect to the quantum register, a quantum error occurrence probability, and a kind of a quantum error is applied.”
Zheng disclose further comprising a quantum noise generator configured to inject a quantum error to which at least one of a quantum error application target quantum register defined by a user with respect to the quantum register, a quantum error occurrence probability, and a kind of a quantum error is applied. ([0109] [0160]-[0182] noise model to generate data error, such as quantum gate noise, etc.)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Zheng‘s error generation in quantum computing into Jiang, Haener and Doi’s invention as they are related to the same field endeavor of quantum computing. The motivation to combine these arts, as proposed above, at least because Zheng‘s error generation in quantum computing help to provide more scenarios for the quantum simulation into Jiang, Haener and Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more scenarios for the quantum simulation with errors generation would help to improve performance of the quantum computing.
In regard to claim 17, Doi and Haener, Zheng, Jiang disclose The quantum simulation apparatus of claim 16,
Doi disclose the kind of the at least one quantum operation defined by the user. ([0029]-[0032] the user can define the quantum simulation operation)
But Doi and Haener, Jiang fail to explicitly disclose “wherein the quantum noise generator comprises a rule manager configured to manage the kind of the quantum error of at least one of a bit reversal error, a phase reversal error, and a measurement error, and is configured to inject the quantum error corresponding to the kind of the at least one quantum error.”
Zheng disclose wherein the quantum noise generator comprises a rule manager configured to manage the kind of the quantum error of at least one of a bit reversal error, a phase reversal error, and a measurement error, and is configured to inject the quantum error corresponding to the kind of the at least one quantum error. ([0108][0109] [0160]-[0182] noise model to generate data error based on the specific layout, such as measurement error, quantum gate noise, etc. and generate the error based on configuration which can be user configured corresponding quantum simulation operation.)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Zheng‘s error generation in quantum computing into Jiang, Haener and Doi’s invention as they are related to the same field endeavor of quantum computing. The motivation to combine these arts, as proposed above, at least because Zheng‘s error generation in quantum computing help to provide more scenarios for the quantum simulation into Jiang, Haener and Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more scenarios for the quantum simulation with errors generation would help to improve performance of the quantum computing.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Doi US 2020/0218787, Haener et al. (Haener) US 2021/0374307, and Liang et al. (Liang) US 2021/0271477 as applied to claim 1, further in view of Zheng et al. (Zheng) US 2021/0399743 and Vacon et al. (Vacon) US 11411658
In regard to claim 18, Doi and Haener, Zheng, Jiang disclose The quantum simulation apparatus of claim 16,
But Doi, and Haener, Zheng, Jiang fail to explicitly disclose “wherein the quantum noise generator comprises an error timing controller configured to control a time of the quantum error occurrence for injecting the quantum error into the quantum register based on a quantum error occurrence rate defined by the user and the quantum circuit state through monitoring of gate application statistics of the quantum register.”
Vacon disclose wherein the quantum noise generator comprises an error timing controller configured to control a time of the quantum error occurrence for injecting the quantum error into the quantum register based on a quantum error occurrence rate defined by the user and the quantum circuit state through monitoring of gate application statistics of the quantum register. (col. 24, line 42-col. 25, line 37, col. 48, line 23-col. 50, line-65, col. 52, line 62-col. 53, line 11 adjust a clock rate to ensure a desired error based on the quantum state information derived from vector and based on the user selection)
It would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made to incorporate Vacon‘s error generation in quantum computing into Jiang, Zheng, Haener and Doi’s invention as they are related to the same field endeavor of quantum computing. The motivation to combine these arts, as proposed above, at least because Vacon‘s error generation with a rate in quantum computing help to provide more scenarios for the quantum simulation into Jiang, Zheng, Haener and Doi’s system. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing data of the claimed invention was made that providing more scenarios for the quantum simulation with errors generation would help to improve performance of the quantum computing.
Response to Arguments
Applicant’s arguments with respect to claims 1-19 filed on 1/22/2026 have been considered but are moot because the arguments do not apply to the current rejection.
With respect to claims 1-19 rejections of 35 USC § 101, please see the rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
PATENT PUB. # PUB. DATE INVENTOR(S) TITLE
US 20210374593 A1 2021-12-02 Niroula et al.
ACCELERATED PATTERN MATCHING METHOD ON A QUANTUM COMPUTING SYSTEM
Niroula et al. disclose A method of determining a pattern in a sequence of bits using a quantum computing system includes setting a first register of a quantum processor in a superposition of a plurality of string index states, encoding a bit string in a second register of the quantum processor, encoding a bit pattern in a third register of the quantum processor, circularly shifting qubits of the second register conditioned on the first register, amplifying an amplitude of a state combined with the first register in which the circularly shifted qubits of the second register matches qubits of the third register, measuring an amplitude of the first register and determining a string index state of the plurality of string index states associated with the amplified state, and outputting, by use of a classical computer, a string index associated with the first register in the measured state… see abstract.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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XUYANG XIA
Primary Examiner
Art Unit 2143
/XUYANG XIA/Primary Examiner, Art Unit 2143