NON-FINAL OFFICE ACTION
This non-final office action addresses U.S. Application No. 17/869,610, which is a broadening reissue application of U.S. Application No. 16/410,917 (hereinafter the “917 Application"), entitled RECONFIGURABLE DICKSON STAR SWITCHED VOLTAGE REGULATOR, which issued as U.S. Patent No. 10,719,099 (hereinafter the “099 Patent").
The status of the claims is as follows:
Claims 1-19 are pending.
Claims 1-3 are rejected.
Claims 4 and 5 are object to.
Claims 6-19 are allowed.
I. REQUEST FOR CONTINUED EXAMINATION
A request for continued examination under 37 C.F.R. §1.114, including the fee set forth in 37 C.F.R. §1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 C.F.R. §1.114, and the fee set forth in 37 C.F.R. §1.17(e) has been timely paid, the finality of the final Office action mailed December 17, 2024 (hereinafter the “2024 Final”) has been withdrawn pursuant to 37 C.F.R. §1.114. Applicant's submission filed on February 18, 2025 (hereinafter the “Feb 2025 Amendment”) has been entered.
II. STATUS OF CLAIMS
The Feb 2025 Amendment is acknowledged. In the Feb 2025 Amendment, patent claims 1, 4-6 and 11 were amended, patent claims 2, 3, 7-10 and 12-19 were unchanged and previously added claims 20-31 were cancelled. Therefore, claims 1-19 are pending herein.
III. PRIORITY
Examiners acknowledge the Applicant’s claim that present application is a reissue application of the 917 Application, filed May 13, 2019, which is a continuation of U.S. Application No. 15/487,682, filed on April 14, 2017, now U.S. Patent No. 10,289,146. Examiners further acknowledge the claim of priority to U.S. Provisional Application No. 62/324,091, filed April 18, 2016. Therefore, Examiners find the earliest possible filing date for the claims is the date of this provisional application.
IV. CLAIM INTERPRETATION
After careful review of the original specification, the prosecution history, and unless expressly noted otherwise by the Examiners, the Examiners find that they are unable to locate any lexicographic definitions (either express or implied) with the required clarity, deliberateness, and precision with regard to pending and examined claims. Because the Examiners are unable to locate any lexicographic definitions with the required clarity, deliberateness, and precision, the Examiners conclude that Applicant is not his own lexicographer for the pending and examined claims. See MPEP §2111.01(IV).
The Examiners further find that because the pending and examined claims herein recite neither “step for” nor “means for” nor any substitute therefore, the examined claims fail Prong (A) as set forth in MPEP §2181(I). Because all examined claims fail Prong (A) as set forth in MPEP §2181(I), the Examiners conclude that all examined claims do not invoke 35 U.S.C. §112, 6th paragraph. See also Ex parte Miyazaki, 89 USPQ2d 1207, 1215-16 (B.P.A.I. 2008)(precedential)(where the Board did not invoke 35 U.S.C. § 112 6th paragraph because “means for” was not recited and because applicant still possessed an opportunity to amend the claims).
Because of the Examiners’ findings above that Applicant is not his own lexicographer and the pending and examined claims do not invoke 35 U.S.C. §112(f), the pending and examined claims will be given the broadest reasonable interpretation consistent with the specification since patentee has an opportunity to amend claims. See MPEP §2111, MPEP §2111.01 and In re Yamamoto et al., 222 USPQ 934 (Fed. Cir. 1984). Under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. See MPEP §2111.01(I). It is further noted it is improper to import claim limitations from the specification, i.e., a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment. See MPEP §2111.01(II).
V. CLAIM REJECTIONS – 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. §102 which forms the basis for all obviousness rejections set forth in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Anticipation Rejections Applying Barker
Claims 1-3 are rejected under 35 U.S.C. §102(a)(2) as being anticipated by U.S. Patent Application Publication No. 2016/0344286 to Carl Barker et al. (hereinafter “Barker”).
Regarding claim 1, Barker discloses:
A voltage regulator configured to receive a first voltage signal and
provide a final voltage signal based, at least in part, on the first voltage signal, the voltage regulator comprising:
See Barker FIGS. 3 and 4, reprinted below:
PNG
media_image1.png
798
501
media_image1.png
Greyscale
PNG
media_image2.png
556
260
media_image2.png
Greyscale
Barker FIG. 3 (annotated) Barker FIG. 4 (annotated)
See Barker Abstract “[a] DC to DC converter for converting voltage between two voltage levels is described.” See also Barker ¶0038 wherein “[t]he method may be a method of transferring power from the higher voltage terminals to the lower voltage terminals, or vice versa, or be capable of transferring power in both directions (i.e. the converter may be a step up, step down or bi-directional converter).”
an inductor, wherein a first terminal of the inductor comprises an input terminal configured to receive the first voltage signal, and a second terminal of the inductor comprises an output terminal configured to provide an intermediate voltage signal; and
See FIG. 3 above, inductor LHV at high input voltage HV.
a step-down regulator comprising an input terminal configured to receive the intermediate voltage signal from the output terminal of the inductor, comprising a switch matrix, a plurality of capacitors, and an output terminal, and configured to provide the final voltage signal, wherein the switch matrix in the step-down regulator is configured to alternate between a first configuration and a second configuration to arrange the plurality of capacitors in a first arrangement and a second arrangement, respectively, with a predetermined duty cycle, thereby also duty-cycling the inductor,
See FIGS. 3 and 4, step down regulator comprising switches 304c shown with capacitors 404 within clusters 302. Further see Barker ¶¶0036-0037:
[0036] Preferably, the steps are carried out in a condition of low, near zero or zero current flow. In such examples, the circuit may conveniently be a resonant circuit. The step of providing a plurality of capacitors in a series configuration connected to higher voltage terminals (i.e. step (i)), or else a step of providing a plurality of capacitors in a matrix configuration comprising at least two parallel branches, the branches comprising a series connection of at least two capacitors connected to lower voltage terminals (i.e. the state of the converter after step (iv)) may continue until current flow within the circuit ceases, at which point steps (ii) to (iv) and/or (v) to (vii) are carried out.
[0037] As will be appreciated, steps (i) to (vii) may be carried out cyclically, such that a connection to the higher and lower voltage terminals is made alternately and repeatedly. The method may start at step (i) or with the provision of a plurality of capacitors in a matrix configuration comprising at least two parallel branches, each branch comprising a series connection of at least two capacitors connected to a lower voltage bus (i.e. the state of the converter after step (iv)).
wherein the switch matrix comprises at least three switches that are connected in series between the input terminal of the step-down regulator and the output terminal of the step-down regulator,
See FIGS. 3 and 4 above, note identified 1st, 2nd and 3rd switches 304c provided in series within regulator.
wherein a first capacitor of the plurality of capacitors is connected to a connection between a first switch of the at least three switches and a second switch of the at least three switches,
See FIGS. 3 and 4 above, note first capacitor in identified 1st cluster is connected between the identified 1st switch and identified 2nd switch.
wherein a second capacitor of the plurality of capacitors is connected to a connection between the second switch and a third switch of the at least three switches, and
See FIGS. 3 and 4 above, note second capacitor in identified 2nd cluster is connected to a connection between the identified 2nd switch and identified 3rd switch.
wherein the first terminal of the inductor remains connected to the first voltage signal and the second terminal of the inductor remains connected to the input terminal of the step-down regulator throughout the duty-cycling of the inductor.
See FIGS. 3 and 4 above, note inductors LLV LHV are always connected during commutation cycles of the switches. Specifically, each of the inductors is connected to the input of the regulator comprising items 302, 304a, 304b, and 304c.
Regarding claim 2, Barker discloses the regulator of claim 1 as evidenced above, and further wherein
when the switch matrix is in a first configuration, the intermediate voltage signal is at a first voltage level, and when the switch matrix is in a second configuration, the intermediate voltage signal is at a second voltage level.
See FIGS. 3 and 4 and ¶¶0036-0038 quoted above wherein by connecting the capacitor in series or parallel, the output voltage levels would be different levels which are cycled back and forth to generate a stepped down output voltage.
Regarding claim 3, Barker discloses the regulator of claim 2 as evidenced above, and further wherein
the first voltage level is a first fractional multiple of the final voltage signal, and wherein the second voltage level is a second fractional multiple of the final voltage signal.
See FIGS. 3 and 4 and ¶¶0036-0038 quoted above wherein by connecting the capacitor in series or parallel, the output voltage levels would be different levels which are cycled back and forth to generate a stepped down output voltage.
VI. ALLOWABLE SUBJECT MATTER
Claims 6-19 are allowed. Regarding these claims, Examiners find the prior art of record herein does not disclose or teach “the first switch and the second switch are configured to alternately couple the first switched capacitor regulator and the second switched capacitor regulator at a second duty cycle” in the manner as recited in the claims and in combination with the other features of the claims.
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 4, Examiners find the prior art of record does not disclose or teach the fourth through seventh switches as connected as recited in the claims and in combination with the other features of the claim. Claim 5 is allowable based on its dependency to claim 4.
VII. EXAMINERS’ RESPONSES TO APPLICANT’S ARGUMENTS
Examiners have fully considered the arguments provide in the Feb 2025 Amendment. However, Examiners have withdrawn all objections and rejections outlined in the 2024 Final. Accordingly, the arguments provided in the Feb 2025 Amendment are generally moot. Nevertheless, in view of and in response to the substantial amendments to the claims, new grounds of objection and rejection are provided above.
VIII. PRIOR OR CONCURRENT PROCEEDINGS
Applicant is reminded of the obligation apprise the Office of any prior or concurrent proceedings in which the 099 Patent is or was involved, such as interferences or trials before the Patent Trial and Appeal Board, reissues, reexaminations, or litigations and the results of such proceedings.
IX. INFORMATION MATERIAL TO PATENTABILITY
Applicant is further reminded of the continuing obligation under 37 C.F.R. §1.56 to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
X. CONCLUSION
Claims 1-19 are pending.
Claims 1-3 are rejected.
Claims 4 and 5 are objected to.
Claims 6-19 are allowed.
The prior art made of record which is considered pertinent to Applicant’s disclosure is listed on the document titled ‘Notice of Reference Cited’ (“PTO-892”). Unless expressly noted otherwise by the Examiners, all documents listed on the PTO-892 are cited in their entirety.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to KENNETH WHITTINGTON whose telephone number is (571) 272-2264. The Examiner can normally be reached on 8:30am - 5:00pm, Monday - Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Andrew J. Fischer, SPE Art Unit 3992, can be reached at (571) 272-6779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-9900.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/KENNETH WHITTINGTON/Primary Examiner, Art Unit 3992
Conferees:
/MY TRANG TON/Primary Examiner, Art Unit 3992
/ANDREW J. FISCHER/Supervisory Patent Examiner, Art Unit 3992