DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed 09/08/2025.
Claims 1-5, 7-12, and 14-19 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-9, 13-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (“vCAT: Dynamic Cache Management using CAT Virtualization”) further in view of Hornung et al. Pub. No. US 2022/0292027 A1 (hereafter Hornung).
Regarding claim 1 Xu teaches a method of virtualized cache allocation for a virtualized computing system, comprising: providing, by a hypervisor for a virtual machine (VM), a virtual shared cache, the virtual shared cache backed by a physical shared cache of a processor (Page 211, Right Colum, paragraph 3, Line 1-19, CAT virtualization that makes use of physical partitions of memory that can be mapped to virtual partitions at the hypervisor and VM level); providing, by the hypervisor to the VM, a virtual service class and a virtual service class bit mask (Page 216, Left Column, paragraph 6, lines 1-5, VCPU has a virtual class of service register in a VM and includes a virtual bit mask register. Page 217, Right column, Paragraph 2, Lines 14-19, different VMs being used in performance evaluation are pinned to multiple vCPUs which are provided virtual COS register and virtual bitmap registers as described in implementation); mapping, by the hypervisor, the virtual service class to a physical service class of the processor; configuring, by the hypervisor, a service class register of the processor based on the mapping of the virtual service class to the physical service class (Page 216, Right Column, paragraph 3, lines 5-8, the hypervisor invokes the mapping procedure which updates the mapping of the virtual to physical mapping between VM and physical COS; Page 216, Right Column, paragraph 4, we extended the hypervisor to trap on this instruction and modify the physical COS registers of these VCPUs’ cores (based on the mapping Pi); Page 216, Left Column, paragraph 6, Lines 1-6, VM has virtual COS registers which include a bit mask and operation as a physical COS register); and. However, Xu fails to teach associating, by the hypervisor, a shift factor with the virtual service class bit mask with respect to physical service class bit mask of the processor, the hypervisor mapping bits of the virtual service class bit mask to locations of the physical service class bit mask offset by the shift factor; configuring, by the hypervisor, a service class register of the processor based on the mapping of the virtual service class to the physical service class; configuring, by the hypervisor, a service class bit mask register of the processor based on the mapping of the bits of the virtual service class bit mask to the locations of the physical service class bit mask offset by the shift factor.
In a similar field of endeavor Hornung teaches associating, by the hypervisor, a shift factor with the virtual service class bit mask with respect to a physical service class bit mask of the processor (Xu, Page 216, Right column, paragraph 4, Lines 6-18, hypervisor modifies the physical COS registers based on the mapping and can be extended to use other algorithms to decide allocation; Hornung, Paragraph 12, a system that allows for a variable width virtual device identifier for globally shared address spaces is described herein. For example, a host system (e.g., an operating system) may set parameters for determining whether an address (e.g., a virtual address) is associated with a memory device. The parameters may include a shift parameter indicating how to shift the virtual address, a mask parameter to mask bits of the shifted virtual address, and a device identifier of the memory device for the globally shared address space), the hypervisor mapping bits of the virtual service class bit mask (Hornung, Paragraph 60, Moreover, after determining the starting bit for determining the device identifier (e.g., based on a value represented by the shift bits 5:0), the global shared range check block 315 may determine a value represented by bits 17:8 of the Local_VID[0] register 415-a. As shown in FIG. 4, bits 17:8 of the Local_VID[0] register 415-a may be mask bits. The mask bits may indicate which address bits to use for determining the device identifier (e.g., the shifted address bits may be ANDed with the mask bits). Thus, the value of the shift bits may indicate a starting bit and the value of the mask bits may indicate a quantity of bits to use to determine the device identifier) to locations of the physical service class bit mask offset by the shift factor (Hornung, Paragraph 59, As shown in FIG. 4, the Local_VID[0] register 415-a may indicate that bits 5:0 of the table are shift bits. The shift bits may indicate the number (e.g., the quantity) of bits to shift the address to move the device identifier (e.g., the Device VID) to bit 0. That is, the virtual address may be shifted (e.g., right, dividing) by a value indicated by the shift bits [5:0]. For example, if the value of the shift bits is thirty (30), the virtual address may be shifted to the right by 30 bits, placing original bit 30 in the location of bit 0 of the shifted address. In other words, a value represented by the shift bits may indicate a starting bit to use for determining the device identifier); configuring, by the hypervisor, a service class bit mask register of the processor based on the mapping of the bits of the virtual service class bit mask to the locations of the physical service class bit mask offset by the shift factor (Hornung, Paragraph 61, Additionally or alternatively, the global shared range check block 315 may determine a value represented by bits 27:18 of the virtual address 305. As shown in FIG. 4, bits 27:18 of a received virtual address may be Local_VID bits. The Local_VID bits may indicate a value (e.g., device identifier) to compare with the value determined based on the shifted and masked bits from the virtual address 305. Accordingly, the global shared range check block 315 may compare a value represented by the Local_VID bits to the device identifier from the virtual address (e.g., based on shifting and masking the virtual address). If the value associated with the Local_VID bits matches the device identifier from the virtual address, the virtual address 305 is associated with the memory device, and a physical address corresponding to the virtual address 305 may subsequently be accessed (e.g., via local translation cache 330); Xu, Page 216, Right column, paragraph 4, Lines 6-18, hypervisor modifies the physical COS registers based on the mapping and can be extended to use other algorithms to decide allocation).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the shifting and masking of virtual addresses Hornung with the virtual service classes of Xu resulting in a system in which the hypervisor of Xu is able to shift and mask the virtual service classes and configure in accordance with the mapping. A person having ordinary skill in the art would have been motivated to make this combination for the purpose of improving the translation/comparison of addresses by efficiently manipulating the relevant portions of the addresses through the use of bitmasking and shifting and allowing for variable width identification for greater flexibility and extending address translation per-device thus reducing computation and increasing efficiency (Hornung ¶ [0012], [0059] – [0061]).
Regarding claim 2 Xu in view of Hornung further teaches the method of claim 1 (see above), wherein the step of configuring comprises: trapping, by the hypervisor, access to the service class bit mask register by the VM; and trapping, by the hypervisor, access to the service class register by the VM (Page 216, Right column, paragraph 4, Lines 3-7, hypervisor to trap on instructions to modify the COS registers).
Regarding claim 7 Xu in view of Hornung further teaches the method of claim 1, wherein the step of configuring comprises: paravirtualizing access to the service class bit mask register and the service class register by the VM (Page 214, Right Column, paragraph 3, lines 1-7, hypercall can be added to communicate either to the VM or bare hardware through virtual COS registers).
Regarding claim 8, this claim is a non-transitory computer readable medium claim having similar limitations as cited in the method claim 1. Thus, claim 8 is also rejected under the same rationale as addressed in the rejection of claim 1 above.
Regarding claim 9, this claim is a non-transitory computer readable medium claim having similar limitations as cited in the method claim 2. Thus, claim 9 is also rejected under the same rationale as addressed in the rejection of claim 2 above.
Regarding claim 14, Xu in view of Hornung further teaches the non-transitory computer readable medium of claim 8 (see above), wherein the physical shared cache comprises a physical last level cache (LLC) of the processor (Page 211, Right column, Lines 1-7, Focus of the paper is on access to last level shared cache).
Regarding claim 15, this claim is a virtualized computer system claim having similar limitations as cited in the method claim 1. Thus, claim 15 is also rejected under the same rationale as addressed in the rejection of claim 1 above.
Regarding claim 16, this claim is a virtualized computer system having similar limitations as cited in the method claim 2. Thus, claim 16 is also rejected under the same rationale as addressed in the rejection of claim 2 above.
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (“vCAT: Dynamic Cache Management using CAT Virtualization”) in view of Hornung et al. Pub. No. US 2022/0292027 A1 (hereafter Hornung) further in view of Vijayrao et al. (US 2015/0095577).
Regarding claim 3 Xu in view of Hornung teaches the method of claim 1 (see above). However, Xu in view of Hornung fails to teach determining, by the hypervisor, a size of the virtual shared cache for the VM based on a number of virtual central processing units (vCPUs) allocated to the VM.
In a similar field of endeavor Vijayrao teaches determining, by the hypervisor, a size of the virtual shared cache for the VM based on a number of virtual central processing units (vCPUs) allocated to the VM (Paragraph 20, The size of the shared cache is allocated based on the requirements of the processor and the number of processors changing will change the required size of the shared cache).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add determining, by the hypervisor, a size of the virtual shared cache for the VM based on a number of virtual central processing units (vCPUs) allocated to the VM as described in Vijayrao with Xu in view of Hornung because the determining of the size of the shared cache based on the requirements of a processor is a technique that can be applied to both physical and virtual processors when allocating the size of a shared cache.
Regarding claim 10, this claim is a non-transitory computer readable medium claim having similar limitations as cited in the method claim 3. Thus, claim 10 is also rejected under the same rationale as addressed in the rejection of claim 3 above.
Regarding claim 17, this claim is a virtualized computer system having similar limitations as cited in the method claim 3. Thus, claim 17 is also rejected under the same rationale as addressed in the rejection of claim 3 above.
Claims 4-5, 11-12, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (“vCAT: Dynamic Cache Management using CAT Virtualization”) in view of Hornung et al. Pub. No. US 2022/0292027 A1 (hereafter Hornung) in view of Vijayrao et al. (US 2015/0095577) further in view of Lu et al. (US 2018/0101486).
Regarding claim 4 Xu in view of Hornung in view of Vijayrao teaches the method of claim 3 (see above). However, Xu in view of Hornung in view of Vijayrao fails to teach placing, by the hypervisor, the virtual shared cache on the physical shared cache based on pinnings of the vCPUs to physical CPUs (pCPUs) of the processor.
In a similar field of endeavor Lu teaches teach placing, by the hypervisor, the virtual shared cache on the physical shared cache based on pinnings of the vCPUs to physical CPUs (pCPUs) of the processor (Paragraph 38, kernel scheduler selects a physical CPU in same proximity as the communicating virtual CPU to place the relevant context of the cache). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add placing, by the hypervisor, the virtual shared cache on the physical shared cache based on pinnings of the vCPUs to physical CPUs (pCPUs) of the processor as describe in Lu with Xu in view of Hornung in view of Vijayrao because it is optimal to place the virtual to the physical cache based on the virtual CPU to the physical CPU to reduce the chance of a miss or conflict occurring when communicating.
Regarding claim 5 Xu in view of Hornung in view of Vijayrao teaches the method of claim 3 (see above). However, Xu in view of Hornung in view of Vijayrao fails to teach placing, by the hypervisor, the virtual shared cache on the physical shared cache based on nonuniform memory access (NUMA) domains of the processor.
In a similar field of endeavor Lu teaches placing, by the hypervisor, the virtual shared cache on the physical shared cache based on nonuniform memory access (NUMA) domains of the processor (Paragraph 38, place relevant context in the same NUMA domain). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add placing, by the hypervisor, the virtual shared cache on the physical shared cache based on nonuniform memory access (NUMA) domains of the processor as describe in Lu with Xu in view of Hornung in view of Vijayrao because placing the cache based on the NUMA domain ensures the communicating parts or in the same area and be subjected to less potential contention when working.
Regarding claim 11, this claim is a non-transitory computer readable medium claim having similar limitations as cited in the method claim 4. Thus, claim 12 is also rejected under the same rationale as addressed in the rejection of claim 4 above.
Regarding claim 12, this claim is a non-transitory computer readable medium claim having similar limitations as cited in the method claim 5. Thus, claim 12 is also rejected under the same rationale as addressed in the rejection of claim 5 above.
Regarding claim 18, this claim is a virtualized computer system having similar limitations as cited in the method claim 4. Thus, claim 18 is also rejected under the same rationale as addressed in the rejection of claim 4 above.
Regarding claim 19, this claim is a virtualized computer system having similar limitations as cited in the method claim 5. Thus, claim 19 is also rejected under the same rationale as addressed in the rejection of claim 5 above.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197