Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6, 9 and 22-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farrington et al. (Farrington et al., “Helios: A Hybrid Electrical/Optical Switch Architecture for Modular Data Centers”, SIGCOMM' 10, ACM, 2010) in view of Hosseini et al. (U.S. Patent Application Pub. 2022/0413216 A1) and Lam et al. (U.S. Patent 11,099,338 B2).
Regarding claim 1, Farrington et al. teaches in FIG. 3 a system comprising: an electrical block including a plurality of electrical switches (Pod 0, Pod 1, Pod 2 and Pod 3) configured to route signals in an electrical domain; and an optical block including a plurality of optical switches (Core 1, Core 2, …, Core 5), wherein the plurality of optical switches are coupled to the plurality of electrical switches in the electrical block, and configured to route signals in an optical domain. The differences between Farrington et al. and the claimed invention are (a) Farrington et al. does not teach a substrate and multi-chip module (MCM) assembly, (b) a number of optical ports, (c) Farrington et al. does not teach routing electrical signals via electrical traces and routing optical signals via waveguides, and (d) wherein the optical block comprises at least one optical switch die and at least one transceiver die, and wherein the one or more waveguides connect the at least one optical switch die to the at least one transceiver die on the substrate.
Hosseini et al. teaches in FIG. 1A a system comprising a substrate 104, an electrical block 103 and an optical block 101 co-package together on the substrate. FIG. 1A also includes at least one optical switch die 101, and at least one transceiver die 102, and a number of optical ports 111. Hosseini et al. teaches in FIGs. 5A-5E multi-chip package (equivalent to multi-chip module of instant claim). Hosseini et al. further teaches in paragraph [0015] routing optical signal through integrated optical waveguides. One of ordinary skill in the art would have been motivated to combine the teaching of Hosseini et al. with the system of Farrington et al. because integrating chips on a common substrate reduces the size of the system and increases reliability. Farrington et al. also teaches on page 3, right col., first paragraph that integration reduces cost. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use multi-chip technology to mount the chips of the system of Farrington et al. on a common substrate, as taught by Hosseini et al.
The combination of Farrington et al. and Hosseini et al. further teaches wherein a configuration of the optical block and a configuration of the electrical block co-packaged together on the substrate (Hosseini et al. teaches in FIG. 1A co-packaging optical block and electrical block on a substrate) are based on the number of optical ports (Farrington et al. teaches in FIG. 3 that the number of the optical ports matches the number of electrical switches), wherein the configuration of the optical block is further based on a number of optical switches contained in the plurality of optical switches (Farrington et al. teaches in FIG. 3 and FIG. 4 that the space between the optical switches can be larger if there are fewer switches).
The combination of Farrington et al. and Hosseini et al. still fails to teach routing electrical signals via electrical traces. Lam et al. teaches in FIG. 1A a multi-chip module comprising a substrate 110, electrical traces 155 and waveguides 157. One of ordinary skill in the art would have been motivated to combine the teaching of Lam et al. with the modified system of Farrington et al. and Hosseini et al. because Lam et al. teaches the details of implementation that are missing from Farrington et al. and Hosseini et al. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use electrical traces for routing electrical signals and waveguides for routing optical signals, as taught by Lam et al., in the modified system of Farrington et al. and Hosseini et al.
Regarding claim 2, Hosseini et al. teaches in FIG. 1A optical ports 111 for the optical transceiver 102; an optical transceiver transmits and receives optical signals; therefore, the optical ports 111 comprise a number of optical input ports and a number of optical output ports. Hosseini et al. teaches in FIG. 1A double-headed arrows for the optical ports 111 also indicates that the ports include input ports and output ports.
Regarding claim 3, Hosseini et al. teaches in FIG. 1A transceiver tiles 102 mounted on the substrate and coupled with the electrical block.
Regarding claim 4, Hosseini et al. teaches in FIG. 1A that the transceivers and the double-headed arrows are one-to-one corresponding.
Regarding claim 5, Hosseini et al. teaches in FIG. 1A that the transceiver tile is part of the optical block.
Regarding claim 6, Farrington et al. teaches in the second paragraph of Section 4.1 FM4224 switch ASIC.
Regarding claim 9, Lam et al. teaches in FIG. 10A and col. 12, lines 64-65 silicon wafer as substrate; Hosseini et al. teaches in paragraph [0015] a plurality of optical transceivers and a plurality of optical waveguides for the connection between the optical switch and the transceivers.
Claim 22 is rejected based on the same reason for rejecting claim 1.
Regarding claims 23 and 25, Hosseini et al. teaches in FIG. 1A one or more optical transceiver tiles, wherein the one or more optical transceiver tiles are coupled with the optical switch 101 and the electronic IC die 103. Farrington et al. teaches in FIG. 3 a plurality of optical switches connected to one or more M-port Application Specific Integrated Circuits (ASICs) (Pod0 to Pod3 which are equivalent to the electronic IC of Hosseini et al.).
Regarding claim 24, Farrington et al. teaches in FIG. 3 four electrical switches that are coupled to the optical switches via optical transceivers.
Regarding claim 26, as discussed above in regard to claim 1, the configuration of the optical switches and the configurations of the electrical switches depend upon each other.
Regarding claim 27, Hosseini et al. teaches in FIG. 1A optical ports 111 wherein the one or more optical transceiver tiles 102 are connected to optical ports in the number of optical ports operating as optical input ports (the number of transceiver tiles and the number of input ports are the same, i.e., each transceiver has one input port).
Regarding claim 28, Hosseini et al. teaches in FIG. 1A optical ports 111 wherein the plurality of optical switches are connected to optical ports in the number of optical ports operating as optical output ports (the transceiver has a transmitter and a receiver; the transmitter transmits optical signal through the optical port; one transceiver is associated with one optical port).
Claim 29 is rejected based on the same reason for rejecting claim 1.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farrington et al., Hosseini et al. and Lam et al. as applied to claim 1-6, 9 and 22-29 above, and further in view of Jiang et al. (U.S. Patent Application Pub. 2021/0373236 A1).
Farrington et al., Hosseini et al. and Lam et al. have been discussed above in regard to claims 1-6, 9 and 22-29. The difference between Farrington et al., Hosseini et al. and Lam et al. and the claimed invention is that Farrington et al., Hosseini et al. and Lam et al. do not teach an optical Printed Circuit Board (PCB). Jiang et al. teaches in FIG. 1 a module comprising components that are mounted on a substrate. Jiang et al. teaches in paragraph [0005] that the substrate can be an optical printed circuit board. One of ordinary skill in the art would have been motivated to combine the teaching of Jiang et al. with the modified system of Farrington et al., Hosseini et al. and Lam et al. because an optical PCB provides waveguides for connecting optical ports of optical devices. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an optical PCB as substrate, as taught by Jiang et al., in the modified system of Farrington et al., Hosseini et al. and Lam et al.
Regarding claim 8, Jiang et al. teaches in FIG. 1 that the substrate is a planar substrate and that it contains optical waveguide circuit. Therefore, it is a planar lightwave circuit.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farrington et al., Hosseini et al. and Lam et al. as applied to claim 1-6, 9 and 22-29 above, and further in view of Chakravarty et al. (Chakravarty et al., “Hybrid material integration in silicon photonic integrated circuits”, Journal of Semiconductors, 2021).
Farrington et al., Hosseini et al. and Lam et al. have been discussed above in regard to claims 1-6, 9 and 22-29. The difference between Farrington et al., Hosseini et al. and Lam et al. and the claimed invention is that Farrington et al., Hosseini et al., and Lam et al. do not teach a silicon nitride low-loss waveguide layer that facilitates low-loss routing between on-chip transmitters and the optical block. Chakravarty et al. teaches hybrid photonic integrated circuits. Chakravarty et al. teaches in FIG. 7(a) silicon nitride waveguide layer. One of ordinary skill in the art would have been motivated to combine the teaching of Chakravarty et al. with the modified system of Farrington et al., Hosseini et al. and Lam et al. because silicon nitride waveguides have low propagation losses (see second paragraph of Introduction section). Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use silicon nitride waveguides, as taught by Chakravarty et al., in the modified system of Farrington et al., Hosseini et al. and Lam et al.
Regarding claim 11, Chakravarty et al. teaches hybrid photonic integrated circuits (see title).
Regarding claim 12, Chakravarty et al. teaches in FIG. 1 InP laser on a SiO2 (glass) chip.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farrington et al., Hosseini et al. and Lam et al. as applied to claims 1-6, 9 and 22-29 above, and further in view of Rathinasamy et al. (U.S. Patent 10,951,325 B1).
Farrington et al., Hosseini et al. and Lam et al. have been discussed above in regard to claims 1-6, 9 and 22-29. The difference between Farrington et al., Hosseini et al. and Lam et al. and the claimed invention is that Farrington et al., Hosseini et al. and Lam et al. do not teach that the substrate, the number of optical ports, the plurality of electrical switches, and the plurality of optical switches are provided on a modular chassis. Rathinasamy et al. teaches in FIG. 4 a modular chassis where modules can be inserted into or removed from the chassis. One of ordinary skill in the art would have been motivated to combine the teaching of Rathinasamy et al. with the modified system of Farrington et al., Hosseini et al. and Lam et al. because a modular chassis allows various modules to be mounted into a common chassis, connected via backplane, and to share common components such as power supply. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to put the modified system of Farrington et al., Hosseini et al. and Lam et al. in a module for mounting into a modular chassis, as taught by Rathinasamy et al.
Response to Arguments
Applicant's arguments filed 3 June 2026 have been fully considered but they are not persuasive.
The Applicant argues:
The independent claims recite features that are neither taught, suggested, nor described in the cited references, alone or in combination. In particular, independent claim 1 recites, inter alia, an electrical block including a plurality of electrical switches configured to route signals over the substrate in an electrical domain via one or more electrical traces. Claim 1 further recites, inter alia, an optical block including a plurality of optical switches, wherein the plurality of optical switches are coupled to the plurality of electrical switches in the electrical block, and configured to route signals over the substrate in an optical domain via one or more waveguides, wherein the plurality of electrical switches and the plurality of optical switches are co-packaged together on the substrate. Independent claim 1 further recites, inter alia, a configuration of the optical block and a configuration of the electrical block co-packaged together on the substrate are based on the number of optical ports, wherein the configuration of the optical block is further based on a number of optical switches contained in the plurality of optical switches, wherein the optical block comprises at least one optical switch die and at least one transceiver die, and wherein the one or more waveguides connect the at least one optical switch die to the at least one transceiver die on the substrate. Similar features are recited in independent claims 22 and 29. It is respectfully submitted that none of the cited references, alone or in combination, describe or suggest the features recited in the independent claims.
More specifically, the Office Action suggests that Farrington discloses an electrical block including a plurality of electrical switches and an optical block including a plurality of optical switches, as claimed. See Office Action mailed March 2, 2026 at page 3. The Office Action specifically references Figure 3 of Farrington as disclosing the above-noted features recited in the independent claims. Applicant cannot agree with this interpretation of Farrington. To the contrary, as shown below and as is made clear by Farrington, Figure 3 illustrates a prototype that "consists of 24 servers, one Glimmerglass 64-port optical circuit switch, three Fulcrum Monaco 24-port 10 GigE packet switches, and one Dell 48-port GigE packet switch for control traffic and out-of-band provisioning." See Farrington at Section 4.1.
Thus, as shown above and as described in Farrington with great specificity, the Glimmerglass element is a single optical switch. The cores within the Glimmerglass element cannot fairly be considered separate optical switches as suggested by the Office Action. Taking such an interpretation of Farrington directly contradicts the explicit teachings of Farrington. Thus, it is Applicant's position that Farrington fails to disclose an optical block as recited in the independent claims. It is also Applicant's position that Farrington fails to disclose an optical block and transceiver block co-packaged together on a substrate, as claimed. Applicant further submits that none of the cited references, including Farrington, disclose the concept of utilizing one or more waveguides to connect at least one optical switch die to at least one transceiver die on a substrate, in the manner claimed.
It is also Applicant's position that the other cited references do not overcome the above-noted shortcomings of Farrington. Indeed, Hosseini also fails to disclose many features of the independent claims, including those features highlighted above. More specifically, Hosseini also discloses exactly one optical switch (101) and one electronic IC (103). As can be seen in Fig. 1A of Hosseini reproduced below for convenience, Hosseini discloses an IC package having an optical die with single optical switch (101). The optical switch is disclosed to be coupled with one or more optical transceivers. The Examiner suggests that Hosseini discloses an electrical block (103) and an optical block (101) co-packaged together on a common substrate (104). See Office Action at page 3. Applicant's reading of Hosseini suggests that Hosseini discloses an optoelectronic package (100) which may include an optical switch (101), an optical transceiver chipset (102), and an electronic IC die (103), "any or all of which may be electronically coupled to the substrate (104)." See Hosseini para. [0035].
The argument is not persuasive. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). It is true that Farrington et al. alone does not teach implementing the system as a multi-chip module using co-packaged technology. However, Hosseini et al. teaches in FIGs. 5A-5E multi-chip package (equivalent to multi-chip module of instant claim) and Lam et al. teaches in FIG. 1A a multi-chip module comprising a substrate 110, electrical traces 155 and waveguides 157. Hosseini et al. teaches one optical switch 101. However, Hosseini et al. teaches in paragraph [0019] optical switches; furthermore it is obvious to duplicate the optical switch according to the scheme taught by FIG. 3 of Farrington et al. and the co-packaged technology to come up with the claimed invention.
The argument continues:
Applicant respectfully submits that Hosseini fails to disclose an optical block comprising a plurality of optical switches, as recited in the independent claims. Based on an understanding of the elements shown and described in FIG. 1A of Hosseini, Applicant further submits that Hosseini fails to disclose the use of waveguides as part of an optical block that further includes multiple optical switches that are further co-packaged with an electrical block including multiple electrical switches, as claimed. It is, therefore, clear that Hosseini fails to overcome the shortcomings of Farrington. Applicant further submits that Lam fails to overcome the shortcomings of Farrington and Hosseini. Indeed, Lam makes no mention of an optical block including a plurality of optical switches, as claimed. To the contrary, Lam only discloses an enclosed volume (120) having a single optical device (156). The embodiments depicted and described in Lam fail to disclose an optical block comprising a plurality of optical switches, as claimed.
The argument is not persuasive. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As discussed above, Hosseini et al. teaches in FIGs. 5A-5E multi-chip package (equivalent to multi-chip module of instant claim) and Lam et al. teaches in FIG. 1A a multi-chip module comprising a substrate 110, electrical traces 155 and waveguides 157. It is obvious to duplicate the optical switch according to the scheme taught by FIG. 3 of Farrington et al. and the co-packaged technology of Hosseini et al. to come up with the claimed invention.
The Applicant continues the argument:
Applicant further submits hat Jiang in combination with the other cited references, fails to disclose the features of dependent claims 7 and 8. For example, Jiang relates to a method of forming an optical interconnect between first and second photonic chips. See Jiang Abstract. There is absolutely no disclosure in Jiang of an optical block having a plurality of optical switches, an electrical block having a plurality of electrical switches, and/or the co-packaging of an optical block and electrical block, as claimed. In addition to this shortcoming, Applicant further submits that Jiang make no mention of a substrate (on which an optical block and electrical block are co-packaged) comprising an optical Planar Lightwave Circuit (PLC) as recited in claim 9. Indeed, the general disclosure of a printed circuit board does not qualify as a disclosure that a substrate, as recited in claim 1, may include an optical PLC, as recited in claim 8. Neither Jiang nor any other cited reference discloses the concept of an optical PLC, let alone utilizing an optical PLC as recited in claim 8.
The argument is not persuasive. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this case, the combination of Farrington et al., Hosseini et al. and Lam et al. teaches all the limitations of claim 1 which claims 7 and 8 depend upon. Furthermore the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
The argument continues:
Chakravarty also fails to overcome the shortcomings of the other cited references. More specifically, Chakravarty only appears to disclose the integration of III-V and ferroelectric materials to enhance functionality of silicon photonic integrated circuits (PICs). See Chakravarty Abstract. There is no disclosure in Chakravarty of an optical block, as claimed, let alone a silicon nitride low-loss waveguide layer that facilitates low-loss routing between on-chip transmitters and an optical block, as recited in claim 10. The general disclosure of a PIC in Chakravarty does not qualify as disclosing a silicon nitride low-loss waveguide layer that facilitates low-loss routing between on-chip transmitters and an optical block (having a plurality of optical switches), as claimed. To the extent that Chakravarty fails to disclose a plurality of optical switches, Applicant submits that Chakravarty fails to overcome the shortcomings of the other cited references and further fails to teach all features recited in claims 10, 11, or 12.
The argument is not persuasive. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In response to the argument that Chakravarty fails to teach all features recited in claims 10, 11, or 12, Chakravarty et al. teaches hybrid photonic integrated circuits. Chakravarty et al. teaches in FIG. 7(a) silicon nitride waveguide layer. One of ordinary skill in the art would have been motivated to combine the teaching of Chakravarty et al. with the modified system of Farrington et al., Hosseini et al. and Lam et al. because silicon nitride waveguides have low propagation losses (see second paragraph of Introduction section). Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use silicon nitride waveguides, as taught by Chakravarty et al., in the modified system of Farrington et al., Hosseini et al. and Lam et al.
The rest of the argument is just replication for the other dependent claims similar to those addressed above and lack persuasiveness.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHI K LI whose telephone number is (571)272-3031. The examiner can normally be reached M-F 6:53 a.m. -3:23 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Payne can be reached at 571 272-3024. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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skl4 July 2026
/SHI K LI/Primary Examiner, Art Unit 2635
Prosecution Insights