Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6, 9 and 22-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farrington et al. (Farrington et al., “Helios: A Hybrid Electrical/Optical Switch Architecture for Modular Data Centers”, SIGCOMM' 10, ACM, 2010) in view of Hosseini et al. (U.S. Patent Application Pub. 2022/0413216 A1) and Lam et al. (U.S. Patent 11,099,338 B2).
Regarding claim 1, Farrington et al. teaches in FIG. 3 a system comprising: an electrical block including a plurality of electrical switches (Pod 0, Pod 1, Pod 2 and Pod 3) configured to route signals in an electrical domain; and an optical block including a plurality of optical switches (Core 1, Core 2, …, Core 5), wherein each of the plurality of optical switches are coupled to each of the plurality of electrical switches in the electrical block, and configured to route signals in an optical domain. The differences between Farrington et al. and the claimed invention are (a) Farrington et al. does not teach a substrate and multi-chip module (MCM) assembly, (b) a number of optical ports, (c) Farrington et al. does not teach routing electrical signals via electrical traces and routing optical signals via waveguides, and (d) wherein the optical block comprises at least one optical switch die and at least one transceiver die, and wherein the one or more waveguides connect the at least one optical switch die to the at least one transceiver die on the substrate.
Hosseini et al. teaches in FIG. 1A a system comprising a substrate 104, an electrical block 103 and an optical block 101 co-package together on the substrate. FIG. 1A also includes at least one optical switch die 101, and at least one transceiver die 102, and a number of optical ports 111. Hosseini et al. teaches in FIGs. 5A-5E multi-chip package (equivalent to multi-chip module of instant claim). Hosseini et al. further teaches in paragraph [0015] routing optical signal through integrated optical waveguides. One of ordinary skill in the art would have been motivated to combine the teaching of Hosseini et al. with the system of Farrington et al. because integrating chips on a common substrate reduces the size of the system and increases reliability. Farrington et al. also teaches on page 3, right col., first paragraph that integration reduces cost. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use multi-chip technology to mount the chips of the system of Farrington et al. on a common substrate, as taught by Hosseini et al.
The combination of Farrington et al. and Hosseini et al. further teaches wherein a configuration of the optical block and a configuration of the electrical block co-packaged together on the substrate (Hosseini et al. teaches in FIG. 1A co-packaging optical block and electrical block on a substrate) are based on the number of optical ports (Farrington et al. teaches in FIG. 3 that the number of the optical ports matches the number of electrical switches), wherein the configuration of the optical block is further based on a number of optical switches contained in the plurality of optical switches (Farrington et al. teaches in FIG. 3 and FIG. 4 that the space between the optical switches can be larger if there are fewer switches).
The combination of Farrington et al. and Hosseini et al. still fails to teach routing electrical signals via electrical traces. Lam et al. teaches in FIG. 1A a multi-chip module comprising a substrate 110, electrical traces 155 and waveguides 157. One of ordinary skill in the art would have been motivated to combine the teaching of Lam et al. with the modified system of Farrington et al. and Hosseini et al. because Lam et al. teaches the details of implementation that are missing from Farrington et al. and Hosseini et al. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use electrical traces for routing electrical signals and waveguides for routing optical signals, as taught by Lam et al., in the modified system of Farrington et al. and Hosseini et al.
Regarding claim 2, Hosseini et al. teaches in FIG. 1A optical ports 111 for the optical transceiver 102; an optical transceiver transmits and receives optical signals; therefore, the optical ports 111 comprise a number of optical input ports and a number of optical output ports. Hosseini et al. teaches in FIG. 1A double-headed arrows for the optical ports 111 also indicates that the ports include input ports and output ports.
Regarding claim 3, Hosseini et al. teaches in FIG. 1A transceiver tiles 102 mounted on the substrate and coupled with the electrical block.
Regarding claim 4, Hosseini et al. teaches in FIG. 1A that the transceivers and the double-headed arrows are one-to-one corresponding.
Regarding claim 5, Hosseini et al. teaches in FIG. 1A that the transceiver tile is part of the optical block.
Regarding claim 6, Farrington et al. teaches in the second paragraph of Section 4.1 FM4224 switch ASIC.
Regarding claim 9, Lam et al. teaches in FIG. 10A and col. 12, lines 64-65 silicon wafer as substrate.
Claim 22 is rejected based on the same reason for rejecting claim 1.
Regarding claims 23 and 25, Hosseini et al. teaches in FIG. 1A one or more optical transceiver tiles, wherein the one or more optical transceiver tiles are coupled with the optical switch 101 and the electronic IC die 103. Farrington et al. teaches in FIG. 3 a plurality of optical switches connected to one or more M-port Application Specific Integrated Circuits (ASICs) (Pod0 to Pod3 which are equivalent to the electronic IC of Hosseini et al.).
Regarding claim 24, Farrington et al. teaches in FIG. 3 four electrical switches that are coupled to the optical switches via optical transceivers.
Regarding claim 26, as discussed above in regard to claim 1, the configuration of the optical switches and the configurations of the electrical switches depend upon each other.
Regarding claim 27, Hosseini et al. teaches in FIG. 1A optical ports 111 wherein the one or more optical transceiver tiles 102 are connected to optical ports in the number of optical ports operating as optical input ports (the number of transceiver tiles and the number of input ports are the same, i.e., each transceiver has one input port).
Regarding claim 28, Hosseini et al. teaches in FIG. 1A optical ports 111 wherein the plurality of optical switches are connected to optical ports in the number of optical ports operating as optical output ports (the transceiver has a transmitter and a receiver; the transmitter transmits optical signal through the optical port; one transceiver is associated with one optical port).
Claim 29 is rejected based on the same reason for rejecting claim 1.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farrington et al., Hosseini et al. and Lam et al. as applied to claims 1-6, 9 and 22-29 above, and further in view of Jiang et al. (U.S. Patent Application Pub. 2021/0373236 A1).
Farrington et al., Hosseini et al. and Lam et al. have been discussed above in regard to claims 1-6, 9 and 22-29. The difference between Farrington et al., Hosseini et al. and Lam et al. and the claimed invention is that Farrington et al., Hosseini et al. and Lam et al. do not teach an optical Printed Circuit Board (PCB). Jiang et al. teaches in FIG. 1 a module comprising components that are mounted on a substrate. Jiang et al. teaches in paragraph [0005] that the substrate can be an optical printed circuit board. One of ordinary skill in the art would have been motivated to combine the teaching of Jiang et al. with the modified system of Farrington et al., Hosseini et al. and Lam et al. because an optical PCB provides waveguides for connecting optical ports of optical devices. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an optical PCB as substrate, as taught by Jiang et al., in the modified system of Farrington et al., Hosseini et al. and Lam et al.
Regarding claim 8, Jiang et al. teaches in FIG. 1 that the substrate is a planar substrate and that it contains optical waveguide circuit. Therefore, it is a planar lightwave circuit.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farrington et al., Hosseini et al. and Lam et al. as applied to claim 1-6, 9 and 22-29 above, and further in view of Chakravarty et al. (Chakravarty et al., “Hybrid material integration in silicon photonic integrated circuits”, Journal of Semiconductors, 2021).
Farrington et al., Hosseini et al. and Lam et al. have been discussed above in regard to claims 1-6, 9 and 22-29. The difference between Farrington et al., Hosseini et al. and Lam et al. and the claimed invention is that Farrington et al., Hosseini et al., and Lam et al. do not teach a silicon nitride low-loss waveguide layer that facilitates low-loss routing between on-chip transmitters and the optical block. Chakravarty et al. teaches hybrid photonic integrated circuits. Chakravarty et al. teaches in FIG. 7(a) silicon nitride waveguide layer. One of ordinary skill in the art would have been motivated to combine the teaching of Chakravarty et al. with the modified system of Farrington et al., Hosseini et al. and Lam et al. because silicon nitride waveguides have low propagation losses (see second paragraph of Introduction section). Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use silicon nitride waveguides, as taught by Chakravarty et al., in the modified system of Farrington et al., Hosseini et al. and Lam et al.
Regarding claim 11, Chakravarty et al. teaches hybrid photonic integrated circuits (see title).
Regarding claim 12, Chakravarty et al. teaches in FIG. 1 InP laser on a SiO2 (glass) chip.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farrington et al., Hosseini et al. and Lam et al. as applied to claims 1-6, 9 and 22-29 above, and further in view of Rathinasamy et al. (U.S. Patent 10,951,325 B1).
Farrington et al., Hosseini et al. and Lam et al. have been discussed above in regard to claims 1-6, 9 and 22-29. The difference between Farrington et al., Hosseini et al. and Lam et al. and the claimed invention is that Farrington et al., Hosseini et al. and Lam et al. do not teach that the substrate, the number of optical ports, the plurality of electrical switches, and the plurality of optical switches are provided on a modular chassis. Rathinasamy et al. teaches in FIG. 4 a modular chassis where modules can be inserted into or removed from the chassis. One of ordinary skill in the art would have been motivated to combine the teaching of Rathinasamy et al. with the modified system of Farrington et al., Hosseini et al. and Lam et al. because a modular chassis allows various modules to be mounted into a common chassis, connected via backplane, and to share common components such as power supply. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to put the modified system of Farrington et al., Hosseini et al. and Lam et al. in a module for mounting into a modular chassis, as taught by Rathinasamy et al.
Response to Arguments
Applicant's arguments filed 21 January 2026 have been fully considered but they are not persuasive.
The Applicant argues:
More specifically, the Office Action admits that neither Farrington, Meng, Janta- Polczynski, nor Ballani disclose features related to routing electrical signals via electrical traces and routing optical signals via waveguides. See Office Action mailed October 15, 2025 at page 4. Applicant agrees with this interpretation of the cited references. Applicant further submits that none of the cited references disclose the concept of utilizing one or more waveguides to connect at least one optical switch die to at least one transceiver die on a substrate, in the manner claimed.
The Office Action, however, argues that Lam overcomes the shortcomings of the other references and "teaches the details of implementation that are missing" from the other references. See Office Action at page 5. The Office Action specifically points to Fig. 1A of Lam (reproduced below) and argues that "it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use electrical traces for routing electrical signals and waveguides for routing optical signals, as taught by Lam et al., in the modified system of Farrington et al., Meng et al., Janta-Polczynski et al. and Ballani et al." See Office Action at page 5. Applicant cannot agree with this interpretation of Lam.
The argument is not persuasive because it amounts to a general allegation that the reference does not teach the limitation without specifically pointing out how the language of the claims patentably distinguishes them from the reference.
The argument continues:
As noted above, Applicant has amended the independent claims to clarify further differences between the cited references and the present application. Specifically, the independent claims have been amended to recite that the optical block comprises at least one optical switch die and at least one transceiver die, and wherein the one or more waveguides connect the at least one optical switch die to the at least one transceiver die on the substrate. There is no cited reference, alone or in combination, that discloses such features.
The argument is not persuasive. FIG. 1A of Hosseini et al. includes at least one optical switch die 101, and at least one transceiver die 102, and a number of optical ports 111.
The Applicant's argument in regard to Ballani et al. is moot because the new ground of rejection does not rely on Ballani et al.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHI K LI whose telephone number is (571)272-3031. The examiner can normally be reached M-F 6:53 a.m.-3:23 p.m.
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skl25 February 2026
/SHI K LI/Primary Examiner, Art Unit 2635