DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/16/2025 has been entered.
Response to Amendment
Examiner acknowledges the amendments made to claim 1. Claims 1-5 and 7 stand as cancelled. No new claims have been added.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,6 and 8-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The previous rejection of claims 1,6 and 8-11 have been withdrawn in light of the amendment made to claim 1.
Claim Interpretation
Examiner notes that the interpretation of the term “wide width region” as stated in claim 1 is understood to be that the term “wide width region” is used as a label for a specific region of the electric resistance layer in which the region has a width wider than a first region of the electric resistance layer as disclosed on page 14 of the specification of the claimed application and shown in figure 3 of the claimed application with the “wide width region” (15b2) and “narrow width region” (15b1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1,6,8,10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko (US 20130003762 A1) in view of Qian et al. (hereinafter Qian) (US 20160282557 A1) and further in view of Pezeshki et al. (hereinafter Pezeshki) (US 20020090011 A1) and Treese et al. (hereinafter Treese) (US 20170194763 A1)
Regarding claim 1, Kaneko discloses
An optical semiconductor device [Fig. 3B] comprising:
a base [1 Fig. 3B] including a base surface [top of 1 Fig. 3B]; (Para. [0022])
a mesa [mesa between grooves 40 Fig. 3B] (Para. [0030]) protruding from the base surface [top of 1 Fig. 3B] in a first direction intersecting the base surface [extends vertically from top of substrate 1] (Para. [0022]) and extending along the base surface [top of 1 Fig. 3B] [into the page Fig. 3B], the base surface [top of 1 Fig. 3B] being along a second direction [into the page Fig. 3B];
an optical waveguide layer [32] (Para. [0028]) provided inside the mesa [inside mesa Fig. 3B] or provided inside the base so as to have a region at least overlapping with the mesa in the first direction;
an electric resistance layer [10] including a first region provided on the mesa [10 on mesa in Fig. 3B] (Para. [0041]), and
a wiring layer [11] including a second region [portion of 11 over 10 Fig. 1A] electrically connected (Para. [0030]) to the electric resistance layer [10] and configured to partially cover the first region [11 shown to cover 10 in Fig. 1A and Fig. 3B]
a second extending portion [portion of 11 extending from 10 to pad portion] (See Figs. 1A and 2A), the second extending portion extending from the second region [portion of 11 over 10 Fig. 1A] in a third direction [left and right Fig. 3, vertically Figs. 1A and 2A] intersecting the first direction [vertically Fig. 3] and the second direction [into page Fig. 3]
a laminated portion [left side stack of 1,1a,22 and 9 under 11 Fig. 3B] (Paras. [0027,0041]) located away from the mesa [mesa between grooves 40 Fig. 3B] in the third direction [left and right Fig. 3b] and including a plurality of semiconductor layers [left side stack of 1,1a,22 and 9 under 11] (Paras. [0027,0041]) laminated in the first direction [vertically Fig. 3B], wherein
a trench [40 Fig. 3B] (Para. [0041]) is provided between the mesa [mesa between grooves 40 Fig. 3B] and the laminated portion [left side stack of 1,1a,22 and 9 under 11],
the second extending portion [portion of 11 extending from 10 to pad portion] (See Figs. 1A and 2A) provided from a top surface of the mesa [above 10 Fig. 3] toward a top surface of the laminated portion [left side stack of 1,1a,22 and 9 under 11 Fig. 3B] (Paras. [0027,0041]) so as to be laid across the trench [40] and away from a bottom of the trench [40] (Para. [0030])
Examiner notes that in lines 6-8 of claim 3, the alternative limitation of, “an optical waveguide layer provided inside the mesa or provided inside the base so as to have a region at least overlapping with the mesa in the first direction”, must only meet one portion of the limitation or the other to be considered sufficient of meeting the claim limitation. For the purposes of examination, the limitation will be understood to be “an optical waveguide layer provided inside the mesa” as shown in Kaneko above.
Kaneko fails to disclose,
a first extending portion extending from the first region in a third direction intersecting the first direction and the second direction
the second extending portion configured to at least partially cover the first extending portion,
a connecting region electrically connected to wiring is provided at a position included in the second extending portion, the position overlapping with the first extending portion on the top surface of the laminated portion, and
a first edge of the first extending portion and a second edge of the second extending portion overlap with each other.
the first extending portion and the second extending portion are overlapped with each other and are provided from a top surface of the mesa toward a top surface of the laminated portion so as to be laid across the trench and away from a bottom of the trench
the second extending portion has the same shape as the first extending portion in the electric resistance layer when viewed from the first direction,
the first extending portion and the second extending portion are in contact with each other across their entire face and,
the wiring layer is not laid across edges of the electric resistance layer in a portion of the wiring layer from its second region that partially covers the first region included in the electric resistance layer to a wide width region of the electric resistance layer that is electrically connected to the wiring
Qian discloses,
a first extending portion [portion of 60 extending under 62] (See Figs. 7M,7N and 7O) (Para. [0093]) extending from the first region [portion of 60 on 22] (See Fig. 7L) (Para. [0073]) in a third direction [vertically Fig. 7O) (Para. [0093])
a second extending portion [portion of 62 extending to 60 Fig. 7O] (Para. 0093]) configured to at least partially cover the first extending portion [portion of 60 extending under 62 Fig. 7N and 7O] (Para. [0093]),
the first extending portion [portion of 60 extending under 62] (See Figs. 7M,7N and 7O) (Para. [0093]) and the second extending portion [portion of 62 extending to 60 Fig. 7O] (Para. 0093]) are overlapped with each other [See Fig. 7N]
the second extending portion [portion of 62 extending to 60 Fig. 7O] has the same shape [rectangular shape Figs. 7N and 7O] as the first extending portion [portion of 60 extending under 62] (See Figs. 7M,7N and 7O) in the electric resistance layer when viewed from the first direction [viewed from above Fig. 7O],
the wiring layer [62 Fig. 7N] is not laid across edges of the electric resistance layer [60 Fig. 7N] in a portion of the wiring layer from its second region that partially covers the first region included in the electric resistance layer to a wide width region of the electric resistance layer that is electrically connected to the wiring [portion of 62 over 60 between square pad area and bottom portion of 62 Fig. 7O] (Para. [0073])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the structure of the extended wiring layer formed over the extended electric resistance layer as shown in Qian with the wiring and electric resistance layers of Kaneko for the purpose of a simplified method of fabrication with efficient device heating. (Qian Para. [0078])
Examiner notes when the electric resistance layer extending beneath the wiring layer as shown in Qian is implemented into Kaneko, the limitation of ,the first extending portion [Qian portion of 60 extending under 62] (See Figs. 7M,7N and 7O) (Para. [0093]) and the second extending portion [Qian portion of 62 extending to 60 Fig. 7O] (Para. 0093]) are overlapped with each other [Qian, See Fig. 7N] and are provided from a top surface of the mesa [Kaneko [mesa between grooves 40 Fig. 3B] (Para. [0030]) toward a top surface of the laminated portion [Kaneko left side stack of 1,1a,22 and 9 under 11 Fig. 3B] (Paras. [0027,0041]) so as to be laid across the trench [Kaneko 40 Fig. 3] and away from a bottom of the trench [Kaneko 40 Fig. 3] (Para. [0030])
Kaneko in view of Qian fails to disclose,
a connecting region electrically connected to wiring is provided at a position included in the second extending portion, the position overlapping with the first extending portion on the top surface of the laminated portion, and
a first edge of the first extending portion and a second edge of the second extending portion overlap with each other, and
the first extending portion and the second extending portion are in contact with each other across their entire face
Pezeshki discloses in Fig. 2,
a connection region [region connection 1609 to 1601] (Para. [0027]) electrically connected to wiring [1609] (Para. [0027]) provided at a position included in an extending portion of an electrical connection layer [1601] (Para. [0027])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a connection region on an extended portion of a wiring layer away from the lasing ridge as shown in Pezeshki on the wiring layer of Kaneko in view of Qian for the purpose of providing external electrical connection to the device to resistively heat the lasing stripe. (Pezeshki Para. [0029])
Kaneko in view of Qian and Pezeshki fails to disclose,
a first edge of the first extending portion and a second edge of the second extending portion overlap with each other, and
the first extending portion and the second extending portion are in contact with each other across their entire face
Treese discloses,
a first edge [edge of 204 in 110 Fig. 2] (Para. [0035]) of a first extending portion [portion of 110 extending to 204 Fig. 2] (Para. [0035]) and a second edge [edge of 118 in 114 Fig.4 (See Fig. 1)] (Para. [0038])of a second extending portion [portion of 114 extending to 118 Fig. 4] overlap with each other [See Figs. 1, 2 and 4] (Para. [0038]) and,
the first extending portion [portion of 110 extending to 204 Fig. 2] and the second extending portion [portion of 114 extending to 118 Fig. 4] are in contact with each other across their entire face (Para. [0038])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement first and second extending portions sharing the same shape overlapping with each other as shown in Treese with the first and second extending portions in the modified device of Kaneko for the purpose of ensuring electrical isolation of the desired contact structure. (Treese Para. [0038])
Regarding claim 6, Kaneko in view of Qian, Pezeshki and Treese discloses the device outlined in the rejection of claim 1 above but fails to disclose,
wherein electric resistivity of the electric resistance layer is larger than electric resistivity of the wiring layer .
Qian discloses in Figure 4C,
an electric resistance layer [60] (Para. [0070]) with a higher resistance than an overlying wiring layer [62] (Para. [0070])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the electric resistance layer having a higher electric resistivity than the wiring layer of Kaneko as shown in Qian for the purpose of reducing generation of heat by the overlying conductors. (Qian Para. [0070])
Regarding claim 8, Kaneko in view of Qian, Pezeshki and Treese as applied to claim 1 above further discloses in Kaneko,
further comprising a high thermal resistance layer [1a Fig. 3B] (Para. [0032]) having thermal conductivity lower than thermal conductivity exhibited in a region adjacent [cladding layers 2 and 6] (Para. [0032]) to the optical waveguide layer [32 Fig. 3B] (Para. [0028]).
Regarding claim 10, Kaneko in view of Qian, Pezeshki and Treese as applied to claim 8 above further discloses in Kaneko,
wherein the high thermal resistance layer [1a Fig. 3B] is formed of a semiconductor material (Para. [0032]).
Regarding claim 11, Kaneko in view of Qian, Pezeshki and Treese as applied to claim 1 above further discloses in Kaneko,
An integrated semiconductor laser device [100 Fig. 1A] comprising the optical semiconductor device according to claim 1 [plurality of mesas and heater portions shown in Fig. 1A]. (Para. [0022])
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable Kaneko in view of Qian, Pezeshki and Treese as applied to claim 1 above, and further in view of Kaneko et al. (US 20180212400 A1).
Regarding claim 9, Kaneko in view of Qian, Pezeshki and Treese discloses the device outlined in the rejection of claim 1 above but fails to disclose,
wherein the high thermal resistance layer is an air gap.
Kaneko et al. discloses,
Wherein the high thermal resistance layer [8 Fig. 5D] is an air gap (Para. [0043,0044]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the high thermal resistance layer as an air gap as disclosed in Kaneko et al. into the device of Kaneko in view of Qian, Pezeshki and Treese for the purpose of thermally isolating the waveguide layer from the substrate. (Kaneko et al. Para. [0044])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Examiner particularly notes (US 20110075693 A1) which discloses a mesa structure with a heater structure on the mesa structure with a contact portion extending over a trench to a laminated portion.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
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/H.J.N./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828