Detailed Action
This Office Action is in response to the remarks entered on 07/15/2026. Amended claims 1-5 have been entered. New claim 6 has been entered. Claims 1-6 are presently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2021-130005, filed on 08/06/2021.
Claim Objections
Claim 1 is objected to because of the following informalities: “at least one processor; and memory storing …” in line 3 should read “at least one processor; and a memory storing …”. Appropriate correction is required.
Claims 2-3 depend from claim 1 and are objected to for the same reasons.
Claim Rejections - 35 USC § 101
Amended claim 1 has been entered. 35 U.S.C. 101 rejections have been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Davies et al. (US 20180174026, hereinafter ‘Davies’).
Regarding claim 1, Davies teaches:
A computation apparatus, comprising: at least one processor; and memory storing a spiking neuron model and instructions, wherein the instructions, when executed by the at least one processor, cause the spiking neural network to: ([Davies, 0033-0034] and [0195] collectively disclose that the apparatus is implemented using a neuromorphic processor and a memory which stores the spiking neural network)
vary, for each of a plurality of time intervals, a membrane potential based on an input condition of a signal in the time interval; ([Davies, 0067] On each synchronization time step T, the Vm membrane potential state read from SOMA_STATE 332B is updated based upon a corresponding accumulated dendrite value)
detect a timing at which the membrane potential attains a prescribed threshold value; and ([Davies, 0067] On each synchronization time step T, the Vm membrane potential state read from SOMA_STATE 332B is updated based upon a corresponding accumulated dendrite value. If Vm membrane potential state exceeds the threshold activation level value in an upward direction, then the soma produces an outgoing spike event passed to the AXON_MAP 334 at time step T+D_axon. The time T is the detected timestep and the time step T+D_axon is the timestep + delay. The definition of ‘time step’ is ‘the interval between two times’)
output a signal at a timing that is within a first time interval and that is in accordance with the timing at which the membrane potential attains the prescribed threshold value within a second time interval, the first time interval being included in the plurality of time intervals, the second time interval being included in the plurality of time intervals and being a time interval further in past than the first time interval. ([Davies, 0067] If Vm membrane potential state exceeds the threshold activation level value in an upward direction, then the soma produces an outgoing spike event (i.e., output signal) passed to the AXON_MAP 334 at time step T+D_axon. The time step T is the second time step at which the membrane exceeds the threshold, and T+D_axon is the first time step for outputting the spike. The definition of ‘time step’ is ‘the interval between two times’)
Regarding claim 4, Davies teaches:
A computation method comprising: ([Davies, 0033-0034] and [0037] disclose the computation method that utilize the spiking neural network)
Claim 4 is a method claim which implements the same features as the apparatus claim 1, and is rejected for at least the same reasons.
Regarding claim 5, Davies teaches:
A non-transitory recording medium that causes a programmable apparatus to execute: ([Davies, 0033-0034] and [0195] collectively disclose that the apparatus is implemented using a neuromorphic processor and a memory which stores the spiking neural network)
Claim 5 is a non-transitory recording medium claim which implements the same features as the apparatus claim 1, and is rejected for at least the same reasons.
Regarding claim 6, Davies teaches:
The computation apparatus according to claim 1,
wherein the first time interval is a time interval in which the neuron model outputs a spike signal, and ([Davies, 0067] If Vm membrane potential state exceeds the threshold activation level value in an upward direction, then the soma produces an outgoing spike event (i.e., output signal) passed to the AXON_MAP 334 at time T+D_axon. The time T is the detected timing and D_axon is the delay.
[Davies, 0058, 0060 and 0119] discloses that the spikes are sent based on the sequential offsets to the base index of the destination neuron population. The delay offset is set from 1 to D_MAX, which indicates that the spike is sent with a delay of 1 … D_MAX, or after the time period for inputting the data that cause the spike. The total neurotransmitter amount scheduled for servicing at time step T+D (i.e., first time interval, Delay + occurrence timing T). The event timing T amounts to the second time interval)
wherein the second time interval is a time interval in which the neuron model receives a spike signal input that is to serve as a basis for determining an output timing of the spike signal in the first time interval. ([Davies, 0067] If Vm membrane potential state exceeds the threshold activation level value in an upward direction, then the soma produces an outgoing spike event (i.e., output signal) passed to the AXON_MAP 334 at time step T+D_axon. The time T is the second time step and T+D_axon is the first time step for outputting the spike signal)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Davies in view of Rhodes et al. (Rhodes et al, “Real-time cortical simulation on neuromorphic hardware”, 2019, hereinafter ‘Rhodes’).
Regarding claim 2, Davies teaches:
The computation apparatus according to claim 1, wherein the spiking neuron model comprises at which the membrane potential attains the prescribed threshold value ([Davies, 0067] On each synchronization time step T, the Vm membrane potential state read from SOMA_STATE 332B is updated based upon a corresponding accumulated dendrite value. If Vm membrane potential state exceeds the threshold activation level value in an upward direction, then the soma produces an outgoing spike event passed to the AXON_MAP 334 at time T+D_axon. The time step T is the second time step and T+D_axon is the first time step for outputting the spike signal. [Davies, Fig. 22, 0167 and 0173] discloses that the soma has a timer, and the timer determines the delay of the output signal (i.e., refractory time and axon delay) )
However, Davies does not specifically disclose:
wherein the spiking neuron model comprises two timers that determine the timing at which the signal to be output
wherein the spiking neuron model switches the two timers for each of the plurality of time intervals.
Rhodes teaches:
wherein the spiking neuron model comprises two timers that determine the timing at which the signal to be output ([Rhodes, page 11, line 13 – page 12, line 27], [page 10, Figure 5] and [page 11, Figure 6] discloses that Neuron core, Poisson core, and Synapse cores has its own timer callback (i.e., more than two timers) and Poisson core timer callback occurs approximately mid-way through the timer period to avoid SDRAM contention with reads/writes by other cores in the ensemble, which indicates that the timers are being switched for each of the time intervals. The signals are output to synaptic input buffers as shown in the Figure 5)
wherein the spiking neuron model switches the two timers for each of the plurality of time intervals. ([Rhodes, page 11, line 13 – page 12, line 27], [page 10, Figure 5] and [page 11, Figure 6] discloses that the Poisson core timer callback occurs approximately mid-way through the timer period to avoid SDRAM contention with reads/writes by other cores in the ensemble, which indicates that the timers are being switched for each of the time intervals. The signals are output to synaptic input buffers as shown in the Figure 5)
Before the effective filing date of the invention to a person of ordinary skill in the art, it would have been obvious, having the teachings of Davies and Rhodes to use a method of utilizing two timers and switching timers for each of the plurality of time intervals of Rhodes to implement the spiking neural network system of Davies. The suggestion and/or motivation is intended to improve efficiency of system by avoiding memory contentions caused by other cores in the ensemble.
Regarding claim 3, Davies teaches:
The computation apparatus according to claim 2, wherein the spiking neuron model comprises: ([Davies, 0033-0034] and [0195] collectively disclose that the apparatus is implemented using a neuromorphic processor and a memory which stores the spiking neural network)
a first spiking neuron model that varies the membrane potential and detects the timing at which the membrane potential attains the prescribed threshold value; and ([Davies, 0067] On each synchronization time step T, the Vm membrane potential state read from SOMA_STATE 332B is updated based upon a corresponding accumulated dendrite value. If Vm membrane potential state exceeds the threshold activation level value in an upward direction, then the soma produces an outgoing spike event passed to the AXON_MAP 334 at time step T+D_axon. The time T is the second time step and T+D_axon is the first time step.
[Davies, 0119 and Fig. 14] discloses the SYNAPSE_MAP 1410 (i.e., which receives the spike payload from the first spiking neuron model) transmitting the spike to DENDRITE ACCUM 316 and SOMA 330. [Davies, 0076] further discloses that the soma configuration receives number of detected spikes
s
i
[
t
]
for time step t at synapse i)
two second spiking neuron models that comprise [Davies, Fig. 22, 0167 and 0173] discloses that the soma has a timer, and the timer determines the delay of the output signal (i.e., refractory time and axon delay). [Davies, 0119 and Fig. 14] discloses transmitting the index to the dendrite accumulator 316 (i.e., the 1st second spiking neuron model) and SOMA 330 (i.e., the 2nd second spiking neuron model). [Davies, 0237 and 0243] The dendrite accumulator comprises a weighting array, and the soma state memory comprises the neuron’s present activation state level. These paragraphs indicate the soma and the dendrite accumulator are spiking neuron models)
wherein, when the first spiking neuron model detects the timing at which the membrane potential attains the prescribed threshold value, the first spiking neuron model outputs the signal to one of the two second spiking neuron models, and ([Davies, 0067-0068] and [0183] shows that the SOMA (AXON_CFG, See Fig. 3) outputs spike payload determined based on the threshold, and [Davies, 0119 and Fig. 14] discloses receiving the spike payload from the SOMA and transmitting the index to the dendrite accumulator 316 (i.e., the 1st second spiking neuron model) and SOMA 330 (i.e., the 2nd second spiking neuron model). [Davies, 0237 and 0243] The dendrite accumulator comprises a weighting array, and the soma state memory comprises the neuron’s present activation state level. These paragraphs indicate the soma and the dendrite accumulator are spiking neuron models)
wherein is to be output to be a timing that is within the first time interval and that is based on a timing that is a prescribed time period after a timing at which the signal is received from the first spiking neuron model in the second time interval. ([Davies, 0067] On each synchronization time step T, the Vm membrane potential state read from SOMA_STATE 332B is updated based upon a corresponding accumulated dendrite value. If Vm membrane potential state exceeds the threshold activation level value in an upward direction, then the soma produces an outgoing spike event passed to the AXON_MAP 334 at time step T+D_axon. The time T is the second time step and T+D_axon is the first time step. [Davies, Fig. 22, 0167 and 0173] discloses that the soma has a timer, and the timer determines the delay of the output signal (i.e., refractory time and axon delay))
However, Davies does not specifically disclose:
two second spiking neuron models that comprise the two timers, respectively, and output the signal
wherein each timer determines the timing at which the signal is to be output
Rhodes teaches:
two second spiking neuron models that comprise the two timers, respectively, and output the signal ([Rhodes, page 11, line 13 – page 12, line 27], [page 10, Figure 5] and [page 11, Figure 6] discloses that Neuron core, Poisson core, and Synapse cores has its own timer callback (i.e., more than two timers) and Poisson core timer callback occurs approximately mid-way through the timer period to avoid SDRAM contention with reads/writes by other cores in the ensemble, which indicates that the timers are being switched for each of the time intervals. The signals are output to synaptic input buffers as shown in the Figure 5)
wherein each timer determines the timing at which the signal is to be output ([Rhodes, page 11, line 13 – page 12, line 27], [page 10, Figure 5] and [page 11, Figure 6] discloses that Neuron core, Poisson core, and Synapse cores has its own timer callback (i.e., more than two timers) and Poisson core timer callback occurs approximately mid-way through the timer period to avoid SDRAM contention with reads/writes by other cores in the ensemble)
Response to Arguments
Response to Arguments under 35 U.S.C. 101
Amended claim 1 has been entered. 35 U.S.C. 101 rejections have been withdrawn.
Response to Arguments under 35 U.S.C. 102 and 103
Arguments: Applicant asserts that the offsets of Davies disclosed at [0058], [0060] and [0119] cannot be relied upon to allegedly disclose the claimed “output a signal at a timing that is within a first time interval and that is in accordance with the timing at which the membrane potential attains the prescribed threshold value within a second time interval.”
Examiner’s Response: Examiner respectfully disagrees. First, the examiner notes that the applicant changes the claim limitation from “varies, for each of a plurality of time intervals, an index value of a signal output” to “vary, for each of a plurality of time intervals, a membrane potential based on…” which requires the examiner to change the mapping of the limitation because the ‘index value’ and the ‘membrane potential’ are distinguishable. The examiner introduced paragraph [0067] from Davies to teach the ‘membrane potential attains the prescribed threshold value’.
Paragraph [0067] discloses a synchronization step that (1) receive the incoming weighted neurotransmitter amounts receiving from the dendrites, (2) updating Vm membrane potential state level based on the accumulated dendrite value, (3) detect whether the Vm membrane potential state exceeds the threshold activation level value, (4) producing outgoing spike event at T+D_axon time step, where D_axon is delay. Examiner asserts that the claimed “output a signal at a timing that is within a first time interval and that is in accordance with the timing at which the membrane potential attains the prescribed threshold value within a second time interval” is exactly the same process as the step disclosed in Davies, paragraph [0067], because the T+D_axon is the first time step (discrete unit of time progression) for outputting a signal and T corresponds to the second time step (discrete unit of time progression) at which the membrane potential attains the prescribed threshold value.
Therefore, arguments regarding claim 1 is not persuasive. Similarly, arguments regarding independent claims 4 and 5 are not persuasive for at least the same reasons. Claims 2-3 depend from claim 1 and arguments regarding claims 2-3 are not persuasive because the arguments regarding claim 1 is not persuasive.
New Claims
New Claim 6 is rejected under 35 U.S.C. 102 as being anticipated by Davies. See 35 U.S.C. 102 rejection for details.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lobo et al., “Spiking Neural Networks and online learning: An overview and perspectives”, 2019 (This prior art is pertinent because it discloses output spike generation based on membrane potential values and a threshold)
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUN KWON whose telephone number is (571)272-2072. The examiner can normally be reached Monday – Friday 7:30AM – 4:30PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Abdullah Kawsar can be reached at (571)270-3169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUN KWON/Examiner, Art Unit 2127
/ABDULLAH AL KAWSAR/Supervisory Patent Examiner, Art Unit 2127
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