Detailed Action
Claims 1-5 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because, under the broadest reasonable interpretation in light of the specification, they are directed to software per se. Specifically, claim 1 recites “computation apparatus that comprises: a spiking neuron model that ...” However, nowhere in the specification is the “spiking neuron model” defined as excluding purely software instantiations of the model. As neither claim 2 nor claim 3 adds hardware to the claim, they are also non-statutory. Examiner recommends amending the claims to recite the hardware on which the spiking neuron model runs explicitly.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Davies et al. (US 20180174026, hereinafter ‘Davies’).
Regarding claim 1, Davies teaches:
A computation apparatus that comprises a spiking neuron model that: ([Davies, 0033-0034] disclose that the apparatus is implemented using a spiking neural network)
varies, for each of a plurality of time intervals, an index value of a signal output based on an input condition of a signal in the time interval; ([Davies, 0118- 0119 and Fig. 14] discloses that the neuron index is output to a dendrite accumulator and soma. The variation of the index occurs during the time period in which the output is being prepared for input to the dendrite accumulator and soma and indexed from the SYNAPSE_MAP 1410 entry and adding the sequential offsets 0 … N-1)
detects an occurrence timing of a prescribed event relating to the index value; and ([Davies, 0067] A soma 330 spikes (detects) in response to accumulate activation value upon the occurrence of an updated operation (i.e., a prescribed event) at time T. [Davies, 0076] further discloses that the soma configuration receives number of detected spikes
s
i
[
t
]
for time step t at synapse i)
outputs a signal at a timing that is within a first time interval and that is in accordance with the occurrence timing of the prescribed event within a second time interval, the first time interval being included in the plurality of time intervals, the second time interval being included in the plurality of time intervals and being a time interval further in past than the first time interval. ([Davies, 0058, 0060 and 0119] discloses that the spikes are sent based on the sequential offsets to the base index of the destination neuron population. The delay offset is set from 1 to D_MAX, which indicates that the spike is sent with a delay of 1 … D_MAX, or after the time period for inputting the data that cause the spike. The total neurotransmitter amount scheduled for servicing at time step T+D (i.e., first time interval, Delay + occurrence timing T). The event timing T amounts to the second time interval)
Regarding claim 4, Davies teaches:
A computation method comprising: ([Davies, 0033-0034] and [0037] disclose the computation method that utilize the spiking neural network)
Claim 4 is a method claim which implements the same features as the apparatus claim 1, and is rejected for at least the same reasons.
Regarding claim 5, Davies teaches:
A non-transitory recording medium that causes a programmable apparatus to execute: ([Davies, 0033-0034] and [0037] disclose the computation apparatus and method that utilize the spiking neural network)
Claim 5 is a non-transitory recording medium claim which implements the same features as the apparatus claim 1, and is rejected for at least the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Davies in view of Rhodes et al. (Rhodes et al, “Real-time cortical simulation on neuromorphic hardware”, 2019, hereinafter ‘Rhodes’).
Regarding claim 2, Davies teaches:
The computation apparatus according to claim 1, wherein the spiking neuron model comprises [Davies, Fig. 22, 0167 and 0173] discloses that the soma has a timer, and the timer determines the delay of the output signal (i.e., refractory time and axon delay). [Davies, 0058, 0060 and 0119] discloses that the spikes are sent based on the sequential offsets to the base index of the destination neuron population. The delay offset is set from 1 to D_MAX, which indicates that the spike is sent with a delay of 1 … D_MAX, or after the time period for inputting the data that cause the spike. The total neurotransmitter amount scheduled for servicing at time step T+D (i.e., first time interval, Delay + occurrence timing T). The event timing T amounts to the second time interval)
However, Davies does not specifically disclose:
wherein the spiking neuron model comprises two timers that determine the timing at which the signal to be output
the spiking neuron model switches the two timers for each of the plurality of time intervals.
Rhodes teaches:
wherein the spiking neuron model comprises two timers that determine the timing at which the signal to be output ([Rhodes, page 11, line 13 – page 12, line 27], [page 10, Figure 5] and [page 11, Figure 6] discloses that Neuron core, Poisson core, and Synapse cores has its own timer callback (i.e., more than two timers) and Poisson core timer callback occurs approximately mid-way through the timer period to avoid SDRAM contention with reads/writes by other cores in the ensemble, which indicates that the timers are being switched for each of the time intervals. The signals are output to synaptic input buffers as shown in the Figure 5)
the spiking neuron model switches the two timers for each of the plurality of time intervals. ([Rhodes, page 11, line 13 – page 12, line 27], [page 10, Figure 5] and [page 11, Figure 6] discloses that the Poisson core timer callback occurs approximately mid-way through the timer period to avoid SDRAM contention with reads/writes by other cores in the ensemble, which indicates that the timers are being switched for each of the time intervals. The signals are output to synaptic input buffers as shown in the Figure 5)
Before the effective filing date of the invention to a person of ordinary skill in the art, it would have been obvious, having the teachings of Davies and Rhodes to use a method of utilizing two timers and switching timers for each of the plurality of time intervals of Rhodes to implement the spiking neural network system of Davies. The suggestion and/or motivation is intended to improve efficiency of system by avoiding memory contentions caused by other cores in the ensemble.
Regarding claim 3, Davies teaches:
The computation apparatus according to claim 2, wherein the spiking neuron model comprises: ([Davies, 0033-0034] and [0037] disclose the computation method that utilize the spiking neural network)
a first spiking neuron model that varies the index value and detects the occurrence timing of the prescribed event; and ([Davies, 0119 and Fig. 14] discloses the SYNAPSE_MAP 1410 (i.e., the first spiking neuron model) transmitting the spike to DENDRITE ACCUM 316 and SOMA 330. The variation of the index occurs during the time period in which the output is being prepared for input to the dendrite accumulator and soma and indexed from the SYNAPSE_MAP 1410 entry and adding the sequential offsets 0 … N-1. [Davies, 0076] further discloses that the soma configuration receives number of detected spikes
s
i
[
t
]
for time step t at synapse i)
two second spiking neuron models that comprise [Davies, Fig. 22, 0167 and 0173] discloses that the soma has a timer, and the timer determines the delay of the output signal (i.e., refractory time and axon delay). [Davies, 0119 and Fig. 14] discloses transmitting the index to the dendrite accumulator 316 (i.e., the first spiking neuron model) and SOMA 330 (i.e., the second spiking neuron model). [Davies, 0237 and 0243] The dendrite accumulator comprises a weighting array, and the soma state memory comprises the neuron’s present activation state level. These paragraphs indicate the soma and the dendrite accumulator are spiking neuron models)
when the first spiking neuron model detects the occurrence timing of the prescribed event, the first spiking neuron model outputs the signal to one of the two second spiking neuron models, and ([Davies, 0119 and Fig. 14] discloses transmitting the index to the dendrite accumulator 316 (i.e., the first spiking neuron model) and SOMA 330 (i.e., the second spiking neuron model). [Davies, 0237 and 0243] The dendrite accumulator comprises a weighting array, and the soma state memory comprises the neuron’s present activation state level. These paragraphs indicate the soma and the dendrite accumulator are spiking neuron models)
[Davies, Fig. 22, 0167 and 0173] discloses that the soma has a timer, and the timer determines the delay of the output signal (i.e., refractory time and axon delay). [Davies, 0058, 0060 and 0119] discloses that the spikes are sent based on the sequential offsets to the base index of the destination neuron population. The delay offset is set from 1 to D_MAX, which indicates that the spike is sent with a delay of 1 … D_MAX, or after the time period for inputting the data that cause the spike. The total neurotransmitter amount scheduled for servicing at time step T+D (i.e., first time interval, Delay + occurrence timing T). The event timing T amounts to the second time interval)
However, Davies does not specifically disclose:
two second spiking neuron models that comprise the two timers, respectively, and output the signal
each timer determines the timing at which the signal to be output
Rhodes teaches:
two second spiking neuron models that comprise the two timers, respectively, and output the signal ([Rhodes, page 11, line 13 – page 12, line 27], [page 10, Figure 5] and [page 11, Figure 6] discloses that Neuron core, Poisson core, and Synapse cores has its own timer callback (i.e., more than two timers) and Poisson core timer callback occurs approximately mid-way through the timer period to avoid SDRAM contention with reads/writes by other cores in the ensemble, which indicates that the timers are being switched for each of the time intervals. The signals are output to synaptic input buffers as shown in the Figure 5)
each timer determines the timing at which the signal to be output ([Rhodes, page 11, line 13 – page 12, line 27], [page 10, Figure 5] and [page 11, Figure 6] discloses that Neuron core, Poisson core, and Synapse cores has its own timer callback (i.e., more than two timers) and Poisson core timer callback occurs approximately mid-way through the timer period to avoid SDRAM contention with reads/writes by other cores in the ensemble)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUN KWON whose telephone number is (571)272-2072. The examiner can normally be reached Monday – Friday 7:30AM – 4:30PM ET.
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/JUN KWON/Examiner, Art Unit 2127
/ABDULLAH AL KAWSAR/Supervisory Patent Examiner, Art Unit 2127
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