DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant claims the benefit of prior-filed Korean Patent Application No. 10-2022- 0022196, filed on February 21, 2022, which is acknowledged.
Drawings
The drawings were received on 07/25/2022. These drawings are acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on the following date(s): 07/23/2024 and 07/25/2022 have been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20170286829, hereinafter ‘Chen’) in view of Danneville et al. (US 20210216856, hereinafter ‘Dan’) in further view of Park et al. (US 12507444, hereinafter ‘Park’).
Regarding independent claim 1, Chen teaches a neuromorphic system for implementing a spike timing dependent plasticity (STDP) operation, the neuromorphic system comprising: (in [0026] FIG. 18 is a flow chart of a method for performing event-based spike timing dependent plasticity (STDP) in a neuromorphic processor, in accordance with embodiments of the present disclosure.)
a pre-synaptic neuron configured to output a pre-neuron spike; (As depicted in Fig. 13 and Fig. 14:
PNG
media_image1.png
274
878
media_image1.png
Greyscale
PNG
media_image2.png
266
814
media_image2.png
Greyscale
in [0104] At 1410, in one embodiment, pre-synaptic neuron 1402 may spike. In response to pre-synaptic neuron 1402 spiking [a pre-synaptic neuron configured to output a pre-neuron spike], pre-synaptic neuron spike history 1412 may be written with a maximum value. Furthermore, in addition to transmitting a forward propagating signal through synapses 1404 to other neurons, pre-synaptic neuron 1402 may transmit a forward propagating STDP signal to synapses and neuron, such as synapse 1404 and post-synaptic neuron 1406…; And in [0094] ... One method of training synapse weights may be spike timing dependent plasticity (“STDP”). STDP may be a temporally asymmetric form of Hebbian learning induced by temporal correlations between the spikes of pre- and postsynaptic neurons. Accordingly, a neuromorphic processor may be a learning architecture that may be trained through iterative adjustment of synapse weights. STDP may modify synapse weights according to a relative spike timing between the pre-synaptic neurons and post-synaptic neurons that each synapse connects. A pre-synaptic neuron firing [a pre-synaptic neuron configured to output a pre-neuron spike] may have a certain probability of inducing firing in a post-synaptic neuron. Accordingly, when a pre-synaptic neurons fires before a post-synaptic neurons fires, there may be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron. This relationship may be reinforced by adjusting the synapse weight connecting the two neurons through long-term potentiation (LTP). LTP may increase synapse weights where the relative timing of pre-synaptic neuron firing and firing in a post-synaptic neuron indicates a correlation or causation. Relatedly, when a pre-synaptic neurons fires after a post-synaptic neurons fires, there may not be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron…)
a first signal generation circuit configured to transform the pre-neuron spike output from the pre-synaptic neuron into a pre-neuron signal available for synaptic learning and output the pre-neuron signal; (As depicted in Fig. 13 and Fig. 14:
PNG
media_image1.png
274
878
media_image1.png
Greyscale
PNG
media_image2.png
266
814
media_image2.png
Greyscale
in [0104] At 1410, in one embodiment, pre-synaptic neuron 1402 may spike. In response to pre-synaptic neuron 1402 spiking, pre-synaptic neuron spike history 1412 may be written with a maximum value [a first signal generation circuit configured to transform the pre-neuron spike output from the pre-synaptic neuron into a pre-neuron signal available for synaptic learning]. Furthermore, in addition to transmitting a forward propagating signal through synapses 1404 to other neurons [a first signal generation circuit configured to transform the pre-neuron spike output from the pre-synaptic neuron into a pre-neuron signal available for synaptic learning and output the pre-neuron signal], pre-synaptic neuron 1402 may transmit a forward propagating STDP signal to synapses and neuron, such as synapse 1404 and post-synaptic neuron 1406. Specifically, a forward propagating signal may be transmitted to post-synaptic STDP module 1406. The forward propagating signal may be transmitted via a multicast network on chip, through synapse 1404, or through any other suitable method. A forward propagating STDP signal may not be evaluated as an input to post-synaptic neuron 1406. A forward propagating STDP signal may include a signal indicating that pre-synaptic neuron 1402 has fired. For example, a forward propagating signal may include an instruction, packet, or other signal indicating that pre-synaptic neuron 1402 has fired. Additionally, a forward propagating signal may include a spike history value of pre-synaptic neuron 1402 [a first signal generation circuit configured to transform the pre-neuron spike output from the pre-synaptic neuron into a pre-neuron signal available for synaptic learning and output the pre-neuron signal], such as post-synaptic neuron spike history 1412.; And in [0094] … The process of selecting, modifying, or adjusting a synapse weight may be referred to as training. One method of training synapse weights may be spike timing dependent plasticity (“STDP”). STDP may be a temporally asymmetric form of Hebbian learning induced by temporal correlations between the spikes of pre- and postsynaptic neurons. Accordingly, a neuromorphic processor may be a learning architecture that may be trained through iterative adjustment of synapse weights. STDP [a first signal generation circuit configured to transform the pre-neuron spike output from the pre-synaptic neuron into a pre-neuron signal available for synaptic learning and output the pre-neuron signal] may modify synapse weights [transform the pre-neuron spike output from the pre-synaptic neuron into a pre-neuron signal available for synaptic learning] according to a relative spike timing between the pre-synaptic neurons and post-synaptic neurons that each synapse connects. A pre-synaptic neuron firing may have a certain probability of inducing firing in a post-synaptic neuron. Accordingly, when a pre-synaptic neurons fires before a post-synaptic neurons fires, there may be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron. This relationship may be reinforced by adjusting the synapse weight connecting the two neurons through long-term potentiation (LTP). LTP may increase synapse weights where the relative timing of pre-synaptic neuron firing and firing in a post-synaptic neuron indicates a correlation or causation. Relatedly, when a pre-synaptic neurons fires after a post-synaptic neurons fires, there may not be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron…)
a first driver having an output terminal and configured to output the pre-neuron signal output from the first signal generation circuit; (As depicted in Fig. 13 and Fig. 14:
PNG
media_image1.png
274
878
media_image1.png
Greyscale
PNG
media_image2.png
266
814
media_image2.png
Greyscale
[0094] Synapses 1100 may have an associated synapse weight. When synapses 1106 transmit [a first driver having an output terminal and configured to output the pre-neuron signal output from the first signal generation circuit] an output of an instance of neuron to an input of an instance of neuron, that output may be multiplied by a synapse weight. As previously described, a neuron may sum or integrate these values. During operation, synapse weights 1106 of synapses 1100 may be selected, modified, or adjusted, making a neuromorphic processor adaptive to various inputs and capable of learning [a first driver having an output terminal and configured to output the pre-neuron signal output from the first signal generation circuit]. The process of selecting, modifying, or adjusting a synapse weight may be referred to as training. One method of training synapse weights may be spike timing dependent plasticity (“STDP”). STDP may be a temporally asymmetric form of Hebbian learning induced by temporal correlations between the spikes of pre- and postsynaptic neurons. Accordingly, a neuromorphic processor may be a learning architecture that may be trained through iterative adjustment of synapse weights. STDP may modify synapse weights according to a relative spike timing between the pre-synaptic neurons and post-synaptic neurons that each synapse connects [a first driver having an output terminal and configured to output the pre-neuron signal output from the first signal generation circuit]. A pre-synaptic neuron firing may have a certain probability of inducing firing in a post-synaptic neuron. Accordingly, when a pre-synaptic neurons fires before a post-synaptic neurons fires, there may be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron. This relationship may be reinforced by adjusting the synapse weight connecting [having an output terminal to transmit claimed signals] the two neurons through long-term potentiation (LTP) [a first driver having an output terminal and configured to output the pre-neuron signal output from the first signal generation circuit]. LTP may increase synapse weights where the relative timing of pre-synaptic neuron firing and firing in a post-synaptic neuron indicates a correlation or causation. Relatedly, when a pre-synaptic neurons fires after a post-synaptic neurons fires, there may not be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron…; 0143-0144: Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches… Program code may be applied to input instructions to perform the functions described herein and generate output information…)
a synapse array including a plurality of input lines, one of the plurality of input lines being connected to the output terminal of the first driver, plurality of output lines and configured to receive the pre-neuron signal output from the first driver; and an STDP implementation circuit including one or more STDP control blocks each disposed on a respective one of the output lines, (As depicted in Fig. 13 and Fig. 14 Examiner notes synapse connect an array/sequence pattern of neuron/nodes of a neural network, the connected lines are configured to transmit signals using claimed driver)
each of the one or more STDP control blocks comprising a first transmission (As depicted in Fig. 13 and 14 Examiner notes that the signals are passed through the synapse to transmit pre & post synaptic neuron as depicted in the images. The signals are transmitted using claimed components in [0089] Neurons 1002 and synapses 1008 may be interconnected such that neuromorphic processor 1000 operates to process or analyze information received by neuromorphic processor [each of the one or more STDP control blocks comprising a first transmission ]. In general, neurons 1002 may transmit an output pulse (or “fire” o “spike”) when inputs received through neuron input 1004 exceed a threshold. In some embodiments, neurons 1002 may sum or integrate signals received at neuron inputs 1004. For example, neurons 1002 may be implemented as leaky integrate-and-fire neuron. When this sum (referred to as a “membrane potential”) exceeds a threshold value, a neuron may generate an output (or “fire”) using a transfer function such as a sigmoid or threshold function. A leaky integrate and fire neuron may sum signals received at neuron inputs 1004 into a membrane potential and may also apply a decay factor (or leak) to reduce a membrane potential…[0094] Synapses 1100 may have an associated synapse weight. When synapses 1106 transmit an output of an instance of neuron to an input of an instance of neuron, that output may be multiplied by a synapse weight. As previously described, a neuron may sum or integrate these values. During operation, synapse weights 1106 of synapses 1100 may be selected, modified, or adjusted, making a neuromorphic processor adaptive to various inputs and capable of learning. The process of selecting, modifying, or adjusting a synapse weight may be referred to as training. One method of training synapse weights may be spike timing dependent plasticity (“STDP”) [each of the one or more STDP control blocks comprising a first transmission ]. STDP may be a temporally asymmetric form of Hebbian learning induced by temporal correlations between the spikes of pre-[each of the one or more STDP control blocks comprising a first transmission ] and postsynaptic [a post-synaptic neuron configured to output the post- neuron spike according to the membrane potential charged in the membrane ] neurons. Accordingly, a neuromorphic processor may be a learning architecture that may be trained through iterative adjustment of synapse weights. STDP may modify synapse weights according to a relative spike timing between the pre-synaptic neurons and post-synaptic neurons that each synapse connects…)
the one or more STDP control blocks being configured to generate a post-neuron spike in response to the pre-neuron signal input through the synapse units, transform the generated post-neuron spike into a post-neuron signal available for synaptic learning and output the post-neuron signal to the synapse units through the respective output lines. (As depicted in Fig. 13 and Fig. 14:
PNG
media_image1.png
274
878
media_image1.png
Greyscale
PNG
media_image2.png
266
814
media_image2.png
Greyscale
And in [0094] …. During operation, synapse weights 1106 of synapses 1100 may be selected, modified, or adjusted, making a neuromorphic processor adaptive to various inputs and capable of learning. The process of selecting, modifying, or adjusting a synapse weight may be referred to as training.. STDP may modify synapse weights according to a relative spike timing between the pre-synaptic neurons and post-synaptic neurons that each synapse connects [the one or more STDP control blocks being configured to generate a post-neuron spike in response to the pre-neuron signal input through the synapse units, transform the generated post-neuron spike into a post-neuron signal available for synaptic learning and output the post-neuron signal to the synapse units through the respective output lines.]. A pre-synaptic neuron firing may have a certain probability of inducing firing in a post-synaptic neuron. Accordingly, when a pre-synaptic neurons fires before a post-synaptic neurons fires, there may be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron [the one or more STDP control blocks being configured to generate a post-neuron spike in response to the pre-neuron signal input through the synapse units, transform the generated post-neuron spike into a post-neuron signal available for synaptic learning and output the post-neuron signal to the synapse units through the respective output lines]. This relationship may be reinforced by adjusting the synapse weight connecting the two neurons through long-term potentiation (LTP). LTP may increase synapse weights where the relative timing of pre-synaptic neuron firing and firing in a post-synaptic neuron indicates a correlation or causation [transform the generated post-neuron spike into a post-neuron signal available for synaptic learning and output the post-neuron signal to the synapse units through the respective output lines]. Relatedly, when a pre-synaptic neurons fires after a post-synaptic neurons fires, there may not be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron…; And in [0105] At 1418, in one embodiment, post-synaptic STDP module 1416 may retrieve post-synaptic neuron spike history 1414. Post-synaptic STDP module 1416 [the one or more STDP control blocks being configured to generate a post-neuron spike in response to the pre-neuron signal input through the synapse units,] may compare and process pre-synaptic neuron spike history 1412 and post-synaptic neuron spike history 1414. In some embodiments, post-synaptic STDP module 1416 may receive pre-synaptic neuron spike history 1412 from pre-synaptic neuron 1402… In some embodiments, a synapse weight offset may be additionally modified by applying any suitable transfer function… )
a synapse array including a plurality of input lines, one of the plurality of input lines being connected to the output terminal of the first driver, a plurality of output lines disposed to cross the plurality of input lines, and synapse units disposed between the plurality of input lines and the plurality of output lines and configured to receive the pre-neuron signal output from the first driver;
Chen teaches the neuromorphic processing system for processing information as noted above.
One of ordinary skill in the art would understand that in modeling/designing, in neuromorphic processor/system, a membrane potential for transmitting signals through synapse units/circuits involves the use of circuit components.
Dan teaches and an STDP implementation circuit including one or more STDP control blocks each disposed on a respective one of the output lines, each of the one or more STDP control blocks comprising a first transmission gate configured to transmit the pre-neuron signal passing through the synapse units and output through the respective output line, a membrane capacitor configured to be charged with a membrane potential by the pre-neuron signal transmitted through the first transmission gate, and a post-synaptic neuron configured to output the post- neuron spike according to the membrane potential charged in the membrane capacitor, the one or more STDP control blocks being configured to generate a post-neuron spike in response to the pre-neuron signal input through the synapse units, in [0016] The “membrane potential” denotes the potential at the terminal of the membrane capacitor of the neuron […the membrane potential charged in the membrane capacitor…]. [0017] Preferably, the end transistor connected to VA.sub.out is a PMOS transistor and the end transistor connected to the membrane potential (V.sub.memB) of the post-neuron is an NMOS transistor… [0020] The synapse may include at least one third intermediate field-effect transistor, preferably CMOS, belonging to the chain of transistors, and positioned between said end transistors, the gate of this third transistor being linked to the drain or to the source of one of the end transistors. This third transistor makes it possible to control the synaptic current by adjusting its intensity… [0027] A learning circuit, called STDP (“spike timing dependent plasticity”) [each of the one or more STDP control blocks …, the one or more STDP control blocks being configured to generate a post-neuron spike in response to the pre-neuron signal input through the synapse units], preferably including: [0028] Two field-effect transistors, preferably CMOS, even more preferably PMOS transistors, linked in series, the first transistor having the source connected to the output potential VB.sub.out of the post-neuron [and a post-synaptic neuron configured to output the post- neuron spike according to the membrane potential charged in the membrane capacitor], the gate connected [a membrane capacitor configured to be charged with a membrane potential by the pre-neuron signal transmitted through the first transmission gate] to a complementary state VB.sub.out bar of this potential and the drain connected to the source of the second transistor, whose drain is connected to a terminal of a first capacitor integrating the synaptic weight potential, the other terminal of this first capacitor being linked to ground, the drain of the second transistor supplying the analogue voltage V.sub.w analogue to the memory circuit, [0029] a third field-effect transistor [each of the one or more STDP control blocks comprising a first transmission gate configured to transmit the pre-neuron signal passing through the synapse units and output through the respective output line], preferably CMOS, even more preferably PMOS, whose source is linked to the potential VA.sub.out of the pre-neuron [an STDP implementation circuit including one or more STDP control blocks each disposed on a respective one of the output lines, each of the one or more STDP control blocks comprising a first transmission gate configured to transmit the pre-neuron signal passing through the synapse units and output through the respective output line, a membrane capacitor configured to be charged with a membrane potential by the pre-neuron signal transmitted through the first transmission gate,], whose gate is linked to ground and whose drain is linked to a terminal of a second capacitor whose other terminal is linked to ground,… And as depicted in Fig 12A and in [0116] To express the STDP from an artificial point of view, FIG. 12A shows an example of a circuit 22 used to determine, at the point P1, the binary synaptic weight potential V.sub.w from the output voltages VA.sub.out and VB.sub.out of the pre-neuron and post-neuron [the one or more STDP control blocks being configured to generate a post-neuron spike in response to the pre-neuron signal input through the synapse units], respectively. This circuit 22 comprises an STDP learning circuit 23 generating what is called an analogue synaptic weight potential V.sub.w analogue, which goes to the input of a SRAM-based memory circuit 24 in order to produce the binary synaptic weight potential V.sub.w. The STDP learning circuit includes firstly a PMOS transistor 19 supplied with VA.sub.out and charging a capacitor 21, and secondly two PMOS transistors 17 and 18 in series charging a capacitor 20, an inverter 16 linking the drain of the transistor 19 to the gate of the transistor 18. The transistor 17 is supplied with VB.sub.out and has its gate connected to VB.sub.out bar, the complementary state of VB.sub.out. Upon the arrival of an action potential of the pre-neuron that is ahead with respect to that of the post-neuron, the analogue synaptic weight voltage V.sub.w analogue across the terminals of the capacitor 20 increases…
PNG
media_image3.png
488
676
media_image3.png
Greyscale
Dan and Chen are analogous art because both involve developing information retrieval and processing techniques for synaptic learning in a spiking neural network (SNN)-based neuromorphic architectures and models.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art for developing circuits for implementing spike-timing dependent plasticity (STDP) and a neuromorphic system as disclosed by Dan with the method of developing information retrieval and processing system for event-driven learning with spike timing dependent plasticity in neuromorphic computers as disclosed by Chen.
One of ordinary skill in the arts would have been motivated to combine the methods disclosed by Dan and Chen above. Doing so allowing for implementing a circuit with low energy consumption that is able to reproduce certain electrical properties of a biological synapse, and that is able to be used in particular in bioinspired architectures, (Dan, 0001).
Chen and Dan teaches the neuromorphic processing system for processing information using a synapse circuit, as noted above.
One of ordinary skill in the art would understand that in modeling/designing, in neuromorphic processor/system can be configured into an array structure as claimed a synapse array including a plurality of input lines, one of the plurality of input lines being connected to the output terminal of the first driver, a plurality of output lines disposed to cross the plurality of input lines, and synapse units disposed between the plurality of input lines and the plurality of output lines and configured to receive the pre-neuron signal output from the first driver;
Park expressly teaches neuromorphic processor/system can be configured into an array structure as claimed a synapse array including a plurality of input lines, one of the plurality of input lines being connected to the output terminal of the first driver, a plurality of output lines disposed to cross the plurality of input lines, and synapse units disposed between the plurality of input lines and the plurality of output lines and configured to receive the pre-neuron signal output from the first driver;, As depicted in Fig4 and in 2:66-3:10: In accordance with another aspect of the present invention, there is provided a neuromorphic system, including: at least one pre-neuron; at least one synapse [a synapse array including a plurality of input lines, one of the plurality of input lines being connected to the output terminal of the first driver, a plurality of output lines disposed to cross the plurality of input lines, and synapse units disposed between the plurality of input lines and the plurality of output lines and configured to receive the pre-neuron signal output from the first driver] electrically connected to the pre-neuron; and at least one post-neuron electrically connected to the synapse and configured to include a completely depleted Silicon-On-Insulator (SOI) device, wherein the post-neuron performs integration and leakage. A depletion region of the post-neuron may be controlled according to an inputted electrical signal (spike) to perform the integration and the leakage. The synapse may have a cross-bar array structure… 3:40-43: FIG. 4 is a schematic diagram illustrating a cross-bar array structure [a synapse array including a plurality of input lines, one of the plurality of input lines being connected to the output terminal of the first driver, a plurality of output lines disposed to cross the plurality of input lines, and synapse units disposed between the plurality of input lines and the plurality of output lines and configured to receive the pre-neuron signal output from the first driver] of a neuromorphic system according to an embodiment of the present invention… 8:11-20: Therefore, the neuromorphic system according to an embodiment of the present invention forms a cross-bar array structure 400 to realize a neural network structure composed of neurons according to an embodiment of the present invention and connection between the neurons, thereby being capable of realizing artificial intelligence hardware with improved efficiency in terms of data processing, transmission speed, and energy consumption due to operation through interaction between the neurons according to an embodiment of the present invention.
PNG
media_image4.png
536
476
media_image4.png
Greyscale
Park, Dan and Chen are analogous art because both involve developing information retrieval and processing techniques for synaptic learning in a spiking neural network (SNN)-based neuromorphic architectures and models.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art for developing circuits for implementing neuromorphic systems that implements neurons constituting the human brain using a plurality of devices and thus mimics data processing by the brain, as disclosed by Park with the method of developing information retrieval and processing system for event-driven learning with spike timing dependent plasticity in neuromorphic computers as collectively disclosed by Dan and Chen.
One of ordinary skill in the arts would have been motivated to combine the methods disclosed by Park, Dan and Chen above. Doing so allowing for implementing a circuit with low energy consumption that mimics data processing by the brain using neuromorphic system containing neurons, (Park, 1:24-44).
Claims 2-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Dan and Park in further view of Kim et al. (US 20140358834, hereinafter ‘Kim’)
Regarding claim 2, the rejection of claim 1 is incorporated and Chen in combination with Dan and Park further teaches the neuromorphic system of claim 1, wherein each of the synapse units comprises: wherein each of the synapse units comprises: a memristor or a memtransistor connected between one of the plurality of input lines connected to the output terminal of the first driver and one of the plurality of output lines which is disposed to cross the one of the plurality of input lines and through which the pre- neuron signal output from the synapse unit is output to a respective one of the STDP control blocks; (in [0093] FIG. 11 is a block diagram of a synapse, in accordance with embodiments of the present disclosure. Synapse 1100 [wherein each of the synapse units comprises: wherein each of the synapse units comprises: a memristor or a memtransistor connected between one of the plurality of input lines connected to the output terminal of the first driver and one of the plurality of output lines which is disposed to cross the one of the plurality of input lines and through which the pre- neuron signal output from the synapse unit is output to a respective one of the STDP control blocks;…] and components thereof may be implemented using circuitry or logic. Each synapse 1100 may include synapse memory 1102. Synapse memory 1102 may be composed of static random access memory, memristors [a memristor], spin torque memory, or any other suitable type of memory circuit or logic. Synapse memory 1102 may store synapse weight 1106 and synapse destination 1110… [0096] FIG. 12 is a block diagram of a neuron, in accordance with embodiments of the present disclosure. Each instance of neuron 1200 may include a neuron memory. Neuron memory may be composed of register files, static random access memory, memristors, spin torque memory, or any other suitable type of memory circuit or logic. Neuron memory may include circuitry or logic that can store information relating to the operation of neuron 1200…; Examiner notes that the scope’s broadest reasonable interpretations (BRI) is simply a memristor)
Additionally, Dan teaches the neuromorphic processing circuit including claimed components, in [0034] As a variant, the STDP learning circuit may be produced using a memristor-based technology [wherein each of the synapse units comprises: wherein each of the synapse units comprises: a memristor or a memtransistor connected between one of the plurality of input lines connected to the output terminal of the first driver and one of the plurality of output lines which is disposed to cross the one of the plurality of input lines and through which the pre- neuron signal output from the synapse unit is output to a respective one of the STDP control blocks; and a transistor connected to the memristor or the memtransistor]… And in [0027] A learning circuit, called STDP (“spike timing dependent plasticity”) [and a transistor connected to the memristor or the memtransistor], preferably including: [0028] Two field-effect transistors [and a transistor connected to the memristor or the memtransistor], preferably CMOS, even more preferably PMOS transistors, linked in series, the first transistor having the source connected to the output potential VB.sub.out of the post-neuron, the gate connected to a complementary state VB.sub.out bar of this potential and the drain connected to the source of the second transistor, whose drain is connected to a terminal of a first capacitor integrating the synaptic weight potential, the other terminal of this first capacitor being linked to ground, the drain of the second transistor supplying the analogue voltage V.sub.w analogue to the memory circuit,…
Park expressly teaches the limitation: and a transistor connected to the memristor or the memtransistor , in 3:11-12: The synapse may include a memristor and a selection element… And in 9:1-3: In addition, the synapse 520 may have a cross-bar array structure and may include a memristor and a selection element.
Additionally, Park teaches the cross bar array configurations as claimed lines wherein each of the synapse units comprises: a memristor or a memtransistor connected between one of the plurality of input lines connected to the output terminal of the first driver and one of the plurality of output lines which is disposed to cross the one of the plurality of input lines and through which the pre- neuron signal output from the synapse unit is output to a respective one of the STDP control blocks, as depicted in fig. 4 and noted in claim 1 rejection.
While one of ordinary skill in the art would understand that a synapse circuit implemented as part of a spike timing dependent plasticity (STDP) operation would include a transistor connected to a memristor.
Chen does not expressly teach the limitation: and a transistor connected to the memristor or the memtransistor
Kim teaches and a transistor connected to the memristor or the memtransistor. (in [0008] In one general aspect, there is provided a synapse circuit to perform spike timing dependent plasticity (STDP) operation, the synapse circuit including a memristor having a resistance value, and a transistor connected to the memristor [a transistor connected to the memristor or the memtransistor], the transistor configured to receive at least two input signals, in which the resistance value of the memristor is changed based on a time difference between the at least two input signals received by the transistor. )
Kim, Park, Dan and Chen are analogous art because both involve developing information retrieval and processing techniques for synaptic learning in a spiking neural network (SNN)-based neuromorphic architectures and models.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art for developing synapse circuit for operation of spike-timing dependent plasticity (STDP) and a neuromorphic system as disclosed by Kim with the method of developing information retrieval and processing system for event-driven learning with spike timing dependent plasticity in neuromorphic computers as collectively disclosed by Park, Dan and Chen.
One of ordinary skill in the arts would have been motivated to combine the methods disclosed by Kim, Park, Dan and Chen, as noted above. Doing so allowing for implementing a synapse circuit configured to receive at least two input signal to update and modify a resistance value of the memristor based on a time difference between the at least two input signals received by the transistor, (Kim, Abstract). This allow for implementing a spiking neural network designed to mimic the operation of biological nervous system, (Kim, 0006).
Regarding claim 3, the rejection of claim 2 is incorporated and Kim further teaches the neuromorphic system of claim 2, wherein a drain terminal of the transistor is connected to the one of the plurality of input lines a source terminal is connected to one end of the memristor or the memtransistor, ( As depicted in Fig. 1 and in [0013] The synapse circuit may further include a first terminal connected to the gate terminal of the transistor and configured to provide the first input signal, and a second terminal connected to the source terminal of the transistor and configured to provide the second input signal, and the synapse circuit may be connected to a pre-synaptic neuron circuit through the first terminal and to a post-synaptic neuron circuit through the second terminal.)
and a gate terminal is connected to a driving line such that the transistor is selected and driven by a driving voltage applied through the driving line and the other end of the memristor or the memtransistor is connected to the one of the plurality of output (As depicted in Fig. 1:
PNG
media_image5.png
548
526
media_image5.png
Greyscale
[0042] In this example, the synapse circuit 110 [and a gate terminal is connected to a driving line such that the transistor is selected and driven by a driving voltage applied through the driving line and the other end of the memristor or the memtransistor is connected to the one of the plurality of output] includes a memristor 113. A resistance value of the memristor 113 may be changed. The synapse circuit 110 also includes a transistor 116 that is connected to the memristor 113. The transistor 116 receives at least two input signals. The resistance value of the memristor 113 may be changed based on a difference in input time of the at least two input signals that are applied to the transistor 116. [0043] For example, the resistance value of the memristor 113 may be changed according to a voltage change due to the input time difference of the input signals. For example, the resistance value of the memristor 113 may be changed according to a voltage change due to an input time difference between a first input signal and a second input signal. The first input signal may be a signal applied to a gate terminal of the transistor 116 [and a gate terminal is connected to a driving line such that the transistor is selected and driven by a driving voltage applied through the driving line and the other end of the memristor or the memtransistor is connected to the one of the plurality of output.]. The second input signal may be a signal based on a membrane voltage applied to a source terminal of the transistor 116. The first input signal may be transmitted from the pre-synaptic neuron circuit A 130, and the second input signal may be transmitted from the post-synaptic neuron circuit B 150. )
Park teaches the plurality of lines connected using synapse circuits/units in a crossbar array as depicted in Fig. 1 and noted in claim 1 rejection.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Kim, Park, Dan and Chen for the same reasons disclosed above.
Regarding claim 4, the rejection of claim 2 is incorporated and Chen in combination with Dan, Park and Kim further teaches the neuromorphic system of claim 2, wherein each of the STDP control blocks further comprises: a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal; a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line; and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the respective output line in response to the post-neuron signal output from the second signal generator. (As depicted in Figs. 10, 13 and 14 and in [0003] A neuromorphic processor may operate in a manner similar to biological neural networks (such as a central nervous system of an animal). Specifically, a neuromorphic processor may include a network of interconnected “neurons” that may exchange data between one another. Each connection between a neuron may be referred to as a “synapse.” [wherein each of the STDP control blocks further comprises: a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal; a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line; and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the respective output line in response to the post-neuron signal output from the second signal generator] A neuron may have one output that may fan out to one or more synapses. At each synapse, the output of a neuron may be multiplied by a synapse weight. This weighted output of a neuron may be transmitted via the one or more synapses to an input of one or more neurons. Neurons may sum (or integrate) these received inputs… [0094] Synapses 1100 may have an associated synapse weight. When synapses 1106 transmit an output of an instance of neuron to an input of an instance of neuron, that output may be multiplied by a synapse weight. As previously described, a neuron may sum or integrate these values. During operation, synapse weights 1106 of synapses 1100 may be selected, modified, or adjusted, making a neuromorphic processor adaptive to various inputs and capable of learning. The process of selecting, modifying, or adjusting a synapse weight may be referred to as training [a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal]. One method of training synapse weights may be spike timing dependent plasticity (“STDP”). STDP may be a temporally asymmetric form of Hebbian learning induced by temporal correlations between the spikes of pre- and postsynaptic neurons [wherein each of the STDP control blocks further comprises: a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal; a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line; and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the respective output line in response to the post-neuron signal output from the second signal generator]. Accordingly, a neuromorphic processor may be a learning architecture that may be trained through iterative adjustment of synapse weights. STDP may modify synapse weights according to a relative spike timing between the pre-synaptic neurons and post-synaptic neurons that each synapse connects. A pre-synaptic neuron firing may have a certain probability of inducing firing in a post-synaptic neuron. Accordingly, when a pre-synaptic neurons fires before a post-synaptic neurons fires, there may be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron [a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line;]. This relationship may be reinforced by adjusting the synapse weight connecting the two neurons through long-term potentiation (LTP) [a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line]. LTP may increase synapse weights where the relative timing of pre-synaptic neuron firing and firing in a post-synaptic neuron indicates a correlation or causation. Relatedly, when a pre-synaptic neurons fires after a post-synaptic neurons fires, there may not be a probability of causation or correlation between a pre-synaptic neuron firing and inducing firing in a post-synaptic neuron..… [0095] STDP module 1108 may operate to adjust synapse weights 1106. STDP module 1108 may receive packets from a pre-synaptic neuron or a post-synaptic neuron of synapse 1100 [and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the respective output line in response to the post-neuron signal output from the second signal generator]. STDP module 1108 may parse these packets to identify instructions for adjusting synapse weight 1106. For example, synapse weight 1106 may be incremented or decremented by one. A positive or negative offset may be added to synapse weight 1106. The sign of synapse weight 1106 may be altered, or the synapse weight 1106 may be multiplied or otherwise scaled. STDP module 1108 and components thereof may be implemented using circuitry or logic [a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal; a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line; and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the respective output line in response to the post-neuron signal output from the second signal generator.]. Examiner notes that synapse circuit uses respective signal generators/drivers to transmit signals between connected pre and post neurons using a membrane potential with respective components, in [0031] A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as may be useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process…)
Additionally:
Dan teaches in [0027] A learning circuit, called STDP (“spike timing dependent plasticity”) [a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal; a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line; and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the respective output line in response to the post-neuron signal output from the second signal generator], preferably including: [0028] Two field-effect transistors, preferably CMOS, even more preferably PMOS transistors, linked in series [a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line], the first transistor having the source connected to the output potential VB.sub.out of the post-neuron [a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal;], the gate connected to a complementary state VB.sub.out bar of this potential and the drain connected to the source of the second transistor [and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the respective output line in response to the post-neuron signal output from the second signal generator], whose drain is connected to a terminal of a first capacitor integrating the synaptic weight potential, the other terminal of this first capacitor being linked to ground, the drain of the second transistor supplying the analogue voltage V.sub.w analogue to the memory circuit, [0029] a third field-effect transistor, preferably CMOS, even more preferably PMOS, whose source is linked to the potential VA.sub.out of the pre-neuron, whose gate is linked to ground and whose drain is linked to a terminal of a second capacitor whose other terminal is linked to ground, and [0030] an inverter whose input is linked to the drain of the third transistor and whose output is linked to the gate of the second transistor.
Kim expressly teaches a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal; a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line; and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the respective output line in response to the post-neuron signal output from the second signal generator. (Depicted in Fig. 1:
PNG
media_image6.png
369
354
media_image6.png
Greyscale
and in [0020] In another general aspect, there is provided a neuromorphic system including: a synapse circuit configured to perform spike timing dependent plasticity (STDP) operation [a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal;], the synapse circuit including a first terminal, a second terminal, a memristor having a resistance value, and a transistor connected to the memristor; a pre-synaptic neuron circuit connected to the memristor through the first terminal of the synapse circuit; and a post-synaptic neuron circuit connected to the memristor through the second terminal of the synapse circuit [a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line;]. The resistance value of the memristor may be changed based on a time difference between at least two input signals received by the synapse circuit … [0040] STDP is a learning mechanism [a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal] postulated to exist in synapses of nerve networks. Based on STDP, synaptic efficacy or weight is slightly altered between two neurons based on the timing of a pre-synaptic spike in a pre-synaptic neuron and a post-synaptic spike in a post-synaptic neuron [a second signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal; a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the respective output line; and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the respective output line in response to the post-neuron signal output from the second signal generator]… [0058] The post-synaptic neuron circuit B 150 may generate a spike that fires [.. the post-synaptic neuron into the post-neuron signal available for synaptic learning and output the post-neuron signal] with reference to a resting voltage V.sub.rest. For example, the resting voltage V.sub.rest may be approximately 0.3 (VDD)… [0070] Thus, the STDP characteristics may be achieved using a synapse circuit according to a voltage-dependent current driven method and neuron circuits generating spikes fired with reference to a proper voltage, for example, the resting voltage V.sub.rest. In addition, because the STDP characteristics may be achieved by only the synapse circuit without an additional circuit, a high integration neuromorphic system may be constructed. )
Park teaches the plurality of lines connected using synapse circuits/units in a crossbar array as depicted in Fig. 1 and noted in claim 1 rejection.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Kim, Park, Dan and Chen for the same reasons disclosed above.
Regarding claim 5, the rejection of claim 4 is incorporated and Chen in combination with Kim and Yas further teaches the neuromorphic system of claim 4, wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the respective output line, to the membrane capacitor in response to the post- neuron signal output from the second signal generator. (As depicted in Figs 13 and 14:
PNG
media_image1.png
274
878
media_image1.png
Greyscale
PNG
media_image2.png
266
814
media_image2.png
Greyscale
And in [0089] Neurons 1002 and synapses 1008 may be interconnected such that neuromorphic processor 1000 operates to process or analyze information received by neuromorphic processor [wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the respective output line, to the membrane capacitor in response to the post- neuron signal output from the second signal generator]. In general, neurons 1002 may transmit an output pulse (or “fire” o “spike”) when inputs received through neuron input 1004 exceed a threshold. In some embodiments, neurons 1002 may sum or integrate signals received at neuron inputs 1004. For example, neurons 1002 may be implemented as leaky integrate-and-fire neuron. When this sum (referred to as a “membrane potential”) exceeds a threshold value, a neuron may generate an output (or “fire”) using a transfer function such as a sigmoid or threshold function. A leaky integrate and fire neuron may sum signals received at neuron inputs 1004 into a membrane potential [wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the respective output line, to the membrane capacitor in response to the post- neuron signal output from the second signal generator] and may also apply a decay factor (or leak) to reduce a membrane potential. Therefore a leaky integrate and fire neuron may fire only if multiple input signals are received at neuron inputs 1004 rapidly enough to exceed a threshold value (i.e. before a membrane potential decays too low to fire) . In some embodiments, neurons 1002 may be implemented using circuits or logic that receive inputs, integrate inputs into a membrane potential, and decay a membrane potential. In further embodiments, inputs may be averaged, or any other suitable transfer function may be used. Furthermore, neurons 1002 may include comparator circuits or logic that generate an output spike at neuron output 1006 when the result of applying a transfer function to neuron input 1004 exceeds a threshold. Once neuron 1002 fires, it may disregard previously received input information by, for example, resetting a membrane potential to 0 or another suitable default value. Once the membrane potential is reset to 0, neuron 1002 may resume normal operation after a suitable period of time (or refractory period)… [0090] Neurons 1002 may be interconnected through synapses 1008. Synapses 1008 may operate to transmit signals from an output of a first neuron 1002 to an input of a second neuron 1002. Neurons 1002 may transmit information over more than one instance of synapse 1008. In some embodiments, one or more instances of neuron output 1006 may be connected, via an instance of synapse 1008, to an instance of neuron input 1004 in the same neuron 1002. An instance of neuron 1002 generating an output to be transmitted over an instance of synapse 1008 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 1008 [wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the respective output line,..]. An instance of neuron 1002 receiving an input transmitted over an instance of synapse 1008 may be referred to as a “post-synaptic neuron” with respect to that instance of synapse 1008. Because an instance of neuron 1002 may receive inputs from one or more instances of synapse 1008, and may also transmit outputs over one or more instances of synapse 1008, a single instance of neuron 1002 may therefore be both a “pre-synaptic neuron” and “post-synaptic neuron,” with respect to various instances of synapses 1008…[0095] STDP module 1108 may operate to adjust synapse weights 1106. STDP module 1108 may receive packets from a pre-synaptic neuron or a post-synaptic neuron of synapse 1100. STDP module 1108 may parse these packets to identify instructions for adjusting synapse weight 1106. For example, synapse weight 1106 may be incremented or decremented by one. A positive or negative offset may be added to synapse weight 1106. The sign of synapse weight 1106 may be altered, or the synapse weight 1106 may be multiplied or otherwise scaled. STDP module 1108 and components thereof may be implemented using circuitry or logic [wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the respective output line, to the membrane capacitor in response to the post- neuron signal output from the second signal generator].)
Additionally:
Dan teaches wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the respective output line, to the membrane capacitor in response to the post- neuron signal output from the second signal generator, in in [0016] The “membrane potential” denotes the potential at the terminal of the membrane capacitor of the neuron [wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the respective output line, to the membrane capacitor in response to the post- neuron signal output from the second signal generator]. [0017] Preferably, the end transistor connected to VA.sub.out is a PMOS transistor and the end transistor connected to the membrane potential (V.sub.memB) of the post-neuron is an NMOS transistor… [0027] A learning circuit, called STDP (“spike timing dependent plasticity”, preferably including: [0028] Two field-effect transistors, preferably CMOS, even more preferably PMOS transistors, linked in series, the first transistor having the source connected to the output potential VB.sub.out of the post-neuron, the gate connected to a complementary state VB.sub.out bar of this potential and the drain connected to the source of the second transistor, whose drain is connected to a terminal of a first capacitor integrating the synaptic weight potential, the other terminal of this first capacitor being linked to ground, the drain of the second transistor supplying the analogue voltage V.sub.w analogue to the memory circuit, [0029] a third field-effect transistor, preferably CMOS, even more preferably PMOS, whose source is linked to the potential VA.sub.out of the pre-neuron], whose gate is linked to ground and whose drain is linked to a terminal of a second capacitor whose other terminal is linked to ground,… And as depicted in Fig 12A and in [0116] To express the STDP from an artificial point of view, FIG. 12A shows an example of a circuit 22 used to determine, at the point P1, the binary synaptic weight potential V.sub.w from the output voltages VA.sub.out and VB.sub.out of the pre-neuron and post-neuron, respectively [wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the respective output line, to the membrane capacitor in response to the post- neuron signal output from the second signal generator]. This circuit 22 comprises an STDP learning circuit 23 generating what is called an analogue synaptic weight potential V.sub.w analogue, which goes to the input of a SRAM-based memory circuit 24 in order to produce the binary synaptic weight potential V.sub.w.…
PNG
media_image7.png
358
634
media_image7.png
Greyscale
[0063] FIG. 2 schematically shows the interconnection between synapse and pre-neurons and post-neurons, … [0079] FIG. 2 illustrates the principle of interconnection between a synapse S and a pre-neuron Pre-N preceding it and a post-neuron Post-N following it. Such a neural circuit 1, supplied for example with a voltage V.sub.dd, forms the foundation of a neural network.
Kim expressly teaches wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the output line, to the membrane capacitor in response to the post-neuron signal output from the second signal generator; (As depicted in Fig. 1 and in [0043] … The first input signal may be a signal applied to a gate terminal of the transistor 116 [wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the output line, to the membrane capacitor in response to the post-neuron signal output from the second signal generator]. The second input signal may be a signal based on a membrane voltage applied to a source terminal of the transistor 116. The first input signal may be transmitted from the pre-synaptic neuron circuit A 130 [wherein the first transmission gate transmits the pre-neuron signal, which passes through the synapse unit and is output through the output line, …], and the second input signal may be transmitted from the post-synaptic neuron circuit B 150. And as depicted in Fig. 1 and in [0086] In the node n1 that is a membrane node of the post-synaptic neuron, the transistor {circle around (e)} and the transistor {circle around (a)} may be serially connected. Here, a source terminal of the transistor {circle around (a)} may be connected to the resting voltage source that supplies the resting voltage V.sub.rest while a source terminal of the transistor {circle around (e)} is connected to a capacitor Cmem [membrane capacitor] to which the membrane voltage is charged […, .the membrane capacitor in response to the post-neuron signal output from the second signal generator]…)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Kim, Park, Dan and Chen for the same reasons disclosed above.
Regarding claim 6, the rejection of claim 4 is incorporated and Kim further teaches the neuromorphic system of claim 4, wherein each of the first and second transmission gates comprises an n-channel metal oxide semiconductor (NMOS) transistor and a p-channel metal oxide semiconductor (PMOS) transistor of which drain and source terminals are connected to each other. (in [0015] The post-synaptic neuron circuit may include an N-metal oxide semiconductor (MOS) and a P-MOS transistor, the N-MOS transistor and the P-MOS transistor being serially connected [wherein each of the first and second transmission gates comprises an n-channel metal oxide semiconductor (NMOS) transistor and a p-channel metal oxide semiconductor (PMOS) transistor of which drain and source terminals are connected to each other], a resting voltage source to supply the resting voltage may be connected to a source terminal of the N-MOS transistor, and a capacitor may be connected to a source terminal of the P-MOS transistor…)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Kim, Park, Dan and Chen for the same reasons disclosed above.
Regarding claim 7, the rejection of claim 6 is incorporated and Dan further teaches the neuromorphic system of claim 6, a second inverter configured to invert the signal output from the first inverter and output the inverted signal to a gate terminal of the PMOS transistor of the first transmission gate; ([0022] The pre-neuron advantageously includes two inverters in cascade, called first and second conforming inverters, respectively generating the voltages VA.sub.out_bar and VA.sub.out…[0025] A memory cell, preferably SRAM, including two inverters, the input of one of which is connected to the output of the other, whose output is a connection point defining the binary synaptic weight potential, …; And in [0039] At least one of the pre-neuron and post-neuron may be of Morris-Lecar type, preferably including: [0040] a capacitor, called membrane capacitance, one of the terminals of which defines a membrane potential, [0041] a pulse feedback circuit including: [0042] a bridge of field-effect transistors, preferably CMOS, even more preferably PMOS and NMOS, in series and linked to the membrane potential by way of their drains, and [0043] at least one capacitor, called delay capacitor, between the gate and the source of one of the transistors of the bridge, and [0044] at least two field-effect inverters, preferably CMOS, in cascade, each one being formed of two transistors, the input of the first inverter being linked to the membrane capacitance and its output being linked to the input of the second inverter and to the gate of one of the transistors of the bridge, the output of the second inverter being linked to the gate of the other transistor of the bridge, or [0045] at least three field-effect inverters, preferably CMOS, two inverters of which are in cascade, each one being formed of two transistors, the input of the first inverter being linked to the membrane capacitance and its output being linked to the input of the second inverter, the output of the second inverter being linked to the gate of one of the transistors of the bridge, the input of the third inverter being linked to the membrane capacitance and the output of the third CMOS inverter being linked to the gate of the other transistor of the bridge. )
and a buffer configured to output the post-neuron signal output from the second signal generator to a gate terminal of the NMOS transistor of the second transmission gate. (in [0025] A memory cell, preferably SRAM, including two inverters, the input of one of which is connected to the output of the other, whose output is a connection point defining the binary synaptic weight potential, [0026] Two field-effect transistors, preferably CMOS, even more preferably NMOS, whose drain-source channels are in series, receiving the analogue voltage V.sub.W analogue on the gate of one of them, and the drain or the source thereof defining the input of the memory cell, and receiving the output potential VB.sub.out of the post-neuron on the gate of the other transistor. [0027] A learning circuit, called STDP (“spike timing dependent plasticity”), preferably including: [0028] Two field-effect transistors, preferably CMOS, even more preferably PMOS transistors, linked in series, the first transistor having the source connected to the output potential VB.sub.out of the post-neuron, the gate connected to a complementary state VB.sub.out bar of this potential and the drain connected to the source of the second transistor, whose drain is connected to a terminal of a first capacitor integrating the synaptic weight potential, the other terminal of this first capacitor being linked to ground, the drain of the second transistor supplying the analogue voltage V.sub.w analogue to the memory circuit, …; Examiner notes claimed buffer as recited memory cell/circuit)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Dan and Chen for the same reasons disclosed above.
Regarding claim 9, the rejection of claim 1 is incorporated and Chen in combination with Dan and Park further teaches the neuromorphic system of claim 1, wherein the pre-neuron signal or the post-neuron signal has a square-wave form, a triangular-wave form or a sawtooth-wave form. (in [0089] Neurons 1002 and synapses 1008 may be interconnected such that neuromorphic processor 1000 operates to process or analyze information received by neuromorphic processor. In general, neurons 1002 may transmit an output pulse (or “fire” o “spike”) when inputs received through neuron input 1004 exceed a threshold. In some embodiments, neurons 1002 may sum or integrate signals received at neuron inputs 1004. For example, neurons 1002 may be implemented as leaky integrate-and-fire neuron. When this sum (referred to as a “membrane potential”) exceeds a threshold value, a neuron may generate an output (or “fire”) using a transfer function such as a sigmoid or threshold function. A leaky integrate and fire neuron may sum signals received at neuron inputs 1004 into a membrane potential and may also apply a decay factor (or leak) to reduce a membrane potential. Therefore a leaky integrate and fire neuron may fire only if multiple input signals are received at neuron inputs 1004 rapidly enough to exceed a threshold value (i.e. before a membrane potential decays too low to fire)…)
While one of ordinary skill in the art would understand that the input pulse can take wave forms, Chen does not expressly recite the types of waveforms.
Kim does expressly recite the types of waveforms including wherein the pre-neuron signal or the post-neuron signal has a square-wave form, a triangular-wave form or a sawtooth-wave form. As depicted in Fig. 1
PNG
media_image8.png
550
542
media_image8.png
Greyscale
One of ordinary skill in the arts would have been motivated to combine the disclosed methods disclosed by Kim, Park, Dan and Chen above. Doing so allowing for implementing a synapse circuit configured to receive at least two input signal to update and modify a resistance value of the memristor based on a time difference between the at least two input signals received by the transistor, (Kim, Abstract). This allow for implementing a spiking neural network designed to mimic the operation of biological nervous system, (Kim, 0006).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Dan, Park and Kim in further view of Friedman et al. (US 20210232903, hereinafter ‘Fried’).
Regarding claim 8, the rejection of claim 2 is incorporated and Fried teaches the neuromorphic system of claim 2, further comprising a lateral inhibition circuit configured to inhibit, when the post-neuron signal is generated from any one of the STDP control blocks connected to one of the output lines among the STDP control blocks, driving of the second signal generators of the other STDP control blocks connected to the other output lines so that no post-neuron signal is generated by the other STDP control blocks connected to the other output lines. (in [0074] The development of a hardware neural network requires artificial neurons and synapses that intrinsically function in a manner analogous to their biological analogs. In order to enable fabrication that is compatible with conventional processes, a synapse crossbar array connects the neurons. In order to emulate biological processes and implement the winner-take-all schemes involved in many machine learning techniques, these neurons must provide lateral inhibition [further comprising a lateral inhibition circuit configured to inhibit, when the post-neuron signal is generated from any one of the STDP control blocks connected to one of the output lines among the STDP control blocks, driving of the second signal generators of the other STDP control blocks connected to the other output lines so that no post-neuron signal is generated by the other STDP control blocks connected to the other output lines], which is achieved here by adapting the DW-MTJ device… [0080] Lateral inhibition is a process that allows an excited neuron to inhibit [further comprising a lateral inhibition circuit configured to inhibit, when the post-neuron signal is generated from any one of the STDP control blocks connected to one of the output lines among the STDP control blocks, driving of the second signal generators of the other STDP control blocks connected to the other output lines so that no post-neuron signal is generated by the other STDP control blocks connected to the other output lines], or reduce, the activity of other nearby or connected neurons [further comprising a lateral inhibition circuit configured to inhibit, when the post-neuron signal is generated from any one of the STDP control blocks connected to one of the output lines among the STDP control blocks, driving of the second signal generators of the other STDP control blocks connected to the other output lines so that no post-neuron signal is generated by the other STDP control blocks connected to the other output lines.]. One such neural computing system that seeks to take advantage of this is the winner-take-all system. As a form of competitive learning, artificial neurons contend for activation, meaning that only one neuron is chosen as the winner and allowed to fire, using lateral inhibition to suppress the output of all other neurons. After the winning neuron fires, the system is reset and the neurons once again compete for activation. A winner-take-all system is one of the many machine learning paradigms that take advantage of the lateral inhibition phenomenon, which is commonly used in recognition and modeling processes. And in[0148] The process of updating weights in a neural network is called learning. Depending on the presence of a teacher signal, learning can be classified into the categories of supervised, unsupervised, and semi-supervised methods. In another aspect of the present invention, a primitive circuit for unsupervised learning is further disclosed as will be shown in reference to FIGS. 23, 24 and 25. Without limitation, this primitive circuit can be co-integrated with other learning sub-systems. The present invention implements unsupervised learning as an electrical approximation of Hebbian (associative) learning, which can be efficiently implemented via the spike-timing dependent plasticity (STDP) rule… )
Park teaches the plurality of lines connected using synapse circuits/units in a crossbar array as depicted in Fig. 1 and noted in claim 1 rejection.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Kim, Park, Dan and Chen for the same reasons disclosed above.
Fried, Kim, Park, Dan and Chen are analogous art because both involve developing information retrieval and processing techniques for synaptic learning in a spiking neural network (SNN)-based neuromorphic architectures and models.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art for developing circuits for implementing neuromorphic crossbar arrays suitable for on-chip competitive learning, as disclosed by Fried with the method of developing information retrieval and processing system for event-driven learning with spike timing dependent plasticity in neuromorphic computers as collectively disclosed by Kim, Park, Dan and Chen.
One of ordinary skill in the arts would have been motivated to combine the disclosed methods disclosed by Fried, Kim, Park, Dan and Chen, as noted above. Doing so allows an excited neuron to inhibit, or reduce, the activity of other nearby or connected neuron, (Fried, 0080).
Response to Arguments
Applicant's arguments filed 3/14/2026 have been fully considered.
Regarding the rejection of claims under 35 USC 102 and 103, applicant remarks are directed to amended limitations that have not been previously considered by the examiner. See current office action above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (NPL: Hardware implementation of neuromorphic computing using large‐scale memristor crossbar arrays): teaches In most ANNs, the neuron functions are either implemented by CMOS circuits composed of 10 or more transistors or in software running on the processors, which limit its further improvements on scalability, stack ability, and energy efficiency. In recent years, memristor-based artificial neurons have been developed. Most ANNs are implemented with memristive synapses and a capacitor in parallel to the memristor implements the integration effect via the charging process.
Yasuda et al. (US 11188815): teaches term driver and generator, in 4:62-5:22: … All axons 20 connect to pre-synaptic neurons 40 at one respective end of each of the axons. All dendrites 30 connect to post-synaptic neurons 50 at one respective end of each of the dendrites. Each one of such ends may be referred to as an input end and an output end respectively…. All columns 30 may connect to post-synaptic neurons 50 through the activation-function-simulated-circuits (not shown). Also, the circuits may be included in the post-synaptic neurons. The neuromorphic array enables interfacing with the post-synaptic neurons downstream and with the pre-synaptic neurons upstream. The pre-synaptic neurons and the post-synaptic neurons are implemented for handling input data from upstream and output data downstream. The pre-synaptic neurons may include I/O drivers [including claimed driver] having DAC (digital to analog converter). The post-synaptic neurons may include I/O drivers [including claimed driver configured to output the post-neuron signal output having/connected to claimed transmission gate configured to transmit the post-neuron signal output from the second driver to the output line in response to the post-neuron signal output from the second signal generator] having ADC (analog to digital converter) a second driver configured to output the post-neuron signal output from the second signal generator to the synapse unit through the output line; and a second transmission gate configured to transmit the post-neuron signal output from the second driver to the output line in response to the post-neuron signal output from the second signal generator]…9:63-10:23: …(45) FIG. 10 shows an exemplary circuit of neuromorphic synapse array implemented with a pulse modulator (PM) according to an embodiment of the present invention. The output, or analog signals of the reference column array 16 is converted to a digital signal through ADC (Analog-Digital Converter) 1020. Each of the output ends 1005 of the operation column arrays 11 are split into two lines. Each line out of the split lines is connected to a capacitor 1040 to generate potential outputs 1070. Each of the lines passes down the output 1070 to the activation function (FIG. 1) outside the array 100. Activation-function-simulated-circuits may be embedded with the neuromorphic array to compose a neuromorphic core. The activation functions generate outputs of the neuromorphic core as inputs of subsequent neuromorphic cores. Another line of each of the outputs is used to subtract an equivalent amount of the output of the reference column array from all the outputs of the operation column arrays. Another line includes a transistor connected to a ground 1050. The transistor is switched by the digital signal dependent on the output or an analog current of the reference column array to pull the equivalent current to the ground. The PM or the pulse generator (PG) generates a pulse signal from the digital signal through the ADC in Pulse Width Modulate (PWM), Pulse Amplitude Modulate (PAM), and Pulse Number Modulate (PNM) schemes. The pulse signal is applied to a transistor at the output ends of the operation column arrays… 11:4-12: … ) FIG. 12 shows an exemplary result of a single synaptic weight model according to an embodiment of the present invention. There are comparisons of simulation results among three cases of a bipolar, unipolar, and constant synaptic weight model, which are conducted using MNIST benchmark data. The result shows that error rates of MNIST are reduced as compared with the case of assigning the average of initial weights to the reference synapse cells before learning phase […the post-neuron signal available for synaptic learning and output the post-neuron signal]…; And in 5:38-51: The NVM based neuromorphic array 100 represents one possibility for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. Especially some advances are reported in the NVM based implementation to two computing paradigms such as spiking neural network (SNN) and deep neural network (DNN). In SNN, NVM-based synaptic connections are updated by a local learning rule such as spike-timing-dependent-plasticity (STDP) […signal generator configured to transform the post-neuron spike output from the post-synaptic neuron into the post-neuron signal available for synaptic learning] to practice a computational approach directly inspired by biology. For DNN, NVM-based arrays can also represent matrices of synaptic weights, implementing the multiply-accumulate (MAC), or the product-sum operation needed for algorithms such as backpropagation in an analog yet massively-parallel fashion.
Han et al. (NPL: “A Vertical Silicon Nanowire Based Single Transistor Neuron with Excitatory, Inhibitory, and Myelination Functions for Highly Scalable Neuromorphic Hardware”): teaches neuromorphic computing architecture has attracted considerable attention, as it can overcome bottlenecks such as a memory wall introduced in conventional von-Neumann computing.[1–5] Neuromorphic hardware includes an artificial neuron, which is a computational element to transfer information through discrete spikes by mimicking a biological neuron. The basic function of a biological neuron follows a leaky integrate-and fire (LIF) mechanism.[6–8] The neuron receives signals from previous synapses, and an output action voltage is produced when the membrane voltage reaches a threshold.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OLUWATOSIN ALABI whose telephone number is (571)272-0516. The examiner can normally be reached Monday-Friday, 8:00am-5:00pm EST..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Huntley can be reached at (303) 297-4307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/OLUWATOSIN ALABI/ Primary Examiner, Art Unit 2129
Prosecution Insights