Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The amendment filed on March 4, 2026 has been received and entered.
Applicant’s Amendments to the Claims have been received and acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mozak et al. (U.S. Publication No. 2015/0066819 A1), hereafter referred to as Mozak’819.
Referring to claim 1, Mozak’819 as claimed, an apparatus comprising: a data (DQ) path of a physical interface (PHY) (Figs. 2-4) of a host device of a memory subsystem (data received on the data line, DQ 530, see paras. [0058] and Fig. 5) to connect to a memory device (both the device 210 or device 220 can be the transmitting/receiving device; delay changes can be compensated by changing the transmit behavior of the transmitter device. In one embodiment, the receiver device can compute the I/O adjustment needed. In one embodiment, the receiver device simply sends raw data to the transmitter, which can then compute an I/O adjustment based on the detected change, see paras. [0029]-[0033], [0066]; also note: One example that device 210 is a memory controller or processor and device 220 is a memory device, see para. [0034]); a data strobe (DQS) path of the PHY (DQS path, see paras. [0005], [0006], [0022], [0058]) of the host device, wherein delay propagation of analog signals in the DQS path and the DQ path is mismatched (measure tDQS delay (the propagation delay of the data strobe signal) and adjust the timing to compensate for the changes in the delay, see para. [0034]; also note: unmatched architectures, see paras. [0028], [0030], and [0041]); and a digital component in the PHY to receive a control signal from the host device (logic 444 represents control logic at memory controller, which can determine what parameter or parameters to adjust to compensate for drift as indicated by periodic training I/O controller 440 can include sampling circuitry to sample the receive signals, see paras. [0048]-[0050]) to introduce a delay compensation in operation of the digital component to compensate for delay propagation mismatch between the DQS path and the DQ path (identify drift in the strobe signal relative to the data signal. Periodic compensation track and compensate for drift in TDQS., see paras. [0022], [0027]-[0033]).
As to claim 2, Mozak’819 also discloses the digital component comprises a component in the DQ path (During periodic training, the control logic detects how much the DQ edge moves relative to a previously stored value. Based on how much the edge moved, the control logic can determine how to offset the DQ center value., see paras. [0022], [0024], [0042], [0043], and [0058]).
As to claim 3, Mozak’819 also discloses the digital component comprises a first in first out (FIFO) buffer (buffer, see paras. [0052], [0066], [0070], and [0084]).
As to claim 4, Mozak’819 also discloses the FIFO buffer comprises a read buffer (buffer, see paras. [0052], [0066], [0070], and [0084]; also note: read, see paras. [0047], [0050], [0052], [0066], [0070], and [0084]).
As to claim 5, Mozak’819 also discloses the FIFO buffer comprises a write buffer (buffer, see paras. [0052], [0066], [0070], and [0084]; also note: write/store, see paras. [0037], [0047], [0050], [0052], [0066], [0070], and [0084]).
As to claim 6, Mozak’819 also discloses the digital component comprises a first FIFO buffer and a second FIFO buffer (buffer, see paras. [0052], [0066], [0070], and [0084]; also note: registers, see paras. [0037], [0050]).
As to claim 7, Mozak’819 also discloses a swap control circuit to selectively reorder data readout from the first FIFO buffer and the second FIFO buffer based on introduction of odd or even units of delay compensation (Even vs. Oddmode, see para. [0024]).
As to claim 8, Mozak’819 also discloses the digital component comprises a component in the DQS path (DQS path, see paras. [0005], [0006], [0022], [0058]).
As to claim 9, Mozak’819 also discloses the digital component comprises a shifter (LFSR (linear shift feedback register), see para. [0024]).
As to claim 10, Mozak’819 also discloses the digital component comprises a first in first out (FIFO) buffer (buffer, see paras. [0052], [0066], [0070], and [0084]; also note: write/store, see paras. [0037], [0047], [0050], [0052], [0066], [0070], and [0084]), and wherein to introduce the delay compensation in operation of the FIFO buffer comprises to adjust a write pointer to the FIFO buffer for a write transaction (adjust I/O parameters of transmission and/or reception for transceiver to compensate for delay, see Figs. 6A-B and paras. [0027], [0040], [0048] and determine if data edge should be incremented or decremented, see para. [0053]).
As to claim 11, Mozak’819 also discloses the digital component comprises a first in first out (FIFO) buffer (buffer, see paras. [0052], [0066], [0070], and [0084]; also note: reads, see paras. [0047], [0050], [0052], [0066], [0070], and [0084]), and wherein to introduce the delay compensation in operation of the FIFO buffer comprises to adjust a read pointer to the FIFO buffer for a read transaction (adjust I/O parameters of transmission and/or reception for transceiver to compensate for delay, see Figs. 6A-B and paras. [0027], [0040], [0048] and determine if data edge should be incremented or decremented, see para. [0053]).
As to claim 12, Mozak’819 also discloses the delay compensation comprises a delay (for each of the multiple different settings for multiple different I/O circuit parameters, the system set a value for each I/O circuit parameter…determine values for each I/O circuit parameter at which the delay is compensated, see para. [0027] and Fig. 3) in increments of a unit interval (Ul) (unit interval, see para. [0005]; also note: determine if data edge should be incremented or decremented, see para. [0053]).
As to claim 13, Mozak’819 also discloses an analog delay circuit to adjust for delay of less than one UI (adjusting timing to compensate for changes in the delay, paras. [0022], [0027]-[0035].
Referring to claim 14, Mozak’819 as claimed, a system, comprising: a memory controller (memory controller, see paras. [0028], [0034], [0050], see Figs. 2 and 4, device 210); a memory device (memory device, see paras. [0021], [0022], [0025], [0026], [0028], Figs. 2 and 4, device 220 420); and a physical interface (PHY) of the memory controller (both the device 210 or device 220 can be the transmitting/receiving device; delay changes can be compensated by changing the transmit behavior of the transmitter device. In one embodiment, the receiver device can compute the I/O adjustment needed. In one embodiment, the receiver device simply sends raw data to the transmitter, which can then compute an I/O adjustment based on the detected change, see paras. [0029]-[0033], [0066]; also note: One example that device 210 is a memory controller or processor and device 220 is a memory device, see para. [0034]; logic 444 represents control logic at memory controller, which can determine what parameter or parameters to adjust to compensate for drift as indicated by periodic training I/O controller 440 can include sampling circuitry to sample the receive signals, see paras. [0048]-[0050]) to couple the memory controller to the memory device (Figs. 2-4), the PHY having a mismatched architecture (unmatched architectures, see paras. [0028], [0030], and [0041]), including: a data (DQ) path (data received on the data line, DQ 530, see paras. [0058] and Fig. 5); a data strobe (DQS) path (DQS path, see paras. [0005], [0006], [0022], [0058]), wherein delay propagation of analog signals in the DQS path and the DQ path is mismatched (measure tDQS delay (the propagation delay of the data strobe signal) and adjust the timing to compensate for the changes in the delay, see para. [0034]); and a digital component to receive a control signal to introduce a delay compensation in operation of the digital component to compensate for delay propagation mismatch between the DQS path and the DQ path (identify drift in the strobe signal relative to the data signal. Periodic compensation track and compensate for drift in TDQS., see paras. [0022], [0027]-[0033]).
Note claims 15 and 21 recite similar limitations of claims 2 and 3. Therefore they are rejected based on the same reason accordingly.
Note claims 16 and 22 recite similar limitations of claims 8 and 9. Therefore they are rejected based on the same reason accordingly.
As to claim 17, Mozak’819 also discloses the PHY comprises a physical interface circuit of the memory controller (memory controller, see paras. [0028], [0034], [0050], see Figs. 2-4, device 210).
As to claim 18, Mozak’819 also discloses the PHY comprises a physical interface circuit of the memory device (memory device, see paras. [0021], [0022], [0025], [0026], [0028], Figs. 2-4, device 220 420).
As to claim 19, Mozak’819 also discloses one or more of: a multicore host processor coupled to the memory controller (processor, see para. [0067], Figs. 7 and 8); a display communicatively coupled to a host processor (display subsystem 830, see Fig. 8); a network interface communicatively coupled to a host processor (network interface 750, see Fig. 7); or a battery to power the system (power management 850, see Fig. 8).
Note claim 20 recites similar limitations of claims 1 and 14. Therefore it is rejected based on the same reason accordingly.
Response to Arguments
Applicant's arguments filed 3/4/2026 have been fully considered but they are not persuasive.
At the outset, Applicants are reminded that claims subject to examination will be given their broadest reasonable interpretation consistent with the specification. In re Morris, 127 F.3d 1048, 1054-55 (Fed. Cir. 1997). In fact, the "examiner has the duty of police claim language by giving it the broadest reasonable interpretation." Springs Window Fashions LP v. Novo Industries, L.P., 65 USPQ2d 1862, 1830, (Fed. Cir. 2003). Applicants are also reminded that claimed subject matter not the specification, is the measure of the invention. Disclosure contained in the specification cannot be read into the claims for the purpose of avoiding the prior art. In re Sporck, 55 CCPA 743, 386 F.2d, 155 USPQ 687 (1986).
With this in mind, the discussion will focus on how the terms and relationships thereof in the claims are met by the references. Response to any limitations that are not in the claims or any arguments that are irrelevant and/or do not relate to any specific claim language will not be warranted.
Applicant argued that “Mozak’819 describes a system that has an unmatched architecture, and provides training compensation in the memory device. One skilled in the art will understand that there is a significant cost increase for the memory device to provide delay compensation for each DQ.” (Page 6 of Applicant’s Amendment)
Examiner does not agree with Applicant. As set forth in the art rejection, Mozak’819 discloses a data (DQ) path of a physical interface (PHY) (Figs. 2-4) of a host device of a memory subsystem (data received on the data line, DQ 530, see paras. [0058] and Fig. 5) to connect to a memory device (both the device 210 or device 220 can be the transmitting/receiving device; delay changes can be compensated by changing the transmit behavior of the transmitter device. In one embodiment, the receiver device can compute the I/O adjustment needed. In one embodiment, the receiver device simply sends raw data to the transmitter, which can then compute an I/O adjustment based on the detected change, see paras. [0029]-[0033], [0066]; also note: One example that device 210 is a memory controller or processor and device 220 is a memory device, see para. [0034]); a data strobe (DQS) path of the PHY (DQS path, see paras. [0005], [0006], [0022], [0058]) of the host device, wherein delay propagation of analog signals in the DQS path and the DQ path is mismatched (measure tDQS delay (the propagation delay of the data strobe signal) and adjust the timing to compensate for the changes in the delay, see para. [0034]; also note: unmatched architectures, see paras. [0028], [0030], and [0041]); and a digital component in the PHY to receive a control signal from the host device (logic 444 represents control logic at memory controller, which can determine what parameter or parameters to adjust to compensate for drift as indicated by periodic training I/O controller 440 can include sampling circuitry to sample the receive signals, see paras. [0048]-[0050]) to introduce a delay compensation in operation of the digital component to compensate for delay propagation mismatch between the DQS path and the DQ path (identify drift in the strobe signal relative to the data signal. Periodic compensation track and compensate for drift in TDQS., see paras. [0022], [0027]-[0033]).
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
In summary, Mozak’819 teaches the claimed limitations as set forth.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Contact Information
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/TITUS WONG/Primary Examiner, Art Unit 2181