Prosecution Insights
Last updated: October 27, 2026
Application No. 17/874,345

heat dissipation and electrical robustness in a three-dimensional package of stacked integrated circuits

Final Rejection §102§103
Filed
Jul 27, 2022
Priority
Jul 29, 2021 — provisional 63/227,185
Examiner
PAGE, DALE E
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Marvell Asia Pte. Ltd.
OA Round
2 (Final)
65%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 65% — above average
65%
Career Allowance Rate
217 granted / 333 resolved
-2.8% vs TC avg
Moderate +7% lift
Without
With
+7.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
4 currently pending
Career history
338
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.5%
+13.5% vs TC avg
§102
27.1%
-12.9% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 333 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1,2,7, 9-10,13,15,16,17,22, 24-25,28,30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koopmans et al. (U.S. Publication 20150279828) Regarding Claim 1, Koopmans teaches an electronic device, comprising: a substrate; (Fig.5, substrate 530) a stack of dies stacked on the substrate, (Fig. 5 die stack 105) the stack comprising: one or more functional dies, ([0017] disclosing die stack to be functional dies) having a major plane defined by at least first and second axial dimensions of the one or more functional dies,(Fig. 1 shows die stack 105 containing dimensions in the “x” and “y” axis) the functional dies (Fid. 5 dies 105) comprising functional electronic circuits ([0017] disclosing dies containing integrated circuits) and being configured to exchange electrical signals at least with the substrate; (Fig. 5 and [0017] disclosing each functional die 102 has a substrate that is configured to exchange electrical signals through interconnects 106 from Fig. 5) one or more dummy dies, (Fig .5 dummy die interposer 120) a lid (Fig. 1, lid cover 112) configured to encapsulate at least part of the stack,(Fig. 1 shows 112 does encapsulate the die stack 105) and to dissipate heat from the electronic device (Fig. 1 and [0011], disclose cover 112 as part of the casing 110 and casing 110 is being used to dissipate heat from the dies), the lind having at least one opening(Fig. 1, an opening space between dummy die 120 and lid 112); and the dummy dies being disposed among the one or more functional dies forming the stack (Fig. 5 showing dummy die 120 disposed “among” the die stack 105) and being configured to: (i) dissipate heat generated by the one or more functional dies (Fig. 5 shows dummy die 120 is thermally conductive to casing 110 through interface 115a from die stack 105) and (ii) pass electrical signals exchanged between the substrate and the one or more functional dies or between two or more of the functional dies. (Fig. 5, [0014] disclose dummy die 120 to be electrically connected to die stack 105), wherein a portion of at least one of the dummy dies extends laterally beyond an edge of the stack , (Fig. 1, also shows dummy die 120, within the “x” axis is longer than the “x” axis dimension of die stack 105) and through the at least one opening in the lid (Fig. 1, opening part between die 120 and lid 112 is extending laterally through) to form a direct thermal coupling with an environment outside the lid (Fig. 1 shows that dummy 120 is thermally connected to the lid 112 through a TIM layer 115a, [0012]. It is noted here that “direct thermal coupling” does not limit the thermal coupling occurring through additional physical structure since “direct thermal coupling” does not preclude intervening layers as long as “coupling” occurs. For example, a TIM layer can be present between two layers and those two layers would still be in direct thermal “coupling”) Regarding Claim 2, Koopmans teaches the electronic device according to claim 1, and further discloses wherein the at least one of the dummy dies (Fig. 1 die 120) comprises first (fig. 1 first metal layer 123, right and left side of die stack 105) and second metal layers (Fig. 1 second metal layers 125) which are: (i) electrically disconnected from one another by a dielectric layer, (Fig. 1, layers 123 are shown to be disconnected from reach other, ¶0018 indicates that layer 120 which layers 123 are disposed in is AlO which is a dielectric) (ii) electrically coupled, respectively, to first and second electrical connections of the electronic device (Fig. 1, metal layers 123 and 125 are also acting as the electrical connection of the electronic device) and (iii) configured to dissipate at least part of the heat generated by at least one of the functional dies. (Metal layer 123 and 125 are made from conductive materials and therefore will also contain thermal conductivity properties to help dissipate at least part of the heat produced from the function die) Regarding Claim 7, Koopmans teaches the electronic device according to claim 1, and further discloses wherein the dummy dies comprise a first dummy die having a first axial dimension of the first dummy die,(Fig. 1 shows die stack 105 containing dimensions in the “x” and “y” axis) which is larger than the first axial dimension of the functional dies, (Fig. 1, also shows dummy die 120, within the “x” axis is longer than the “x” axis dimension of die stack 105) and a second dummy die (Fig. 4, dummy die support 445) having a second axial dimension (Fig. 4 dimension within the “y” axis), which is larger than the second axial dimension of the functional dies. (Fig. 4 shows that support 445 is vertically larger than one of the functional dies 102) Regarding Claim 9, Koopmans teaches the electronic device according to claim 1, and further discloses wherein the portion of the at least one of the dummy dies is thermally coupled to the lid at the opening. (Fig. 1 shows that dummy 120 is thermally connected to the lid 112 through a TIM layer 115a, [0012]) Regarding Claim 10, Koopmans teaches the electronic device according to claim 9, and further discloses comprising a thermal interface material (TIM) (Fig. 1 interface 115A) disposed between the lid (Fig. 1, 112) and the portion of the at least one of the dummy dies, (Fig. 1, showing interface 115a between dummy die 120 and lid 112) the TM configured to thermally couple between the lid and the portion of one of the dummy dies ([0012], discloses the use of 115a to be thermally couple the dummy die 120 to lid 112) Regarding Claim 13, Koopmans teaches the electronic device according to claim 1, and further teaches wherein at least one of the dummy dies comprises a semiconductor substrate. ([0018] disclosing dummy die 120 is a semiconductor substrate) Regarding Claim 15, Koopmans teaches the electronic device according to claim 1, and further teaches wherein at least one of the dummy dies comprises a ceramic substrate. ([0018] disclosing dummy die 120 is a ceramic substrate) Regarding Claim 16, Koopmans teaches a method for producing an electronic device, the method comprising: disposing, on a substrate (Fig.5, substrate 530) a stack of dies, (Fig. 5 die stack 105) the stack comprising one or more functional dies, ([0017] disclosing die stack to be functional dies) having a major plane defined by at least first and second axial dimensions (Fig. 1 shows die stack 105 containing dimensions in the “x” and “y” axis) the functional dies (Fid. 5 dies 105) comprising functional electronic circuits ([0017] disclosing dies containing integrated circuits) for exchanging electrical signals at least with the substrate; (Fig. 5 and [0017] disclosing each functional die 102 has a substrate that is configured to exchange electrical signals through interconnects 106 from Fig. 5) disposing, over the stack of dies, a lid (Fig. 1, lid cover 112) configured to encapsulate at least part of the stack,(Fig. 1 shows 112 does encapsulate the die stack 105) and to dissipate heat from the electronic device (Fig. 1 and [0011], disclose cover 112 as part of the casing 110 and casing 110 is being used to dissipate heat from the dies), the lid having at least one opening (Fig. 1, an opening space between dummy die 120 and lid 112); and disposing, on the substrate among the one or more functional dies forming the stack, one or more dummy dies (Fig .5 dummy die interposer 120) for:(i) dissipating heat generated by the one or more functional dies, (Fig. 5 shows dummy die 120 is thermally conductive to casing 110 through interface 115a from die stack 105) (ii) passing electrical signals exchanged between the substrate and the one or more functional dies or between two or more of the functional dies, (Fig. 5, [0014] disclose dummy die 120 to be electrically connected to die stack 105) wherein a portion of at least one of the dummy dies extends laterally beyond an edge of the stack , (Fig. 1, also shows dummy die 120, within the “x” axis is longer than the “x” axis dimension of die stack 105) and through the at least one opening in the lid (Fig. 1, opening part between die 120 and lid 112 is extending laterally through) to form a direct thermal coupling with an environment outside the lid (Fig. 1 shows that dummy 120 is thermally connected to the lid 112 through a TIM layer 115a, [0012]. It is noted here that “direct thermal coupling” does not limit the thermal coupling occurring through additional physical structure since “direct thermal coupling” does not preclude intervening layers as long as “coupling” occurs. For example, a TIM layer can be present between two layers and those two layers would still be in direct thermal “coupling”) Regarding Claim 17, the method according to claim 16, comprising, forming in the at least one of the dummy dies (Fig. 1 die 120), first (fig. 1 first metal layer 123, right and left side of die stack 105) and second metal layers (Fig. 1 second metal layers 125), which are (i) electrically disconnected from one another by a dielectric layer (Fig. 1, layers 123 are shown to be disconnected from reach other since element 120 is indicated in ¶0018 to be AlO which is a dielectric), and (ii) electrically coupled, respectively, to first and send electrical connections of the electronic device (Fig. 1, metal layers 123 and 125 are also acting as the electrical connection of the electronic device) for dissipating at least part of the heat generated by at least one of the functional dies (Metal layer 123 and 125 are made from conductive materials and therefore will also contain thermal conductivity properties to help dissipate at least part of the heat produced from the function die) Regarding Claim 22, The method according to claim 16, wherein selecting the dummy dies comprises selecting a first dummy die having a first axial dimension,(Fig. 1 shows die stack 105 containing dimensions in the “x” and “y” axis) which is larger than the first axial dimension of the functional dies, (Fig. 1, also shows dummy die 120, within the “x” axis is longer than the “x” axis dimension of die stack 105) and selecting a second dummy die (Fig. 4, dummy die support 445) having a second axial dimension, (Fig. 4 dimension within the “y” axis) which is larger than the second axial dimension of the functional dies. . (Fig. 4 shows that support 445 is vertically larger than one of the functional dies 102) Regarding Claim 24, The method according to claim 23, wherein the portion of the at least one of the dummy dies is thermally coupled to the lid at the opening. (Fig. 1 shows that dummy 120 is thermally connected to the lid 112 through a TIM layer 115a, [0012]) Regarding Claim 25, The method according to claim 24, comprising disposing a thermal interface material (TIM) (Fig. 1 interface 115A) between the lid (Fig. 1, 112) and the portion of the at least one of the dummy dies for thermally coupling between the lid and the portion of one of the dummy dies. ([0012], discloses the use of 115a to be thermally couple the dummy die 120 to lid 112) Regarding Claim 28, Koopmans teaches the method according to claim 16, wherein disposing the one or more dummy dies comprises disposing at least one of the dummy dies having a semiconductor substrate. ([0018] disclosing dummy die 120 is a semiconductor substrate) Regarding Claim 30, Koopman teaches the method according to claim 16, wherein disposing the one or more dummy dies comprises disposing at least one of the dummy dies having a ceramic substrate. ([0018] disclosing dummy die 120 is a semiconductor substrate) Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3-4,18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koopmans in view of Karp (U.S. Patent 11398469) Regarding Claim 3, Koopmans teaches electronic device according to claim 2, and further teaches wherein the first electrical connections comprise one or more power rails electrically coupled to the first metal layer, (Fig. 1 first metal layer 123, as being part of an electrical circuit device with inherently need power and would have to have power and ground connected to the circuit) wherein the second electrical connections comprise one or more ground rails electrically coupled to the second metal layer, (Fig. 1 first metal layer 125, as being part of an electrical circuit device with inherently need power and would have to have power and ground connected to the circuit) and wherein the first and second metal layers form a structure. Koopmans fails to disclose an intra-stack capacitor for mitigating electrostatic discharge (ESD) effects within the electronic device. However, Karp teaches an intra-stack capacitor (Fig. 3, element 362-2, capacitor within a die stack 102,104,106,108) for mitigating electrostatic discharge (ESD) effects within the electronic device. (Colm. 11 lines 25-45, stating the capacitor is used for power supply ESD mitigation). It would have been obvious to a person of skill in the art at the time of the effective filing date to add the capacitor of Karp for the first and second metal layer of Koopmans to provide proper ESD mitigation within the electronic device. Regarding Claim 4, Koopmans teaches the electronic device according to claim 2, and further teaches a first and second metal layers,(Fig. 1, metal layers 123 and 125) Koopmans fails to disclose an intra-stack capacitor configured to supply power to at least one of the functional dies. However, Karp teaches an intra-stack capacitor (Fig. 3, element 362-2, capacitor within a die stack 102,104,106,108) for mitigating electrostatic discharge (ESD) effects within the electronic device. (Colm. 11 lines 25-45, stating the capacitor is used for power supply ESD mitigation). It would have been obvious to a person of skill in the art at the time of the effective filing date to add the capacitor of Karp for the first and second metal layer of Koopmans to provide proper ESD mitigation within the electronic device. Regarding Claim 18, Koopmans teaches the method according to claim 17, wherein the first electrical connections comprise one or more power rails electrically coupled to the first metal layer, (Fig. 1 first metal layer 123, as being part of an electrical circuit device with inherently need power and would have to have power and ground connected to the circuit) wherein the second electrical connections comprise one or more ground rails electrically coupled to the second metal layer, (Fig. 1 first metal layer 125, as being part of an electrical circuit device will inherently need power and would have to have power and ground connected to the circuit) and wherein forming the first and second metal layers comprises forming a structure. Koopmans fails to disclose an intra-stack capacitor for mitigating electrostatic discharge (ESD) effects within the electronic device. However, Karp teaches an intra-stack capacitor (Fig. 3, element 362-2, capacitor within a die stack 102,104,106,108) for mitigating electrostatic discharge (ESD) effects within the electronic device. (Colm. 11 lines 25-45, stating the capacitor is used for power supply ESD mitigation). It would have been obvious to a person of skill in the art at the time of the effective filing date to add the capacitor of Karp for the first and second metal layer of Koopmans to provide proper ESD mitigation within the electronic device. Regarding Claim 19, The method according to claim 17, wherein forming the first and second metal layers (Fig. 1, metal layers 123 and 125) comprises forming structure for powering the functional dies (Fig.1, metal layers 125 and 123,as being part of an electrical circuit device, will inherently need power and would have to have power and ground connected to the circuit) Koopmans does not disclose an intra-stack capacitor structure. However, Karp teaches an intra-stack capacitor (Fig. 3, element 362-2, capacitor within a die stack 102,104,106,108) for mitigating electrostatic discharge (ESD) effects within the electronic device. (Colm. 11 lines 25-45, stating the capacitor is used for power supply ESD mitigation). It would have been obvious to a person of skill in the art at the time of the effective filing date to add the capacitor of Karp for the first and second metal layer of Koopmans to provide proper ESD mitigation within the electronic device. Claim(s) 5,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koopmans in view of Kim (U.S. Publication 20200303341) further in view of Yang et al. (U.S. Publication 20090166835) Regarding Claim 5, Koopmans teaches the electronic device according to claim 1, and further teaches a dummy die (Fig. 1 die 120), but fails to disclose a first dummy die disposed between the substrate and a first one of the functional dies, and (ii) a second dummy die disposed between two of the functional dies. However, Kim teaches a dummy die (Fig. 1A dummy die 108) disposed between the substrate and a first one of the functional dies (Fig. 1A shows dummy die 108 between substrate 110 and functional die 118. Kim does teach a second dummy die 120 but fails to teach the second dummy die in between two functional dies. It would have been obvious to a person of skill in the art at the time of the effective filing date to use the dummy die of Koopmans between the substrate and functional die of Kim to electrically couple the package substrate to the functional die. Further, Koopmans in view of Kim fail to teach a dummy die disposed between two of the functional dies. However, Yang does teach a dummy die (Fig. 1 interposer unit 102) disposed between two of the functional dies. (Fig. 1 shows interposer 102 between IC die 120 and 114). It would have been obvious to a person of skill in the art at the time of the effective filing date to place the second dummy die from Kim between the functional dies of Yang to reduce overall package height, [0028] from Yang. Regarding Claim 20, Koopmans teaches the method according to claim 16, and further teaches a dummy die (Fig. 1 die 120), but fails to disclose a first dummy die disposed between the substrate and a first one of the functional dies, and (ii) a second dummy die disposed between two of the functional dies. However, Kim teaches a dummy die (Fig. 1A dummy die 108) disposed between the substrate and a first one of the functional dies (Fig. 1A shows dummy die 108 between substrate 110 and functional die 118. Kim does teach a second dummy die 120 but fails to teach the second dummy die in between two functional dies. It would have been obvious to a person of skill in the art at the time of the effective filing date to use the dummy die of Koopmans between the substrate and functional die of Kim to electrically couple the package substrate to the functional die. Further, Koopmans in view of Kim fail to teach a dummy die disposed between two of the functional dies. However, Yang does teach a dummy die (Fig. 1 interposer unit 102) disposed between two of the functional dies. (Fig. 1 shows interposer 102 between IC die 120 and 114). It would have been obvious to a person of skill in the art at the time of the effective filing date to place the second dummy die from Kim between the functional dies of Yang to reduce overall package height, [0028] from Yang. Claim(s) 11,26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koopmans in view of Davis et al. (U.S. Publication 20160225742) Regarding Claim 11, Koopmans teaches the electronic device according to claim 1, and still teaches the lid (Fig. 1, lid 112) but fails to teach the lid to have cooling fins. However, Davis does teach one or more cooling fins,(Fig. 10 showing a heat sink 104 with plural fins) which are configured to provide an additional surface area on the lid for heat dissipation. ([0038] discloses heat sink 104 thermally coupled to lid to provide additional surface area for heat dissipation). It would have been obvious to a person of skill in the art at the time of the effective filing date to use the heat sink with plural fins from Davis to the lid structure of Koopmans to further provide additional surface area to the lid structure for better passive cooling means. Regarding Claim 26, Koopmans teaches the method according to claim 16, and still teaches the lid (Fig. 1, lid 112) but fails to teach the lid to have cooling fins. However, Davis does teach one or more cooling fins,(Fig. 10 showing a heat sink 104 with plural fins) which are configured to provide an additional surface area on the lid for heat dissipation. ([0038] discloses heat sink 104 thermally coupled to lid to provide additional surface area for heat dissipation). It would have been obvious to a person of skill in the art at the time of the effective filing date to use the heat sink with plural fins from Davis to the lid structure of Koopmans to further provide additional surface area to the lid structure for better passive cooling means. Claim(s) 14,29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koopmans further in view of Majumdar (U.S. Publication 20160126159). Regarding Claim 14, Koopmans teaches the electronic device according to claim 1, but fails to disclose wherein at least one of the dummy dies comprises a polymer substrate. However, Majumdar teach at least one of the dummy dies comprises a polymer substrate (Fig. 1, claim 9 disclose a dummy die interpose 102 to be made from polymer). It would have been obvious to a person of skill in the art at the time of the effective filing date to use the polymer interpose of Majumdar with the interposer dummy die from Koopmans as a simple substitution to yield predictable results. Regarding Claim 29, Koopmans teaches the method according to claim 16, but fails to disclose wherein disposing the one or more dummy dies comprises disposing at least one of the dummy dies having a polymer substrate. However, Majumdar teach at least one of the dummy dies comprises a polymer substrate (Fig. 1, claim 9 disclose a dummy die interpose 102 to be made from polymer). It would have been obvious to a person of skill in the art at the time of the effective filing date to use the polymer interpose of Majumdar with the interposer dummy die from Koopmans as a simple substitution to yield predictable results. Claim(s) 12,27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koopmans further in view of Lin (U.S. Publication 20140048951). Regarding Claim 12, Koopmans teaches the electronic device according to claim 1, but fails to disclose a stiffener formed between the substrate and the lid, the stiffener being configured to improve a mechanical stiffness of the electronic device. However, Lin teaches a stiffener (Fig. 2 stiffener 41) formed between the substrate (Fig. 2 coreless substrate 20) and the lid (Fig. 2 heat dissipation plate 81 acting as a covering lid), the stiffener being configured to improve a mechanical stiffness of the electronic device. ([0013] stating the stiffener is to be used to suppress warping and bending of the assembly). It would have been obvious to a person of skill in the art at the time of the effective filing date to use the stiffener from Lin between the lid and substrate of Koopmans to suppress warping and bending of the substrate, [0013] from Lin. Regarding Claim 27, Koopmans teaches the method according to claim 16, but fails to disclose forming a stiffener, between the substrate and the lid, for improving a mechanical stiffness of the electronic device. However, Lin teaches a stiffener (Fig. 2 stiffener 41) formed between the substrate (Fig. 2 coreless substrate 20) and the lid (Fig. 2 heat dissipation plate 81 acting as a covering lid), the stiffener being configured to improve a mechanical stiffness of the electronic device. ([0013] stating the stiffener is to be used to suppress warping and bending of the assembly). It would have been obvious to a person of skill in the art at the time of the effective filing date to use the stiffener from Lin between the lid and substrate of Koopmans to suppress warping and bending of the substrate, [0013] from Lin. Response to Arguments Applicant's arguments filed 4/16/2025 have been fully considered but they are not persuasive. Applicant first argues that element 120 of Koopman is not a dummy die disposed “among” the functional dies because it is “over” the functional dies. This is unpersuasive as applicant is reading the claim more narrowly than it is recited. Specifically, “among” does not preclude being disposed “over” something as among can simply mean “alongside” or “part of a group”. Applicant appears to be arguing that “among” should be limited to being read as “surrounded by” or “in the middle of” which are more narrowly construed meanings of “among”. As such, this argument is unpersuasive. Applicant next argues that Koopman does not teach a dummy die extending laterally beyond an edge of the stack and through the at least one opening in the lid and forming a direct thermal coupling an environment outside the lid. This is unpersuasive. As noted above, element 120 is the dummy die and Fig.1 clearly shows it extending latterly beyond an edge of the stack. Additionally, applicant does not specify the structure of the opening in the lid and since the “lid” in Koopman is, as applicant noted, combined elements 112 and 113, the “opening” is area in the void formed by the surrounding 113 “walls” and the top “112”. Nothing in the claim limitations require that the opening be from one side of, for example, 112 to the other side. Since this is the case, the dummy die merely need to be presently extending “through” the opening; and since the “opening” is, as noted above, the space defined by sidewalls 113 and top 112 and 120 is clearly extending “through” that area, this meets the claim limitations for “extending through”. Furthermore, “direct thermal coupling” does not require “direct contact” as is implied in the arguments; it merely requires that there be a direct route of thermal coupling between two things and since Koopman clearly shows a direct thermal route from the environment to 120 via element 112 and the TIM to element 120 that is extending “through” the opening defined by 113 and 112 to the TIM, there is direct thermal coupling occurring between it and the outside environment. Regarding the arguments directed to claim 16, since claim 16 is just the generic method of making claim 1, the same response to claim 1 would read on claim 16. The remaining arguments are based on the dependency on the independent claims and since the arguments regarding the independent claims are found unpersuasive, so, too, are these arguments found. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DALE E PAGE whose telephone number is (571)270-7877. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jul 27, 2022
Application Filed
Feb 26, 2025
Non-Final Rejection mailed — §102, §103
Apr 16, 2025
Response Filed
Oct 06, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
65%
Grant Probability
72%
With Interview (+7.2%)
3y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 333 resolved cases by this examiner. Grant probability derived from career allowance rate.

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