DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/26/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sundaresan et al. [US 2020/0388695 A1], “Sundaresan”.
Regarding claim 1, Sundaresan discloses a silicon carbide semiconductor device (Fig. 6-Fig.7ff – see annotated Fig. 7ff* for clarification and easier reference numbering) , comprising:
a SiC substrate (Fig. 7ff*, 701) of a first conductivity type (N+);
a drift layer (702) of the first conductivity type (N) disposed on (as shown) the SiC substrate (701);
an active area (AA) and a termination area (TA) formed in the drift layer (702), the active area including a plurality of transistor cells (¶[0002] teaches power semiconductor devices), and the termination area (TA) surrounding a periphery of the active area (as shown), wherein the termination area comprises a main junction region (TA-MJ) and an edge region (TA-ER) adjacent to the main junction region (as shown);
an insulating layer (714) disposed on the drift layer (as shown);
a polysilicon layer (715) disposed on the insulating layer (as shown), comprising a first portion (715.1) disposed over the active area (AA) and a second portion (715.2) disposed over the termination area (TA), wherein the second portion (715.2) extends from the edge region through the main junction region to the active area (as shown);
an interlayer dielectric layer (717) disposed on the polysilicon layer (715); and
a metal layer (721) disposed on the interlayer dielectric layer (714), comprising a first portion (721.1) disposed over the active area (AA) and a second portion (721.2) disposed over the termination area (TA);
wherein at least one of the second portion (715.2) of the polysilicon layer (715) and the second portion (721.2) of the metal layer (721) is configured configurated to electrically connect to at least one of a gate electrode and a source electrode (as shown in Fig. 7ff, ¶[0022]); and
wherein each of the transistor cells comprises:
a first well region (705) of a second conductivity type (p-type), disposed on the drift layer (as shown);
a source region (710) of the first conductivity type (N), disposed on the first well region (705); and
a doped region (713) of the second conductivity (P), extending through the source region (710) and the first well region (705), and contacting the drift layer (702).
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Regarding claim 3, Sundaresan disclose claim 1, Sundaresan discloses the second portion of the metal layer (Fig. 7ff*, 721.2) and the second portion of the polysilicon layer (715.2) are electrically connected to the gate electrode (715.2) (as shown in Fig. 7ff, ¶[0022]).
Regarding claim 4, Sundaresan disclose a silicon carbide semiconductor device (Fig. 6-Fig.7ff – see annotated Fig. 7ff* above for clarification and easier reference numbering), comprising:
a SiC substrate (Fig. 7ff*, 701) of a first conductivity type (N+);
a drift layer (702) of the first conductivity type (N) disposed on (as shown) the SiC substrate;
an active area (AA) and a termination area (TA) formed in the drift layer (702), the active area including a plurality of transistor cells (¶[0002] teaches power semiconductor devices), and the termination area surrounding a periphery of the active area (as shown), wherein the termination area comprises a main junction region (TA-MJ) and an edge region (TA-ER) adjacent to the main junction region (as shown);
an insulating layer (714) disposed on the drift layer (as shown);
a polysilicon layer (715) disposed on the insulating layer (as shown), comprising a first portion (715.1) disposed over the active area (AA) and a second portion (715.2) disposed over the termination area (TA), the second portion (715.2) of the polysilicon layer being configured to connect to at least one of a gate electrode and a source electrode (as shown in Fig. 7ff, ¶[0022]), wherein the second portion extends from the edge region through the main junction region to the active area (as shown);
an interlayer dielectric layer (717) disposed on the polysilicon layer (715); and
a metal layer (721) disposed on the interlayer dielectric layers (as shown), wherein each of the transistor cells comprises:
a first well region (705) of a second conductivity type (p-type), disposed on the drift layer (as shown);
a source region (710) of the first conductivity type (n-type), disposed on the first well region (as shown); and
a doped region (713) of the second conductivity (p-type), extending through the source region and the first well region, and contacting the drift layer (as shown).
Regarding claim 5, Sundaresan disclose claim 4, Sundaresan discloses the metal layer (Fig. 7ff*, 721.2) and the second portion of the polysilicon layer (715.2) are electrically connected to the gate electrode (715.2) (as shown in Fig. 7ff, ¶[0022]).
Regarding claim 6, Sundaresan disclose a silicon carbide semiconductor device (Fig. 6-Fig.7ff – see annotated Fig. 7ff* above for clarification and easier reference numbering), comprising:
a SiC substrate (Fig. 7ff*, 701) of a first conductivity type (N+);
a drift layer (702) of the first conductivity type (N) disposed on (as shown) the SiC substrate (701);
an active area (AA) and a termination area (TA) formed in the drift layer, the active area including a plurality of transistor cells (¶[0002] teaches power semiconductor devices), and the termination area (TA) surrounding a periphery (as shown) of the active area (AA), wherein the termination area (TA) comprises a main junction region (TA-MJ) and an edge region (TA-ER) adjacent to the main junction region (as shown);
an insulating layer (714) disposed on the drift layer (as shown);
a polysilicon layer (715) disposed on the insulating layer (as shown), comprising a first portion (715.1) disposed over the active area (AA) and a second portion (715.2) disposed over the termination area (TA), wherein the second portion extends from the edge region through the main junction region to the active area (as shown);
an interlayer dielectric layer (717) disposed on the polysilicon layer (715); and
a metal layer (721) disposed on the interlayer dielectric layer (714), comprising a first portion (721.1) disposed over the active area (AA) and a second portion (721.2) disposed over the termination area (TA), the second portion of the metal layer being configured to connect to at least one of a gate electrode and a source electrode (as shown in Fig. 7ff, ¶[0022]);
wherein each of the transistor cells comprises:
a first well region (705) of a second conductivity type (p-type), disposed on the drift layer (as shown);
a source region (710) of the first conductivity type (N), disposed on the first well region (705); and
a doped region (713) of the second conductivity (P), extending through the source region (710) and the first well region (705), and contacting the drift layer (702).
Regarding claim 7, Sundaresan disclose claim 6, Sundaresan discloses the second portion of the metal layer (Fig. 7ff*, 721.2) and the second portion of the polysilicon layer (715.2) are electrically connected to the gate electrode (715.2) (as shown in Fig. 7ff, ¶[0022]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Sundaresan et al. [US 2020/0388695 A1], “Sundaresan” as applied to claim 1 above, and further in view of Uchida et al. [US 2015/0349051 A1], “Uchida”.
Regarding claim 2, Sundaresan disclose claim 1, Sundaresan does not explicitly disclose the second portion of the metal layer extends laterally beyond the second portion of the polysilicon layer.
However, Uchida disclose a semiconductor device with a second portion of a polysilicon layer (Fig. 3A, 108g) in the termination region (100G-100S). Uchida further disclose the second portion of the metal layer (114L) extends laterally beyond the second portion of the polysilicon layer in direction towards the termination region. Uchida discloses the gate wiring can be adjusted to match the pitch of the cell (¶[0050]).
Therefore it would obvious to one of ordinary skill in the art before the filing date of the invention to extend the metal layer beyond the polysilicon layer as taught in Uchida in the device of Sundaresan such that the second portion of the metal layer extends laterally beyond the second portion of the polysilicon layer because such a modification allows for the improve the effectively reduce the signal delay (¶[0078] of Uchida).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection required by Applicant’s amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gandhi et al. [US 2014/0167068 A1] Silicon carbide device e.g. silicon carbide MOSFET, junction-gate field-effect transistor (JFET) power device for power application.
Kudou [US 2015/0108503 A1] teaches a cell region is provided with a gate insulating film disposed on the semiconductor layer and a gate electrode disposed on the gate insulating film, and a wiring region is provided with a field insulating film disposed on the semiconductor layer and a gate wire disposed on the field insulating film.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/Examiner, Art Unit 2897