DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7, 14-20 in the reply filed on 01/20/2026 is acknowledged. Newly added claims 21-26 are acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kataeva et al., hereinafter referred to as Kataeva (US 2020/0110991 A1) in view of Kara et al., hereinafter referred to as Kara (US 2019/0122105 A1).
As per claim 1, Kataeva discloses a memory-based device (Kataeva: Abstract; [0044]-[0045]), comprising:
a plurality of first wires (Kataeva: Para. [0046] discloses “a plurality of input bars 50”);
a plurality of second wires arranged across the plurality of first wires (Kataeva: Para. [0046] discloses “a plurality of output bars 51 and 52 are provided in such a manner as to intersect with the plurality of input bars 50”);
a plurality of resistors (memristors 53), wherein each of the plurality of resistors is coupled to one of the plurality of first wires (50) and one of the plurality of second wires (51/52), wherein a plurality of input signals are transmitted (provided) from the plurality of first wires through the plurality of resistors to the plurality of second wires (Kataeva: Para. [0046] discloses “a plurality of memristors 53 for weighting input signals”; Kataeva: Para. [0047] discloses “The memristor 53 for weighting an input signal is provided at an intersection of the input bar 50 and the output bar 51. The input bar 50 and the output bar 51 are connected to each other via the memristor 53”; Kataeva: Para. [0049] discloses “voltage signals V1 and V2 each input from the input neuron 55 to the input bar 50 are multiplied by conductance values G1 and G2, respectively, by the memristors 53”); and
(Kataeva: Paras. [0022], [0024], [0067] disclose applying a non-linear activation function like ReLU and configuring a predetermined bias input, which mathematically shifts the sum value processed by the activation function.),
However, Kataeva does not explicitly disclose “… a processor configured to receive a sum value of the input signals from one of the plurality of second wires, and shift the sum value by a nonlinear activation function to generate a shifted sum value, wherein the processor is configured to calculate a backpropagation value based on the shifted sum value and a target value related to a corresponding input signal of the plurality of input signals, and generate a pulse number based on the corresponding input signal of the plurality of input signals and the backpropagation value, wherein each of a value of the corresponding input signal and the backpropagation value is higher than or equal to a threshold value, wherein the processor is configured to apply a voltage pulse to one of the plurality of resistors related to the corresponding input signal based on the pulse number, in order to modify the value of the corresponding input signal in the plurality of input signals to be the same as the target value.”
Further, Kara is in the same field of endeavor and teaches a processor configured to receive a sum value of the input signals from one of the plurality of second wires (column lines), and shift the sum value by a nonlinear activation function to generate a shifted sum value (Kara: Paras. [0031], [0045] disclose a digital processing unit (DPU 4) receiving the digital signal values corresponding to the weighted sum of the input signals (∑ Wᵢⱼ x₁ᵢ) from the column lines, applying a non-linear activation function (e.g., sigmoid) to the sum and using bias neurons to offset/shift the signals.), wherein the processor is configured to calculate a backpropagation value based on the shifted sum value and a target value related to a corresponding input signal of the plurality of input signals (Kara: Para. [0048] discloses the processor calculating a backpropagation value based on the activated sum and a target value, as the the DPU calculates error values δ3k by subtracting the activation output from the expected network output [target value].), and generate a pulse number (nij) based on the corresponding input signal (x1i) of the plurality of input signals and the backpropagation value (Kara: Paras. [0050], [0062] disclose generating a pulse number based on the input signal and the backpropagation value (calculating weight correction ΔWij using input x1i and error δ2j, and rounding this value to generate a discrete number of programming pulses nij.), wherein each of a value of the corresponding input signal and the backpropagation value is higher than or equal to a threshold value (Kara: Paras. [0048], [0051] disclose executing these calculations specifically for devices “for which x1i and/or δ2j exceed a threshold level,” meeting the requirement that the input and backpropagation values are higher than or equal to a threshold.), wherein the processor is configured to apply a voltage pulse (applied potentiation) to one of the plurality of resistors related to the corresponding input signal based on the pulse number, in order to modify the value of the corresponding input signal in the plurality of input signals to be the same as the target value (Kara: Paras. [0004], [0062], [0067] disclose controller 7 applies |nij| potentiation or depression programming pulses to the device to update the stored weight, repeatedly reducing the error to reach the expected network output [i.e., applying a voltage pulse to the resistor based on the pulse number to modify the network signal outputs to match the target].).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, and having the teachings of Kataeva and Kara before him or her, to modify the memory-based crossbar array of Kataeva to include the processor backpropagation threshold and voltage pulse generation features as described in Kara. The motivation for doing so would have been to improve the efficiency and accuracy of neural network training algorithms by enabling dynamic and precise adjustments to the resistance weights of the memristors.
As per claim 2, Kataeva-Kara disclose the device of claim 1, wherein the plurality of first wires and the plurality of second wires are arranged to form an array, wherein each of the plurality of resistors located at the same column of the array has a first terminal and a second terminal, the first terminals of the plurality of resistors are coupled to different wires of the plurality of first wires, and the second terminals of the plurality of resistor are coupled to the same wire of the plurality of second wires (Kara: Paras. [0032]-[0033] disclose crossbar arrays of memristive devices, connected between row and column lines. The devices 10 are arranged in logical rows and columns with each device connected been a particular row line and column line, indicating devices in the same column are connected to different row lines [first wires] and the same column line [second wire]. Additionally, Kataeva: Paras. [0047]-[0048] disclose the crossbar circuit 44 includes a plurality of input bars 50, a plurality of output bars 51 and 52, a plurality of memristors 53. The memristor 53 for weighting an input signal is provided at an intersection of the input bar 50 and the output bar 51. The input bar 50 and the output bar 51 are connected to each other via the memristor 53.).
As per claim 3, Kataeva-Kara disclose the device of claim 2, wherein the processor is configured to respectively shift sum values from the plurality of second wires located in columns of the array by the nonlinear activation function to generate shifted sum values (Kara: Para. [0042] discloses the activation function typically comprises a non-linear function; Kara: Para. [0045] discloses DPU 4 [the processor] is configured to calculate digital signal values by applying the activation function to the weighted sum signals from the column lines [second wires] of the array to generate output values.).
As per claim 4, Kataeva-Kara disclose the device of claim 3, wherein the processor is configured to calculate backpropagation values based on the shifted sum values and a plurality of target values, wherein each of the plurality of target values corresponds to one of the plurality of input signals (Kataeva: Paras. [0036], [0093]-[0094] disclose calculating a difference “e = target - y” for “back propagation” using actual output voltage y generated at each “shift position” and a “target analog output voltage target” corresponding to the input “Teaching data”, teaching calculating backpropagation values based on shifted sum values and a plurality of target values, wherein each of the plurality of target values corresponds to one of the plurality of input signals.).
As per claim 5, Kataeva-Kara disclose the device of claim 4, wherein the processor is configured to compare each of the values of the plurality of input signals with the threshold value, and compare each of the backpropagation values with the threshold value, wherein the processor is configured to generate pulse numbers based on the plurality of input signals and the backpropagation values if each of the plurality of input signals and the backpropagation values is higher than or equal to the threshold value (Kara: Paras. [0048]-[0051] disclose the processor comparing the input signals and backpropagation values (error signals) with a threshold level, and computing a weight-correction value based on the input signals and backpropagation values if they exceed the threshold level (ΔWij may be computed for only a subset of devices “for which x1i and/or δ2j exceed a threshold level,” where x1i represents input signals and δ2j represents backpropagation error signals); generating pulse numbers based on this computation (The rounded result gives a number n of these programming pulses to be applied to the device).).
As per claim 6, Kataeva-Kara disclose the device of claim 5, wherein the processor is configured to correspondingly apply voltage pulses to the plurality of resistors, through one of the plurality of first wires and one of the plurality of second wires, based on the pulse numbers, so as to change resistance of the plurality of resistors (Kara: Para. [0041] discloses that by application of appropriate programming pulses to a cell via the corresponding row line [first wire] and column line [second wire], the cell can be programmed to a high-resistance or low-resistance state; Kara: Paras. [0058], [0062] disclose the DPU [processor] determining a number of programming pulses to be applied to the device, and applying the corresponding number of potentiation or depression programming pulses to the device to change its state/resistance.).
As per claim 7, Kataeva-Kara disclose the device of claim 1, wherein the nonlinear activation function comprises at least one of a sigmoid function and a rectified linear unit (ReLU) function (Kataeva: Para. [0039] discloses “According to the present embodiment, a ReLU is used as the activation function”.).
As per claim 14, Kataeva discloses a device (Kataeva: Abstract; [0044]-[0045]), comprising:
a plurality of first wires configured to receive a plurality of input signals (Kataeva: Para. [0046] discloses “a plurality of input bars 50”);
a plurality of second wires (Kataeva: Para. [0046] discloses “a plurality of output bars 51 and 52”.);
a plurality of resistors (memristors 53) configured to transmit the plurality of input signals to one of the plurality of second wires to generate a sum value (Kataeva: Paras. [0022], [0047], [0049] disclose each of the neurons calculates a sum of values provided at each intersection of the input bars 50 and the output bars 51; Para. [0046] discloses “a plurality of memristors 53 for weighting input signals”; Kataeva: Para. [0047] discloses “The memristor 53 for weighting an input signal is provided at an intersection of the input bar 50 and the output bar 51. The input bar 50 and the output bar 51 are connected to each other via the memristor 53”; Kataeva: Para. [0049] discloses “voltage signals V1 and V2 each input from the input neuron 55 to the input bar 50 are multiplied by conductance values G1 and G2, respectively, by the memristors 53”.); and
a processor configured to:
shift the sum value by a nonlinear activation function to generate a shifted sum value (Kataeva: Paras. [0022], [0024], [0067] disclose applying a non-linear activation function like ReLU and configuring a predetermined bias input, which mathematically shifts the sum value processed by the activation function.),
However, Kataeva does not explicitly disclose “… calculate a feedback based on the shifted sum value and a target value related to a corresponding input signal of the plurality of input signals, generate a pulse number based on the corresponding input signal and the feedback, apply a voltage pulse to one of the plurality of resistors related to the corresponding input signal based on the pulse number, and modify a value of the corresponding input signal to be the same as the target value.”.
Further, Kara is in the same field of endeavor and teaches calculate a feedback based on the shifted sum value and a target value related to a corresponding input signal of the plurality of input signals (Kara: Para. [0048] discloses the processor calculating a backpropagation value based on the activated sum and a target value, as the the DPU calculates error values δ3k by subtracting the activation output from the expected network output [target value].),
generate a pulse number (nij) based on the corresponding input signal (x1i) and the feedback (Kara: Paras. [0050], [0062] disclose generating a pulse number based on the input signal and the backpropagation value (calculating weight correction ΔWij using input x1i and error δ2j, and rounding this value to generate a discrete number of programming pulses nij.),
apply a voltage pulse (applied potentiation) to one of the plurality of resistors related to the corresponding input signal based on the pulse number, in order to modify the value of the corresponding input signal in the plurality of input signals to be the same as the target value (Kara: Paras. [0004], [0062], [0067] disclose controller 7 applies |nij| potentiation or depression programming pulses to the device to update the stored weight, repeatedly reducing the error to reach the expected network output [i.e., applying a voltage pulse to the resistor based on the pulse number to modify the network signal outputs to match the target].).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, and having the teachings of Kataeva and Kara before him or her, to modify the memory-based crossbar array of Kataeva to include the feedback voltage pulse generation features as described in Kara. The motivation for doing so would have been to improve the efficiency and accuracy of neural network training algorithms by enabling dynamic and precise adjustments to the resistance weights of the memristors.
As per claim 15, the claim(s) recites analogous limitations to claim(s) 3 above, and is/are therefore rejected on the same premise.
As per claim 16, the claim(s) recites analogous limitations to claim(s) 4 above, and is/are therefore rejected on the same premise.
As per claim 17, Kataeva-Kara disclose the device of claim 16, wherein the processor is further configured to:
compare each of the plurality of input signals with a threshold value (Kara: Paras. [0048]-[0051] disclose the processor comparing the input signals and backpropagation values [feedbacks] with a threshold level, and computing a weight-correction value based on the input signals and backpropagation values if they exceed the threshold level (ΔWij may be computed for only a subset of devices “for which x1i and/or δ2j exceed a threshold level,” where x1i represents input signals and δ2j represents backpropagation error signals); generating pulse numbers based on this computation (The rounded result gives a number n of these programming pulses to be applied to the device).),
compare each of the plurality of feedbacks with the threshold value (Kara: Paras. [0048]-[0051] disclose the processor comparing the input signals and backpropagation values [feedbacks] with a threshold level.), and
adopt the plurality of input signals and the plurality of feedbacks when the plurality of input signals and the plurality of feedbacks are higher than the threshold value (Kara: Paras. [0048]-[0051] disclose computing a weight-correction value based on the input signals and backpropagation values if they exceed the threshold level (ΔWij may be computed for only a subset of devices “for which x1i and/or δ2j exceed a threshold level,” where x1i represents input signals and δ2j represents backpropagation error signals); generating pulse numbers based on this computation (The rounded result gives a number n of these programming pulses to be applied to the device).).
As per claim 18, Kataeva-Kara disclose the device of claim 17, wherein the plurality of feedbacks comprise backpropagation values (Kara: Paras. [0048]-[0051] disclose computing a weight-correction value based on the input signals and backpropagation values [feedbacks].).
As per claim 19, Kataeva-Kara disclose the device of claim 18, wherein the processor is further configured to:
generate a plurality of pulse numbers based on the plurality of input signals and the plurality of feedbacks, and correspondingly apply voltage pulses to the plurality of resistors, through one of the plurality of first wires and one of the plurality of second wires, based on the plurality of pulse numbers, so as to change resistances of the plurality of resistors (Kara: Para. [0041] discloses that by application of appropriate programming pulses to a cell via the corresponding row line [first wire] and column line [second wire], the cell can be programmed to a high-resistance or low-resistance state; Kara: Paras. [0058], [0062] disclose the DPU [processor] determining a number of programming pulses to be applied to the device, and applying the corresponding number of potentiation or depression programming pulses to the device to change its state/resistance.).
As per claim 20, the claim(s) recites analogous limitations to claim(s) 7 above, and is/are therefore rejected on the same premise.
Claims 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Strukov et al., hereinafter referred to as Strukov (US 2021/0019609 A1) in view of Kara et al., hereinafter referred to as Kara (US 2019/0122105 A1).
As per claim 21, Strukov discloses a device (Strukov: Abstract.), comprising:
a first processor (Strukov: Para. [0136] discloses one or more processors 500.);
a plurality of resistors (variable resistors), wherein a plurality of input signals are transmitted from the first processor through the plurality of resistors (Strukov: Para. [0084] discloses each synaptic weight is implemented with one or several non-volatile memory elements acting as a variable resistor whose resistance can be tuned. If the input is applied as a voltage signal to rows of the crossbar, current on each column will be the dot product.); and
a second processor configured to receive a sum value of the input signals from one of the plurality of resistors, and shift the sum value by a nonlinear activation function to generate a shifted sum value (Strukov: Paras. [0059], [0136] disclose circuits/processors performing a summation and applying the activation function to the summation using operational amplifier. f' is the activation function, that can be any nonlinear function such as 'tanh'.),
However, Strukov does not explicitly disclose “… wherein the second processor is configured to calculate a backpropagation value based on the shifted sum value and a target value related to a corresponding input signal of the plurality of input signals, and generate a pulse number based on the corresponding input signal of the plurality of input signals and the backpropagation value, wherein each of a value of the corresponding input signal and the backpropagation value is higher than or equal to a threshold value, wherein the second processor is configured to apply a voltage pulse to one of the plurality of resistors related to the corresponding input signal based on the pulse number, in order to modify the value of the corresponding input signal in the plurality of input signals to be the same as the target value.”
Further, Kara is in the same field of endeavor and teaches wherein the second processor is configured to calculate a backpropagation value based on the shifted sum value and a target value related to a corresponding input signal of the plurality of input signals (Kara: Para. [0048] discloses the processor calculating a backpropagation value based on the activated sum and a target value, as the the DPU calculates error values δ3k by subtracting the activation output from the expected network output [target value].), and generate a pulse number (nij) based on the corresponding input signal (x1i) of the plurality of input signals and the backpropagation value (Kara: Paras. [0050], [0062] disclose generating a pulse number based on the input signal and the backpropagation value (calculating weight correction ΔWij using input x1i and error δ2j, and rounding this value to generate a discrete number of programming pulses nij.), wherein each of a value of the corresponding input signal and the backpropagation value is higher than or equal to a threshold value (Kara: Paras. [0048], [0051] disclose executing these calculations specifically for devices “for which x1i and/or δ2j exceed a threshold level,” meeting the requirement that the input and backpropagation values are higher than or equal to a threshold.), wherein the second processor is configured to apply a voltage pulse (applied potentiation) to one of the plurality of resistors related to the corresponding input signal based on the pulse number, in order to modify the value of the corresponding input signal in the plurality of input signals to be the same as the target value (Kara: Paras. [0004], [0062], [0067] disclose controller 7 applies |nij| potentiation or depression programming pulses to the device to update the stored weight, repeatedly reducing the error to reach the expected network output [i.e., applying a voltage pulse to the resistor based on the pulse number to modify the network signal outputs to match the target].).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, and having the teachings of Strukov and Kara before him or her, to modify the neuromorphic computing circuitry of Strukov to include the processor backpropagation threshold and voltage pulse generation features as described in Kara. The motivation for doing so would have been to improve the efficiency and accuracy of neural network training algorithms by enabling dynamic and precise adjustments to the resistance weights of the memristors.
As per claim 22, Strukov-Kara disclose the device of claim 21, wherein the second processor is configured to respectively shift sum values by the nonlinear activation function to generate shifted sum values (Strukov: Para. [0136] discloses one or more processors 500; Kara: Para. [0042] discloses the activation function typically comprises a non-linear function; Kara: Para. [0045] discloses DPU 4 is configured to calculate digital signal values by applying the activation function to the weighted sum signals from the column lines of the array to generate output values.).
As per claim 23, Strukov-Kara disclose the device of claim 22, wherein the second processor is configured to calculate backpropagation values based on the shifted sum values and a plurality of target values, wherein each of the plurality of target values corresponds to one of the plurality of input signals (Strukov: Para. [0136] discloses one or more processors 500; Kara: Para. [0048] discloses calculating error values for backpropagation based on an “expected output” and “digital signal values”, which teaches calculating backpropagation values based on sum values and target values.).
As per claim 24, Strukov-Kara disclose the device of claim 23, wherein the second processor is configured to compare each of the values of the plurality of input signals with the threshold value, and compare each of the backpropagation values with the threshold value, wherein the second processor is configured to generate pulse numbers based on the plurality of input signals and the backpropagation values if each of the plurality of input signals and the backpropagation values is higher than or equal to the threshold value (Strukov: Para. [0136] discloses one or more processors 500; Kara: Paras. [0048]-[0051] disclose the processor comparing the input signals and backpropagation values (error signals) with a threshold level, and computing a weight-correction value based on the input signals and backpropagation values if they exceed the threshold level (ΔWij may be computed for only a subset of devices “for which x1i and/or δ2j exceed a threshold level,” where x1i represents input signals and δ2j represents backpropagation error signals); generating pulse numbers based on this computation (The rounded result gives a number n of these programming pulses to be applied to the device).).
As per claim 25, Strukov-Kara disclose the device of claim 24, wherein the second processor is configured to correspondingly apply voltage pulses to the plurality of resistors based on the pulse numbers, so as to change resistance of the plurality of resistors (Strukov: Para. [0136] discloses one or more processors 500; Kara: Para. [0041] discloses that by application of appropriate programming pulses to a cell via the corresponding row line [first wire] and column line [second wire], the cell can be programmed to a high-resistance or low-resistance state; Kara: Paras. [0058], [0062] disclose the DPU [processor] determining a number of programming pulses to be applied to the device, and applying the corresponding number of potentiation or depression programming pulses to the device to change its state/resistance.).
As per claim 26, Strukov-Kara disclose the device of claim 21, wherein the nonlinear activation function comprises at least one of a sigmoid function and a rectified linear unit (ReLU) function (Strukov: Para. [0059] discloses the activation function can be any nonlinear function.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and can be viewed in the list of references.
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/PEET DHILLON/Primary Examiner
Art Unit: 2488
Date: 03-11-2026