Prosecution Insights
Last updated: July 17, 2026
Application No. 17/875,845

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Non-Final OA §102§103
Filed
Jul 28, 2022
Priority
Jul 28, 2021 — CN 202110855630.7
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Technology Innovation Center (Beijing) Corporation
OA Round
3 (Non-Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
669 granted / 931 resolved
+3.9% vs TC avg
Strong +19% interview lift
Without
With
+18.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
62 currently pending
Career history
1009
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
83.7%
+43.7% vs TC avg
§102
12.2%
-27.8% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 Receipt is acknowledged of a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 01/23/2026. Response to Arguments Applicant’s arguments with respect to claim(s) Rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 5 and 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. 20220285533. PNG media_image1.png 633 937 media_image1.png Greyscale Regarding claim 1, fig. 11 of Lee discloses a semiconductor structure, comprising: a substrate 304; a plurality of channel layers 310 vertically stacked over the substrate and extending along a first lateral direction (across the page – X direction) parallel to a surface of the substrate; an isolation layer (as labeled by examiner above) on the substrate, wherein a top surface of the isolation layer is not higher than a top surface of any of the plurality of channel layers; gate structures 1104 over the isolation layer, wherein the gate structures surrounds a portion of a length of each channel layer of the plurality of channel layers; PNG media_image2.png 520 523 media_image2.png Greyscale an inner spacer (combination of 502 and 602) formed between adjacent two channel layers 310 of the plurality of channel layers, the inner spacer comprising an opening 902 for enveloping an end of one of the gate structures formed between the adjacent two channel layers, wherein the opening of the inner spacer is formed by a first corner layer (as labeled by examiner above) of the inner spacer and a second corner layer (as labeled by examiner above) of the inner spacer, both extending along the first lateral direction (across the page – X direction), and a middle layer 602 of the inner space extending along a second lateral direction (into the page – Y direction) between the first corner layer and the second corner layer, the second lateral direction parallel to the surface of the substrate and perpendicular to the first lateral direction, and a middle portion of the end of the one of the gate structures protrudes along the first lateral direction into the opening of the inner spacer. Regarding claim 2, fig. 10A of Lee discloses wherein: a size (X-dimension) of the first corner layer and a size of the second corner layer along the first lateral direction is larger than a size of the middle layer along the first lateral direction. Regarding claim 3, fig. 10A/11A of Lee discloses further comprising: outer spacers (328 and 320 combination as labeled in fig. 4) extending vertically along sidewalls of all of the gate structures and the channel layers, wherein sidewalls of the outer spacers are recessed to accommodate end surfaces of the plurality of channel layers along a second the first lateral direction. Regarding claim 5, par [0033] of Lee discloses wherein the inner spacer is made of a material including silicon nitride. Regarding claim 17, fig. 11A of Lee discloses further comprising: source/drain doped layers 802 at two sides of each gate structure along the first lateral direction, wherein surfaces of the source/drain doped layers, surfaces of inner spacers, and end surfaces of the plurality of channel layers are vertically coplanar with each other (the plane in between). Regarding claim 18, fig. 11A of Lee discloses wherein: a top surface (upper surface is top as oppose to lower surface being bottom surface) of the isolation layer is coplanar with a bottom surface of the source/drain doped layers (as the two are in direct contact). Regarding claim 19, fig. 11A of Lee discloses further comprising: a dielectric layer 328 over the isolation layer, wherein the dielectric layer covers a portion of the plurality of channel layers and the gate structures, and exposes top surfaces of the gate structures. Regarding claim 20, fig. 11A of Lee discloses wherein: the plurality of channel layers includes a bottom channel layer between adjacent isolation layers (left and right side) along the first lateral direction, the bottom channel layer has a top surface higher than the top surface of the isolation layers. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee. Regarding claim 4, Lee discloses claim 3, but does not disclose of wherein the sidewalls of the outer spacers are recessed with respect to the end surfaces of the plurality of channel layers by about 1 nm to about 5 nm. However, although Lee is silent about the claimed range, it should be noted that a range does inherently exist in the fig. 21 of Lee reference, but it is not stated. Therefore, the prior art of Lee provides foundation for experimental optimization and suggests a progress of changes in size/proportion in order to optimize the distance between the plurality of channels. Therefore, while the structure of Lee does not quantitatively state a range, the courts have held that when the only difference between the claimed invention and the prior art is a size/proportion, then a prima facie case of obviousness exists [See MPEP 2144.04(IV)(A)]. Therefore, it would have been obvious to one of ordinary skill in the art form a device of Lee wherein said range is about 1 nm to about 5 nm in order to optimize the distance between the plurality of channels. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571 )272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 1 earlier event
May 29, 2025
Non-Final Rejection mailed — §102, §103
Aug 29, 2025
Response Filed
Nov 13, 2025
Final Rejection mailed — §102, §103
Dec 07, 2025
Response after Non-Final Action
Jan 23, 2026
Request for Continued Examination
Feb 02, 2026
Response after Non-Final Action
Apr 27, 2026
Non-Final Rejection mailed — §102, §103
Jun 21, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
90%
With Interview (+18.6%)
3y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

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