Prosecution Insights
Last updated: July 17, 2026
Application No. 17/875,860

PREDICTION OF WAFER FLATNESS

Final Rejection §112
Filed
Jul 28, 2022
Priority
Dec 16, 2021 — continuation of PCTCN2021138711
Examiner
RASTOVSKI, CATHERINE T
Art Unit
2857
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
214 granted / 317 resolved
-0.5% vs TC avg
Strong +28% interview lift
Without
With
+28.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
14 currently pending
Career history
337
Total Applications
across all art units

Statute-Specific Performance

§101
23.3%
-16.7% vs TC avg
§103
57.4%
+17.4% vs TC avg
§102
8.0%
-32.0% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 317 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see pg. 7, filed March 26, 2026, with respect to the rejection(s) of claim(s) 1-10 and 24-25 under 35 U.S.C. 103 have been fully considered and are discussed below. Applicant argues on pg. 7, regarding the 35 U.S.C. 103 rejection presented in the previous office action, that: “By this amendment, independent claims 1, 24 and 25 are amended to incorporate the limitations of allowable claim 4. Accordingly, independent claims 1, 24 and 25 and dependent claims 2-10 thereof are patentable over the cited references.” In response the examiner partly agrees and partly finds the argument persuasive. The Applicant has amended allowable subject matter from claim 4 which depended from claim 1 in the previous Office Action. Therefore the 35 U.S.C. 103 rejection presented towards claim 1 is withdrawn. Claims 2-10 are allowed by virtue of their dependence from claim 1. However, Applicant has also amended claim 4 into separate independent claims 24 and 25, of which claim 4 did not depend in the previous office action. Ergo it is unclear how a processor and/or a memory and/or an executable program may modify a wafer by forming structures on a working surface of a wafer using a plurality of fabrication steps, which presents new 35 U.S.C. 112(b) issues which are cited in the rejection below. Claim Rejections - 35 USC § 112 Claims 24-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite. Claim 24, lines 1-2 disclose “A computer apparatus, comprising processing circuitry configured to.” Claim 24, lines 11-12 disclose “modify the first wafer by forming the structures on the working surface of the first wafer using a plurality of fabrication steps.” It is unclear how a processing circuitry can form structures on a working surface of a wafer using a plurality of fabrication steps. Therefore one of ordinary skill in the art would not be apprised of the scope of the claim. For the purposes of the present examination a processor may not perform a modification step of forming structures. However, further clarification is required. Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite. Claim 25, lines 1-2 disclose “A non-transitory computer-readable storage medium storing a program executable by one or more processors to perform.” Claim 25, lines 11-12 disclose “modify the first wafer by forming the structures on the working surface of the first wafer using a plurality of fabrication steps.” It is unclear how a non-transitory computer-readable storage medium storing a program executable by one or more processors can form structures on a working surface of a wafer using a plurality of fabrication steps. Therefore one of ordinary skill in the art would not be apprised of the scope of the claim. For the purposes of the present examination a processor may not perform a modification step of forming structures. However, further clarification is required. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. US 10,763,099 B2 to Dai et al. relates to wafer flatness control using backside compensation structure. US 12,469,725 B2 to Stoddard et al. relates to a method for determining corrective film pattern to reduce semiconductor wafer bow. US 2023/0161267 A1 to Fulford et al. relates to prediction multi-axis photolithography alignment correction using stressor film. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC S. VON WALD whose telephone number is (571)272-7116. The examiner can normally be reached Monday - Friday 7:30 - 5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Rastovski can be reached at 5712700349. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.S.V./Examiner, Art Unit 2857 /Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2857
Read full office action

Prosecution Timeline

Jul 28, 2022
Application Filed
Feb 28, 2023
Response after Non-Final Action
Feb 10, 2026
Non-Final Rejection mailed — §112
Mar 26, 2026
Response Filed
Apr 23, 2026
Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
96%
With Interview (+28.5%)
3y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 317 resolved cases by this examiner. Grant probability derived from career allowance rate.

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