DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 and 24-25 in the reply filed on August 26, 2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hooge et al. (US 10,622,233 B2), hereinafter Hooge, in further view of Dai et al. (US 2020/0058486 A1), hereinafter Dai.
Regarding claim 1, Hooge discloses A method for determining wafer flatness, comprising:
storing a first wafer expansion of a first wafer that is collected along a first direction parallel to a working surface of the first wafer during a lithography process for patterning structures on the working surf ace of the first wafer; and (Hooge, e.g., see fig. 1 illustrating distorted wafer (100) in the three separate distortion poses of (110), (112), and (114); see also col. 2, line 9 – col. 3, line 49 disclosing out-of-plane distortion (OPD); e.g., x-direction and y-direction forces pushing or pulling the wafer, and in-plane distortion (IPD); e.g., expansion, stretching, or compression, wherein the shape is not uniform; e.g., see fig. 1. Also disclosed is the shape data representative of global distortion of the wafer utilizing pixel technology for amelioration (correction) through a pattern of a backside layer; see also col. 3, line 66 – col. 4, line 8 disclosing subject wafer (205) has multiple semiconductor structures that are at least partially fabricated on a top surface (207) of the subject wafer (205). For example, such structures can includes gates, transistors, trenches, vias, hard masks, films, etc. Thus, subject wafer (205) can be a semiconductor-grade substrate; see also col. 5, lines 64-67 disclosing a large portion of the stretching component is accounted for by the lithography tool; see also col. 4, lines 43-46 and col. 6, lines 41-46 disclosing chart (130) and chart (150) of fig. 1 representative of 2D charts utilizing shading to represent forces acting on the wafer; see also fig. 2 and col. 3, lines 50-60 disclosing the example wafer distortion amelioration system (200) includes a wafer-shape meter (210). The wafer-shape meter (210) acquires wafer-shape data about a subject wafer (205). The subject wafer (205) is a substrate that exhibits out-of-plane and/or in-plane distortion; see also col. 4, lines 26-42 disclosing a wafer shape meter (210) which receives the measurement, creates x,y or radial locations of the substrate, as well as Z-height measurement or relative deflection; e.g., positive or negative; examiner notes that the above cited material discloses a wafer-shape meter collecting a shape to include an OPD and/or IPD of the working surface of a wafer and along a lateral/parallel direction as indicated by (130) and/or (150) of fig. 1 during a photolithography process which is utilized for creating a patterning structure of the working surface of said wafer; examiner notes that charts (130) and (150) are necessarily stored first wafer expansions as they are processed by a processor; examiner further notes that the out-of-plane distortion (OPD) is construed as a first wafer expansion along a first direction).
before a fabrication step with a wafer flatness requirement, determining a wafer distortion of the first wafer based on the first wafer expansion collected during the lithography process using a flatness prediction model that is configured to predict the wafer flatness. (Hooge, e.g., see rejection as applied above disclosing the first wafer expansion collected during the lithography process with a lithography tool; see also fig. 2 illustrating a stress estimator (230), a subject-wafer simulator (220) and model of ideal wafer (225); see also col. 4, line 47 – col. 5, line 41 disclosing wafer-shape meter (210) obtaining a shape data, a generated simulation based on the wafer model producing a highly detailed physics model, wherein the model is a FEM. The Finite Element Model produces chunks called pixels (pixelation), wherein the relevant data from the pixels is collected and presented as distortions; see also col. 6, line 31 – col. 7, line 22 disclosing discretized wafer simulations and stress estimator working in conjunction to estimate of forces acting on each pixel, wherein the FEM outputs simulation outputs the distortion; examiner notes that distortions from an ideally flat wafer utilizes a FEM to predict the deviations from an ideal flatness per the model; see also col. 9, lines 23-36 disclosing with some implementations, the system sends information about the adjustments made by the backside layer(s) to one or more tools in the semiconductor fabrication process so that those tools can take the adjustments into consideration for their processes. This may be called feed-forwarding the impact of the amelioration pattern to other tools in the fabrication process; construed as “before a fabrication step with a wafer flatness requirement”).
Hooge discloses a distortions from an ideally flat wafer which is implicitly a determined wafer flatness, however, Hooge may not be relied upon as explicitly disclosing determining a wafer flatness.
However, Dai further discloses determining a wafer flatness. (Dai, e.g., see fig. 3 illustrating step (302) disclosing obtain a model indicative of a wafer flatness difference between 1st and 2nd directions; see also para. [0032] disclosing various embodiments provide a novel backside deposition solution using a compensation structure with a specifically-designed pattern for compensating for wafer flatness variations in different directions. The pattern can be determined based on a model indicative of the wafer flatness difference in different directions, which can be generated using simulation data and/or measurement data of wafer flatness at any given fabrication stage; see also para. [0052] disclosing fig. 3 is a flowchart of an exemplary method (300) for controlling wafer flatness).
Accordingly, it would be prima facie obvious to one of ordinary skill in the art, at the time the invention was effectively filed, to have modified Hooge with Dai’s wafer flatness for at least the reasons that wafer flatness is utilized in a compensation structure, such as layout, thickness, and material, which may be optimized to balance the wafer flatness difference and improving the yield of the semiconductor, as taught by Dai; e.g., see para. [0032].
Regarding claim 2, Hooge in view of Dai discloses The method according to claim 1, further comprising:
depositing a layer on a back side of the first wafer with a thickness that is based on the determined wafer flatness of the first wafer. (Hooge, e.g., see rejection as applied to claim 1; see fig. 2 illustrating a process of depositing a layer on the backside of a wafer with a thickness in order to correct distortions; see also col. 7, lines 34-64 disclosing ameliorates includes reducing the distortion of the subject wafer. In some implementations, the action may be called a correction. Regardless, the amelioration action results in the application of a backside layer that reduces the out-of-plane and/or the in-plane distortion. Various factors go into generating the backside pattern. Those factors include, at least in part, on the compressive/tensile stress of the backside film, the thickness of the film, and the designed pattern/stress distribution profile of the backside film. The back-side pattern applier (250) is the tool or set of tools that produce and deposits the backside pattern to the backside of the subject wafer. As a result, the distortion of the subject wafer is reduced and perhaps eliminated. The amelioration action performed by the backside-pattern applier (250) may be accomplished by depositing one or more films on the backside surface to assist with distortion correction. Fig. 2 shows substrate (255), which is a corrected version of the subject wafer. The substrate (255) has a top surface (257) and a backside surface with a backside film (259) deposited thereon. The backside film (259) is deposited on the backside surface that may, for example, either pulls a substrate inwardly or pushes it outwardly).
Regarding claim 3, Hooge in view of Dai discloses The method according to claim 1, wherein:
the method further includes measuring a second wafer expansion along a second direction parallel to the working surface of the first wafer, the first direction being perpendicular to the second direction; and (Hooge, e.g., see rejection as applied to claim 1; see also fig. 1 illustrating in-plane distortion (IPD) of a wafer (140); examiner notes that an in-plane distortion (IPD) causing horizontal distortion is construed as a second wafer expansion along a second direction; see also col. 2, lines 32-45 disclosing the shape of the example distorted wafer (100) may be caused by stresses or force that act out-of-plane and in-plane. The expansion and contraction forces (i.e., x-direction and y-direction forces) push or pull the wafer in the same plane as the wafer itself and often produce some out-of-plane distortion as represented by the directional arrow of (119). The vertical distortion shown by (116) causes a horizontal movement shown by (120). When the wafer is clamped on a table, the horizontal movement (120) can cause IPD and contribute to overlay; see also col. 3, lines 42-49 disclosing there is also distortion due to the horizontal forces on the wafer. That is, in-plane distortion. At least some of the implementations of the technologies described herein address the IPD of the substrates, which may result from distortions from bending and stretching; see also col. 5, lines 42-63 disclosing chart (140) of fig. 1 is an example of a 2D chart of the estimated in-plane distortion (IPD) data derived from a calculation of the slope of the wafer-shape data. The shading indicates the relative amount of IPD as plotted on the area of the wafer. For a stressed film on one side of the wafer, the slope of the data points in a given direction is proportional to the IPD which contributes to overlay error when the wafer is chucked. The IPD can be approximated to the slope of the wafer bow through this equation
u
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t
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, eqn. 1. The first term represents in the in-plane stretching due to the film stress and the second term represents the bending caused by the film stress. With this equation, the measured wafer bow (which is an example of the wafer shape data) can be converted to IPD).
the determining includes determining the wafer flatness of the first wafer based on the first wafer expansion and the second wafer expansion using the flatness prediction model. (Hooge, e.g., see rejection as applied above and to claim 1; see also fig. 2 and col. 3, lines 50-65 disclosing fig. 2 shows an example wafer distortion amelioration system (200). The example wafer distortion amelioration system (200) is an example of an implementation of the technology described herein. The wafer-shape meter (210) acquires wafer-shape data about a subject wafer (205). The subject wafer (205) is a substrate that exhibits out-of-plane and/or in-plane distortion; see also col. 7, lines 34-43 disclosing ameliorates includes reducing the distortion of the subject wafer. The action may be called a correction. Regardless, the amelioration action results in the application of a backside layer that reduces the out-of-plane and/or in-plane distortion. Various factors go into generating the backside pattern. these factors include at least in part, on the compressive/tensile stress of the backside film, the thickness of the film, and the designed pattern/stress distribution profile of the backside film).
Regarding claim 5, Hooge in view of Dai disclose: The method according to claim 1, wherein
the wafer flatness is indicated by a bow of the first wafer, (Hooge, e.g., see rejection as applied to claim 1, specifically fig. 1 illustrating a “bow” as indicated by (112) and (114); see also charts (130) and (150) illustrating bows from a top view).
the flatness prediction model is a bow prediction model that predicts the bow of the first wafer, and (Hooge, e.g., see rejection above and to claim 1; see also col. 3, lines 1- disclosing a wafer bow (i.e., a first-order distortion) or wafer warm (i.e., second-order distortion) are examples of global distortions and, in particular global out-of-plane distortions. The technology described herein may include a determination of the local distortion of each multiple discretized pixels of a semiconductor wafer. That determination is based on shape data of that wafer. The shape data represents the global distortion of the wafer; see also col. 4, lines 9-25 disclosing note that the entire subject wafer (205) can have bowing (including top surface (207) and that this bowing is at least manifest in the backside surface (209). conventionally, a given substrate can develop a bow or deflection of between 1 and 400 microns; see also equation 3 utilizing plate theory equations; construed by the examiner as a bow prediction model).
the determining includes determining the bow of the first wafer based on the first wafer expansion using the bow prediction model. (Hooge, e.g., see col. 9, line 49 – col. 10, line 17 disclosing the example process (500) implements an approach called the curvature method. this approach accounts for non-uniform film stress and for the correction of shapes that originate from non-equibiaxial stress. The following equations (which are extension of Stoney’s equation) are examples of equations that may be employed that account for non-uniform film stress; e.g., see equation 3. These are examples of the plate theory equations that may be used. Using such equations, the non-uniform film stress can be related to the local curvature. Solving such equations using the measured wafer bow gives the backside correction pattern for the curvature method).
Regarding claim 7, Hooge in view of Dai is not relied upon as explicitly disclosing: The method according to claim 1, wherein the lithography process is a lithography process that is performed closest in time to the fabrication step with the wafer flatness requirement.
However, Dai further discloses: the lithography process is a lithography process that is performed closest in time to the fabrication step with the wafer flatness requirement. (Dai, e.g., see rejection as applied above; see also para. [0068] disclosing to pattern compensation structure (808), a photoresist layer can be first patterned using the specifically designed layout by photolithography and development. The patterned photoresist layer then can be used as an etch mask to etch the exposed portions of film (806) by wet etch and/or dry etch; examiner notes the dry etch is optimally performed on a flat wafer, wherein dry etching a non-flat wafer results in degraded etch performance, uniformity, and critical dimension control, and wherein patterning the wafer to immediately send the wafer to dry etch is construed as “closest in time” as there are no intermediary steps between lithography and dry etch).
Accordingly, it would be prima facie obvious to one of ordinary skill in the art, at the time the invention was effectively filed, to have modified Hooge in view of Dai’s method with Dai’s lithography process is a lithography process that is performed closest in time to the fabrication step with the wafer flatness requirement for at least the reasons that removal of the compensation structure is determined based on the subsequent fabrication processes, as taught by Dai; e.g., see para. [0069].
Regarding claim 9, Hooge in view of Dai is not relied upon as explicitly disclosing: The method according to claim 1, wherein the fabrication step with the wafer flatness requirement is performed after formation of contact structures and word line contacts.
However, Dai further discloses: wherein the fabrication step with the wafer flatness requirement is performed after formation of contact structures and word line contacts. (Dai, e.g., see fig. 1 and paras. [0034]-[0035] disclosing fig. 1A depicts a word line (WL) through array contact (TAC) region (102) of the 3D memory device, including NAND memory string region (110), a TAC region (120), and top select gate (TSG) staircase regions (130). As shown in fig. 1A, WL TAC region (102) can also include a plurality of slit structures (114) each extending laterally in the word line direction and in a stripe shape. At least some slit structures (114) can function as the common source contact for an array of NAND memory strings (112) and NAND memory string regions (110); see also para. [0069] disclosing the timing of removing the compensation structure can be determined based on the current fabrication process and/or subsequent fabrication processes; construed as “the fabrication step with the wafer flatness requirement is performed after”).
Accordingly, it would be prima facie obvious to one of ordinary skill in the art, at the time the invention was effectively filed, to have modified Hooge in view of Dai’s method with Dai’s fabrication step with the wafer flatness requirement is performed after formation of contact structures and word line contacts for at least the reasons that it is known to utilize contacts as alignment anchors for later layers in the semiconductor fabrication process.
Regarding claim 24, Claim 24 discloses A computing apparatus, comprising processing circuitry configured to: store a wafer expansion of a wafer that is collected along a first direction parallel to a working surface of the wafer during a lithography process for patterning structures on the working surface of the wafer; and before a fabrication step with a wafer flatness requirement, determine a wafer flatness of the wafer based on the wafer expansion collected during the lithography process using a flatness prediction model that is configured to predict the wafer flatness., and is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hooge in view of Dai for reasons analogous to those set forth in connection with claim 1. Claim 24 is different than claim 1 in the claim recitation disclosing: A computing apparatus, comprising processing circuitry, wherein Hooge discloses (Hooge, e.g., see col. 11, lines 35-48 disclosing the term “computer-readable media” includes computer storage media, which may include magnetic storage devices, optical disks, and digital versatile disc, smart cards, flash memory devices, and volatile and non-volatile memory. Unless the context indicates otherwise, the term “logic” includes hardware, software, firmware, circuitry, logic circuitry, integrated circuitry, other electronic components and/or combinations thereof that is suitable to perform the functions described for that logic).
Regarding claim 25, Claim 25 recites A non-transitory computer-readable storage medium storing a program executable by one or more processors to perform: storing a wafer expansion of a wafer that is collected along a first direction parallel to a working surface of the wafer during a lithography process for forming structures on the working surface of the wafer; and before a fabrication step with a wafer flatness requirement, determining a wafer flatness of the wafer based on the wafer expansion collected during the lithography process using a flatness prediction model that is configured to predict the wafer flatness., and is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hooge in view of Dai for reasons analogous to those set forth in connection with claim 24.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hooge in view of Dai, in further view of Zach et al. (US 2022/0187718 A1), hereinafter Zach.
Regarding claim 6, Hooge in view Dai disclose The method according to claim 1, wherein:
the flatness prediction model is based on a Finite Element Model; and (Hooge, e.g., see fig. 2 and col. 4, lines 53-60 disclosing that the wafer model (225) is a highly detailed physics model of an initially flat wafer subjected to idealized film stress that is accomplished by use of a Finite Element model which uses the FE method for finite element analysis).
the method further includes:
measuring a wafer expansion of a wafer along a direction that is parallel to the working surface of the second wafer during a lithography process for patterning structures on the working surface of the wafer; (Hooge, e.g., see rejection above; see also fig. 1 illustrating distorted wafer (100) in the three separate distortion poses of (110), (112), and (114); see also fig. 1 and col. 2, line 9 – col. 3, line 49 disclosing OPD and IPD distortion in correlation with a reference plane, wherein expansion and contraction forces push or pull the wafer, represented by directional arrows, and wherein a process or amelioration is conducted to correct global and local distortions; see also col. 3, line 66 – col. 4, line 8 disclosing subject wafer (205) has multiple semiconductor structures that are at least partially fabricated on a top surface (207) of the subject wafer (205). For example, such structures can includes gates, transistors, trenches, vias, hard masks, films, etc. Thus, subject wafer (205) can be a semiconductor-grade substrate; see also col. 5, lines 64-67 disclosing a large portion of the stretching component is accounted for by the lithography tool; see also col. 4, lines 43-46 disclosing chart (130) of fig. 1 is an example of a two-dimensional (2D) chart of the wafer-shape data obtained from a wafer. The shading indicates the out-of-plane (i.e., Z-position) distortion as plotted on the area of the wafer; see also col. 6, lines 41-46 disclosing chart (150) of fig. 1 is an example of a 2D chart of the estimated force from the wafer-shape data. The shading indicates the relative amount of force as plotted on the area of the wafer. This may be calculated by taking the slope of the estimated IPD to get the curvature which is mathematically related to the stress; see also fig. 2 and col. 3, lines 50-60 disclosing the example wafer distortion amelioration system (200) includes a wafer-shape meter (210). the wafer-shape meter (210) acquires wafer-shape data about a subject wafer (205). The subject wafer (205) is a substrate that exhibits out-of-plane and/or in-plane distortion; see also col. 4, lines 26-42 disclosing wafer shape measurements produced on a KLA-Tencore producing x,y, and z measurements relative to deflection tied to a planar coordinate system, wherein concavity and convexity is produced as positive or negative data; examiner notes that the above cited material discloses a wafer-shape meter collecting a shape to include an OPD and/or IPD of the working surface of a wafer and along a lateral/parallel direction as indicated by (130) and/or (150) of fig. 1 during a photolithography process which is utilized for creating a patterning structure of the working surface of said wafer; examiner notes that charts (130) and (150) are necessarily stored first wafer expansions as they are processed by a processor; examiner further notes that the out-of-plane distortion (OPD) is construed as a first wafer expansion along a first direction).
before the fabrication step with the wafer flatness requirement is performed on the wafer, determining a wafer flatness of the wafer based on the wafer expansion of the wafer using the flatness prediction model; and (Hooge, e.g., see rejection as applied above disclosing the first wafer expansion collected during the lithography process and also with regard to Dai in fig. 3 and para. [0032] disclosing wafer flatness; see also fig. 2 illustrating a stress estimator (230), a subject-wafer simulator (220) and model of ideal wafer (225); see also col. 4, line 47 – col. 5, line 41 disclosing spatial filters as a function of Zernike polynomials to describe a wafer shape, wherein a subject-wafer simulator (220) simulates a model subject wafer from the stress estimator (230) and produces a highly detailed physics model of an ideally flat wafer subjected to idealized film stress through the FEM. The wafer simulator discretized the idealized wafer model into a grid or array or chunks (pixels), wherein after the pixelization, amelioration is performed on the pixels of the simulation; e.g., see fig. 3; see also col. 6, line 31 – col. 7, line 22 disclosing utilizing stress estimator (230) and subject-wafer simulator (220) to estimate the forces acting on each pixel, which optimization of estimates occurs and the Fem simulation outputs the distortion to represent a film stress profile, and uses superposition to add up the form of overall distortion; examiner notes that distortions from an ideally flat wafer utilizes a Fem to predict the deviations from an ideal flatness per the model; see also col. 9, lines 23-36 disclosing with some implementations, the system sends information about the adjustments made by the backside layer(s) to one or more tools in the semiconductor fabrication process so that those tools can take the adjustments into consideration for their processes. This may be called feed-forwarding the impact of the amelioration pattern to other tools in the fabrication process; construed as “before a fabrication step with a wafer flatness requirement”).
measuring an actual wafer flatness of the wafer; and (Hooge, e.g., see rejection as applied above to claim 1, specifically with regard to Dai disclosing a wafer flatness in fig. 3 and para. [0032]; see also fig. 5 and col. 10, lines 40-64 disclosing at block (540), the system calculates wafer shape based, at least in part, on custom parameters (545). The custom parameters (545) include, for example, the number of backside layers, the film properties, coverage boundaries, and pixel size. At block (550), the system calculates residual wafer shape. The residual wafer shape is defined as the difference between the shape data of wafer (510) and the calculate wafer shape (540))
updating the flatness prediction model based on the measured wafer flatness of the wafer and the determined wafer flatness of the wafer. (Hooge, e.g., see rejection as applied above and claim 1, specifically with regard to Dai disclosing fig. 3 and para. [0032]; see also col. 10, line 49 – col. 11, line 15 disclosing at block (560), the system updates. The following may be updated: global stress map multiplier, shift stress map uniformity; and non-equibiaxial stress correction pattern. Update adjust parameters to reduce residual wafer shape. These parameters could include: a global stress adjustment, a known stress pattern design to counteract a specific shape, a known shape caused by non-equibiaxial stress behavior, modifications to the slope of the stress between high and low-stress areas, and additional analytical terms to the model. Collectively, blocks (540), (550), and (560) form an optimization loop that is repeated until optimized results are found. In this loop, the system optimizes for the number of analytical terms to include the plate theory equations based on the raw data and solve for the stress. The system optimizes the thickness of a dual stack of compressive or tensile base layer covered by a patterned film of opposing stress determined previously. The system converts the map of the stress into a map of the percentage of corrective coverage of the film. Then the system converts the percentage coverage in a given section to pattern with that percent coverage. The optimization ends when a series of metrics such as residual wafer shape, the residual IPD, local stress variation, etc. meet a predefined value).
Hooge in view of Dai is not relied upon as explicitly disclosing: machine learning algorithm; and a second wafer;
However, Zach further discloses: machine learning algorithm; and a second wafer; (Zach, e.g., see para. [0015] disclosing embodiments of the present disclosure may utilize shape measurements performed on first and second incoming wafers. The conversion of shape data to predicted overlay information may be carried out using machine learning algorithm and/or a mechanical model; see also paras. [0024]-[0025] disclosing as shown in fig. 1B, the wafer metrology sub-system (102) may perform (1) shape measurement son a first wafer; (2) shape measurements on a second wafer. The wafer metrology subsystem (102) may perform a second shape measurement on a second wafer (110b) and then transmit the shape measurement data to the controller (104) via data signal (103b); see also para. [0028] disclosing a first algorithm executed by the controller (104) includes a machine learning algorithm. the machine learning algorithm applied by controller (104) may include any machine learning algorithm known in the art).
Accordingly, it would be prima facie obvious to one of ordinary skill in the art, at the time the invention was effectively filed, to have modified Hooge in view of Dai’s method with Zach’s machine learning algorithm and second wafer for at least the reasons that performing a fabrication process in batches; e.g., more than one wafer, is common due to the cost savings of associated with batch processing, wherein machine learning is known in the art as a component that increases efficiency and optimization in identifying data in measurements for immediate correction.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hooge in view of Dai, in further view of Liu (US 2020/0350287 A1), hereinafter Liu.
Regarding claim 10, Hooge in view of Dai is not relied upon as explicitly disclosing: The method according to claim 1, wherein the structures include contact structures and word line contacts, and the lithography process patterns the contact structures and the word line contacts.
However, Dai further discloses: wherein the structures include contact structures and word line contacts, and (Dai, e.g., see fig. 1 and paras. [0034]-[0035] disclosing fig. 1A depicts a word line (WL) through array contact (TAC) region (102) of the 3D memory device, including NAND memory string region (110), a TAC region (120), and top select gate (TSG) staircase regions (130). As shown in fig. 1A, WL TAC region (102) can also include a plurality of slit structures (114) each extending laterally in the word line direction and in a stripe shape. At least some slit structures (114) can function as the common source contact for an array of NAND memory strings (112) and NAND memory string regions (110)).
Accordingly, it would be prima facie obvious to one of ordinary skill in the art, at the time the invention was effectively filed, to have modified Hooge in view of Dai’s method with Dai’s structures include contact structures and word line contacts for at least the reasons that contacts and word line contacts help in ensuring of alignment, pattern fidelity, and overall device reliability.
Hooge in view of Dai is not relied upon as explicitly disclosing: the lithography process patterns the contact structures and the word line contacts.
However, Liu further discloses: the lithography process patterns the contact structures and the word line contacts. (Liu, e.g., see paras. [0071]-[0073] disclosing as illustrated in fig. 5B, an array of 3D XPoint memory cells (506) are formed above and in contact with some transistors (504) 9e.g., ones that form the peripheral circuit of array of 3D XPoint memory cells (506). To form 3D XPoint memory cells (506), perpendicular conductors can be formed as word lines (WL) (507) and bit lines (508). 3D XPoint memory cells (506) can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP and any other suitable processes. Method (900) proceeds to operation (906), as illustrated in fig. 9, in which a first bonding layer is formed above the first interconnect layer. The first bonding layer can include a plurality of first bonding contacts. As illustrated in fig. 5C, a bonding layer is formed above interconnected layer (512). Bonding layer (514) can include a plurality of bonding contacts (516) surrounded by dielectrics. Bonding contacts (516) then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer (512) by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer)).
Accordingly, it would be prima facie obvious to one of ordinary skill in the art, at the time the invention was effectively filed, to have modified Hooge in view of Dai’s method with Liu’s lithography process patterns the contact structures and the word line contacts for at least the reasons that patterning contact structures and word line contacts during a lithography process constrains critical dimensions for later patterning as well as stabilize topography.
Conclusion
Claims 4 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
US 2024/0003010 A1 to Huang et al. relates to backside deposition and local stress modulation for wafer bow compensation.
US 2023/0136819 A1 to Porter et al. relates to control of wafer bow during integrated circuit processing.
US 2022/0074869 A1 to Arora et al. relates to integrated wafer bow measurements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC S. VON WALD whose telephone number is (571)272-7116. The examiner can normally be reached Monday - Friday 7:30 - 5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Rastovski can be reached at (571) 270-0349. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/E.S.V./Examiner, Art Unit 2863
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2863