DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed March 2nd, 2026. Claims 1-30 are pending, of which claims 1-10 and 21-30 are currently rejected. Claims 11-20 have been cancelled by Applicant.
Election/Restrictions
Applicant’s election of claims 1-10 and 21-30 in the reply filed on 03/02/2026 is acknowledged. Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/02/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/12/2024 is in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claim 28 is objected to because of the following informalities:
Claim 28 is improperly annotated: “(The) system of claim 27” should be “(New) The system of claim 27”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Double Patenting Rejection #1
Claims 1-5 and 7-10 is rejected on the ground of non-statutory double patenting as being unpatentable over claims 6-13 of U.S. Patent Application No. US 2024/0069864 (hereinafter “the ‘864 patent application”).
Current Application: 17/876378
U.S. Application No. US 2024/0069864
Claim 1: A device, comprising:
a plurality of integer multiplier circuits;
a multiplexer circuit configured to provide portions of mantissas of a plurality of feature elements and portions of mantissas of a plurality of weight elements to respective integer multiplier circuits of the plurality of integer multiplier circuits, wherein the feature elements and the weight elements are floating-point data types, and wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a feature element by a respective portion of the mantissa of a weight element to generate a partial product;
a first shift circuit configured to shift bits of the partial products based on exponents of the plurality of feature elements and of the plurality of the weight elements;
a first integer adder circuit configured to add the shifted partial products to generate a sum; and
a composition circuit configured to generate an output element based on the sum generated by the first integer adder circuit, the exponents of the plurality of feature elements, and the exponents of the plurality of weight elements.
Claim 1: A device, comprising:
a plurality of integer multiplier circuits;
a multiplexer circuit configured to provide portions of mantissas of a plurality of feature elements and portions of mantissas of a plurality of weight elements to respective integer multiplier circuits of the plurality of integer multiplier circuits, wherein the feature elements and the weight elements are floating-point data types, and wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a feature element by a respective portion of the mantissa of a weight element to generate a partial product; and
(claim 6: a first shift circuit configured to shift bits of the partial products based on the exponents of the set of first data elements and of the set of second data elements;
a first integer adder circuit configured to add the shifted partial products to generate a sum; and
a composition circuit configured to generate the output data element based on the sum generated by the first integer adder circuit)
output circuits configured to generate an output data element based on the partial products generated by the plurality of integer multiplier circuits and exponents of the set of first data elements and of the set of second data elements.
Claim 6-13 of the ‘864 patent application fully anticipates claim 1-5 and 7-10 of the instant application. All the limitations contained within Claims 1-5 and 7-10 of the instant application are found within claim 6-14 of the ‘864 patent application as shown in the table above.
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 30 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Urbanski et al. (EP 3 857 353) included in the IDS filed on 02/12/2024 (hereinafter “Urbanski”).
Regarding claim 1, Urbanski teaches:
A device, comprising:
a plurality of integer multiplier circuits (¶ 0073 and Fig. 12 plurality of fixed point multipliers as integer multipliers 1234);
a multiplexer circuit configured to provide portions of mantissas of a plurality of feature elements and portions of mantissas of a plurality of weight elements to respective integer multiplier circuits of the plurality of integer multiplier circuits (¶ 0073 and fig. 12 1230 and 1232 multiplexers to provide mantissas of feature elements and weight elements to respective integer multiplier circuits),
wherein the feature elements and the weight elements are floating-point data types (¶ 0071 -¶ 0072 inputs received both A and B are floating point types), and wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a feature element by a respective portion of the mantissa of a weight element to generate a partial product (¶ 0073 discusses multiplication of A and B i.e., weight and feature mantissas in order to generate a partial product);
a first shift circuit configured to shift bits of the partial products based on exponents of the plurality of feature elements and of the plurality of the weight elements (¶ 0073 shifter circuits shift products from multipliers based on exponent bits Fig. 1336);
a first integer adder circuit configured to add the shifted partial products to generate a sum (¶ 0073 adders receive output from shifter circuits and add partial products, Fig. 12 1246); and
a composition circuit configured to generate an output element based on the sum generated by the first integer adder circuit, the exponents of the plurality of feature elements, and the exponents of the plurality of weight elements (Fig. 12 1270 output FP conversion as composition circuit for outputting the final result).
Regarding claim 2, Urbanski teaches:
The device of claim 1, wherein the plurality of feature elements are paired with the plurality of weight elements, respectively, to form a plurality of feature-weight pairs (¶ 0073 A and B inputs i.e., feature and weight elements are paired up to be multiplied by respective multipliers),
wherein the device further comprises an exponent circuit (Fig. 12 elements 1214, 1216, 1240 as exponent add circuit) configured to:
add the exponents of the feature element and the weight element for each feature-weight pair to generate a respective exponent sum (¶ 0071 -¶ 0072 describe separating of inputs into exponents, mantissas, and sign bits, exponents are provided to exponent add circuit, Fig. 12 elements 1214, 1216, 1240 as exponent add circuit);
determine a maximum exponent sum from the respective exponent sums (Fig. 12 1240 determines max exponent sum; ¶ 0073); and
for each feature-weight pair, determine a difference between the maximum component sum and the respective exponent sum (Fig. 12 1240 as described in ¶ 0073 determines a difference between max exponent sum and respective exponent sum),
wherein the first shift circuit is configured to shift the bits of the partial products based on the respective differences between the maximum component sum and the respective exponent sums (Fig. 12 1240 output is provided to shifter circuits 1236, so shifting occurs with respect to this value as described in ¶ 0073), and
wherein the output element is generated based on the maximum exponent sum (max exponent sum and respective differences are used in shifter circuits 1236, hence output provided by 1270 will be based on this max exponent sum and respective differences.).
Regarding claim 3, Urbanski teaches:
The device of claim 2, further comprising:
a sign circuit configured to determine an output sign for each feature-weight pair based on sign bits of the respective feature elements and weight elements (Fig. 12 1226 1228; ¶ 0073); and
a conversion circuit configured to generate two's complements of the shifted partial products based on the respective output signs prior to being added by the first integer adder circuit (Fig. 12 1242 numeric conversion circuit to convert output to 2s complement before entering the first integer adder circuit, as explained in ¶ 0073).
Regarding claim 4, Urbanski teaches:
The device of claim 3, wherein the composition circuit is further configured to:
convert the sum generated by the first integer adder circuit from two's complement to signed-magnitude format (¶ 0030 after summation the output is converted to sign and magnitude format, normalized, and rounded to bit length); and
round the converted sum to a predetermined bit length (Fig. 12 1250 normalization and rounding to bit length; ¶ 0030),
wherein a sign bit of the output element is based on the converted sum, an exponent of the output element is based on the determined maximum exponent sum, and a mantissa of the output element is based on the rounded sum (Fig. 12 output at 1270 has corresponding sign bit, exponent based on maximum exponent sum computation of 1240, 1264 and mantissa is based on rounded sum from 1250).
Claim 30 recites the method practiced by the device of claim 1 and is therefore rejected for the same reasons therein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Urbanski.
While Urbanski in the embodiment shown in Fig. 12 shows the device of claim 4, this embodiment of Urbanski does not teach adjusting the maximum exponent sum based on the normalization of the rounded sum.
However, Urbanski in the embodiment shown in Fig. 13 teaches normalizing of the rounded sum occurring at 1350, and at 1360 adjusting of the maximum exponent based on the normalization as explained in ¶ 0100.
It would be obvious before the effective filing date of the claimed invention to combine the adjustment of the maximum exponent based on the normalization as taught by the Fig. 13 embodiment of Urbanski with the device as taught by the Fig. 12 embodiment of Urbanski as both embodiments are directed towards a device for floating point multiply add operations. One with ordinary skill in art would be motivated to combine the teachings because doing so would provide a lesser error prone (Urbanski: ¶ 0090).
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Urbanski further in view of Kim et al. (US 2021/0312012 A1) (hereinafter “Kim”).
Regarding claim 6, while Urbanski teaches the device of claim 5, Urbanski does not explicitly teach the bit size of the mantissas being greater than the bit size of the multipliers.
However, Kim teaches:
wherein a bit size of the mantissas of the plurality of feature elements and the plurality of weight elements is greater than a bit size of the 3 plurality of integer multiplier circuits (Kim: ¶ 0041 inputs are 16 bits in length and are broken down into pieces to be processed i.e., mantissa portions, while multipliers are 11 bit length ¶ 0083, multipliers are used in integer calculation mode ¶ 0038; Fig. 7A shows one bit multiplier, however it accepts are number of inputs not just two, this would require multiple multipliers being provided to multiplier).
It would be obvious before the effective filing date to combine the bit size of the inputs as compared to the bit size of the multipliers as taught by Kim with the device as taught by Urbanski as both teachings are directed towards floating-point multiplications being implemented with integer operations. One with ordinary skill in the art would be motivated to combine the teachings because the power consumption and size of the device may be improved by implementing the computations in this way (Kim: ¶ 0156).
Regarding claim 7, Urbanski in view of Kim further teaches:
The device of claim 6, wherein the multiplexer circuit is further configured to, for each feature-weight pair (Kim: Fig. 10 mantissa portions IN_A1-IN_A4 and IN_B1-IN_B4 are chosen by multiplexers M11-M61 and corresponding multiplications are routed to various multipliers F_mul1-F_mul4):
provide different portions of the mantissa of the feature element to different 4 respective integer multiplier circuits (Kim: Fig. 7A shows one bit multiplier, however it accepts are number of inputs (not just two), this would require multiple multipliers being provided to multiplier, portions of inputs i.e., mantissas IN_A1-IN_A4 and IN_B1-IN_B4); and
provide one portion of the mantissa of the corresponding weight element to each of the different respective integer multiplier circuits (Kim: Fig. 7A shows one bit multiplier, however it accepts are number of inputs (not just two), this would require multiple multipliers being provided to multiplier, portions of inputs i.e., mantissas IN_A1-IN_A4 and IN_B1-IN_B4),
wherein a different portion of the mantissa of the corresponding weight element is provided to each of the different respective integer multiplier circuits during different cycles of the device (Kim: Fig. 3 different portions of activation i.e., feature elements provided to different MACs i.e., multipliers in the array).
Regarding claim 8, Urbanski in view of Kim teaches a plurality of shift circuits, and a plurality of integer adder circuits having a second of each respectively (Urbanski: Fig. 12 shift circuits 1236 and the rest of the group; Fig. 12 adder circuits 1246 and the rest of the group), wherein the second shift circuit output are taken in by the second integer adder circuit which provide a sum of partial products and accordingly is processed by the conversion circuit.
Regarding claim 9, Urbanski in view of Kim teaches a plurality of shift circuits, and a plurality of integer adder circuits having a third of each respectively (Urbanski: Fig. 12 shift circuits 1236 and the rest of the group; Fig. 12 adder circuits 1246 and the rest of the group), wherein the third shift circuits output are taken in by the third integer adder circuit which provide a sum of partial products and accordingly is processed by the conversion circuit.
Regarding claim 10, Urbanski in view of Kim further teaches:
The device of claim 9, wherein the composition circuit is configured to provide the output element to an accumulator circuit (Urbanski: ¶ 0076).
Claims 21-30 are rejected under 35 U.S.C. 103 as being unpatentable over Urbanski further in view of Kaul et al. (US 2018/0315398 A1) (hereinafter “Kaul”).
Regarding claim 21, Kaul teaches a CNN for floating-point multiply add operations through convolutional layers (Kaul: ¶ 0153 and ¶ 0159).
Kaul does not teach:
a plurality of integer multiplier circuits;
a multiplexer circuit configured to provide portions of mantissas of a plurality of feature elements and portions of mantissas of a plurality of weight elements to respective integer multiplier circuits of the plurality of integer multiplier circuits, wherein the feature elements and the weight elements are floating-point data types, and wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a feature element by a respective portion of the mantissa of a weight element to generate a partial product;
a first shift circuit configured to shift bits of the partial products based on exponents of the plurality of feature elements and of the plurality of the weight elements;
a first integer adder circuit configured to add the shifted partial products to generate a sum; and
a composition circuit configured to generate an output element based on the sum generated by the first integer adder circuit, the exponents of the plurality of feature elements, and the exponents of the plurality of weight elements.
However, Urbanski teaches:
a plurality of integer multiplier circuits (Urbanski: ¶ 0073 and Fig. 12 plurality of fixed point multipliers as integer multipliers 1234);
a multiplexer circuit configured to provide portions of mantissas of a plurality of feature elements and portions of mantissas of a plurality of weight elements to respective integer multiplier circuits of the plurality of integer multiplier circuits (Urbanski: ¶ 0073 and Fig. 12 1230 and 1232 multiplexers to provide mantissas of feature elements and weight elements to respective integer multiplier circuits),
wherein the feature elements and the weight elements are floating-point data types (Urbanski: ¶ 0071 -¶ 0072 inputs received both A and B are floating point types), and wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a feature element by a respective portion of the mantissa of a weight element to generate a partial product (Urbanski: ¶ 0073 discusses multiplication of A and B i.e., weight and feature mantissas in order to generate a partial product);
a first shift circuit configured to shift bits of the partial products based on exponents of the plurality of feature elements and of the plurality of the weight elements (Urbanski: ¶ 0073 shifter circuits shift products from multipliers based on exponent bits Fig. 1336);
a first integer adder circuit configured to add the shifted partial products to generate a sum (Urbanski: ¶ 0073 adders receive output from shifter circuits and add partial products, Fig. 12 1246); and
a composition circuit configured to generate an output element based on the sum generated by the first integer adder circuit, the exponents of the plurality of feature elements, and the exponents of the plurality of weight elements (Urbanski: Fig. 12 1270 output FP conversion as composition circuit for outputting the final result).
In combining Kaul and Urbanski, each convolutional layer of Kaul as depicted in Fig. 2A would have at each cluster 214 within the processing array of 212, the circuits as taught by Urbanski in Fig. 12 (as mapped above).
It would be obvious before the effective filing date of the claimed invention to combine each convolutional layer having the circuits as taught by Urbanski with the convolutional neural network as taught by Kaul as both teachings are directed towards computations of floating point operands. One with ordinary skill in the art would be motivated to combine the teachings because doing so would provide less error prone results, have a lower gate count, and a smaller area for the device (Urbanski: ¶ 0090).
Regarding claim 22, Kaul in view of Urbanski further teaches:
The system of claim 21, wherein the system is configured to perform machine learning operations (Kaul: ¶ 0153 and ¶ 0159 CNN for floating-point multiply add operations).
Regarding claim 23, Kaul in view of Urbanski further teaches:
The system of claim 21, further comprising a command register configured to store a command for a convolution operation (Kaul: ¶ 0053 command buffer for containing commands to run convolution operations).
Regarding claim 24, Kaul in view of Urbanski further teaches:
The system of claim 23, wherein the command comprises one or more parameters for the convolution operation (Kaul: ¶ 0059 commands containing parameters for how to process inputs), the one or more parameters comprising at least one parameter indicating that the feature elements and the weight elements are floating point data types (Kaul: ¶ 0300 contains field for relevant data 3206 needed for command to process, relevant data being inputs which are floating point).
Regarding claim 25, Kaul in view of Urbanski further teaches:
The system of claim 24, further comprising a controller circuit configured to parse the command for a convolution operation and configure the convolution layer based at least in part on the one or more parameters (Kaul: ¶ 0186 control logic to be used for parsing of command and directing of inputs throughout processor, Fig. 2 controller circuit as 222 + 218 + 216 + 204 as described in ¶ 0059).
Regarding claim 26, Kaul in view of Urbanski further teaches:
The system of claim 25, wherein the command register is incorporated into the controller circuit (Kaul: ¶ 0059 command buffer incorporated as part of controller circuit, is what provides data to be processed in clusters).
Regarding claim 27, Kaul in view of Urbanski further teaches:
The system of claim 23, further comprising a scheduler configured to coordinate operations of a plurality of layers in a convolutional neural network (CNN), the plurality of layers comprising the convolution layer (Kaul: ¶ 0054 scheduler for coordinating operations of processing array; ¶ 0175 splitting of computations across layers, which must be split up by scheduler in order to be processed accordingly).
Regarding claim 28, Kaul in view of Urbanski further teaches:
The system of claim 27, wherein the scheduler writes the command to the command register (Kaul: ¶ 0053 command buffer for containing commands to run convolution operations; ¶ 0054 scheduler for coordinating operations of processing array).
Regarding claim 29, Kaul in view of Urbanski further teaches:
The system of claim 21, further comprising an accumulation circuit, wherein the composition circuit is configured to provide the output element to the accumulation circuit (Urbanski: ¶ 0076).
The motivation to combine with respect to claim 11 applies equally to claim 29.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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