DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6-9, 11-17 and 19-25 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tsai et al. (US 2021/0125875) hereinafter “Tsai”.
Regarding claim 6, Figs. 9, 10A-10C and 13 of Tsai teaches a method comprising: fabricating on a substrate (Item 20) a device comprising a first transistor in a first active region (See Picture 1 below), a second transistor in a second active region (See Picture 1 below) and a sacrificial gate structure (Combination of Items 34, 32 and 25) at a boundary (See Picture 1 below) between the first active region and the second active region; each of the first transistor, the second transistor and the sacrificial gate structure comprises (a) a fin channel (Items 24 or 25) extending from the substrate (Item 20) and (b) one or more gate layers (Items 34 and 32) over the fin channel (Items 24 or 25), each of the first transistor and the second transistor further comprises source/drain feature (Item 42); and forming a tapered trench (Fig. 13 Item 56 which includes both air and Item 54) at the boundary between the first active region and the second active region, wherein said forming comprises, in a single continuous etching step (Paragraph 0040 where one etching process may be used and 0045 where one plasma etching process is used which comprises multiple cycles), etching the one or more gate layers (Items 34 and 32) of the sacrificial gate structure, the fin channel (Item 25) underneath the one or more gate layers of the sacrificial gate structure, and a portion of the substrate (Paragraph 0048 where the trench extends into the substrate) at the boundary between the first active region and the second active region, wherein a width of the tapered trench (Item 56 which includes both air and Item 54) at a top of the fin channel (Item 25) is greater than a width of the tapered trench at a bottom of the one or more gate layers (Items 34 and 32) of the sacrificial gate structure (Paragraph 0041), without performing a separate etching for the fin channel and the portion of the substrate after etching the one or more gate layers (Paragraph 0045 where the plasma etching process may include multiple cycles utilizing various etchants effective for etching the isolation opening; Further the etching of the isolation opening using the multiple cycles is not interrupted by any other processing step and thus is continuous).
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Picture 1 (Labeled version of Tsai Fig. 9)
Regarding claim 7, Tsai further teaches where the single continuous etching step is a dry etching step (Paragraph 0040).
Regarding claim 8, Tsai further teaches where the one or more gate layers (Items 34 and 32) over the fin channel (Item 25) of the sacrificial gate structure comprise a metal gate layer (Item 34; Paragraph 0024) and a dielectric gate layer (Item 32; Paragraph 0024) and wherein the single continuous etching comprises etching the metal gate layer (Item 34) and the dielectric gate layer (Item 32).
Regarding claim 9, Fig. 13 of Tsai further teaches where a portion of the metal gate layer (Item 34) and the dielectric gate layer (Item 32) along a tapered wall of the trench remains intact upon the etching.
Regarding claim 11, Tsai further teaches filling the tapered trench (Item 56) with a dielectric material (Item 60’; Paragraph 0049).
Regarding claim 12, Tsai further teaches where the dielectric material (Item 60’) is silicon nitride (Paragraph 0049).
Regarding claim 13, Tsai further teaches where each of the first transistor and the second transistor (See Picture 1 above) comprises a FinFET transistor (Paragraph 0005).
Regarding claim 14, Figs. 9, 10A-10C and 13 of Tsai teaches a method of fabricating a semiconductor device, comprising: providing a sacrificial structure (Combination of Items 34, 32 and 25) on a substrate (Item 20), the sacrificial structure comprises (a) a fin channel (Item 25) extending from the substrate (Item 20) and (b) one or more gate layers (Items 34 and 32) wrapping over the fin channel (Item 25), the sacrificial structure (Combination of Items 34, 32 and 25) is disposed at an active edge adjacent to an active region, and etching, in a single continuous etching step (Paragraph 0040 where one etching process may be used and 0045 where one plasma etching process is used which comprises multiple cycles), the one or more gate layers (Items 34 and 32) of the sacrificial structure, the fin channel (Item 25) of the sacrificial structure and a portion of the substrate (Paragraph 0048 where the trench extends into the substrate) underneath the sacrificial gate structure to form a trench (Item 56 which includes both air and Item 54) having a tapered profile, wherein a width of the trench (Item 56 which includes both air and Item 54) at a top of the fin channel (Item 25) is greater than a width of the trench at a bottom of the one or more gate layers (Items 34 and 32) (Paragraph 0041), and wherein the etching does not damage a source/drain feature (Item 42) within the adjacent active region, without performing a separate etching for the fin channel and the portion of the substrate after etching the one or more gate layers (Paragraph 0045 where the plasma etching process may include multiple cycles utilizing various etchants effective for etching the isolation opening; Further the etching of the isolation opening using the multiple cycles is not interrupted by any other processing step and thus is continuous).
Regarding claim 15, Tsai further teaches where the etching is dry etching (Paragraph 0040).
Regarding claim 16, Tsai further teaches where the one or more gate layers (Items 34 and 32) over the fin channel (Item 25) of the sacrificial gate structure comprise a metal gate layer (Item 34; Paragraph 0024) and a dielectric gate layer (Item 32; Paragraph 0024) and wherein the continuously etching comprises etching the metal gate layer (Item 34) and the dielectric gate layer (Item 32).
Regarding claim 17, Fig. 13 of Tsai further teaches where a portion of the metal gate layer (Item 34) and the dielectric gate layer (Item 32) along a tapered wall of the trench remains intact upon the etching.
Regarding claim 19, Tsai further teaches filling the trench (Item 56) with a dielectric material (Item 60’; Paragraph 0049).
Regarding claim 20, Tsai further teaches where the dielectric material (Item 60’) is silicon nitride (Paragraph 0049).
Regarding claim 21, Figs. 9, 10A-10C and 13 of Tsai teaches a method comprising: fabricating on a substrate (Item 20) a device comprising a first transistor in a first active region (See Picture 1 above), a second transistor in a second active region (See Picture 1 above) and a sacrificial gate structure (Combination of Items 34, 32 and 25) at a boundary (See Picture 1 above) between the first active region and the second active region; each of the first transistor, the second transistor and the sacrificial gate structure comprises (a) a fin channel (Items 24 or 25) extending from the substrate (Item 20) and (b) one or more gate layers (Items 34 and 32) over the fin channel (Items 24 or 25), each of the first transistor and the second transistor further comprises source/drain feature (Item 42); and forming a trench (Fig. 13 Item 56 which includes both air and Item 54) at the boundary between the first active region and the second active region, wherein said forming comprises etching, in a single continuous etching step (Paragraph 0040 where one etching process may be used and 0045 where one plasma etching process is used which comprises multiple cycles), the one or more gate layers (Items 34 and 32) of the sacrificial gate structure, the fin channel (Item 25) underneath the one or more gate layers of the sacrificial gate structure and a portion of the substrate (Paragraph 0048 where the trench extends into the substrate) at the boundary between the first active region and the second active region, wherein an angle between a tapered wall of the trench (Item 56 which includes air and Item 54) and a first direction (Left to right across the page) perpendicular to a second direction (Up and down across the page) in which the fin channel protrudes from the substrate (Item 20) is from about 45 degrees to less than about 90 degrees (Paragraph 0041).
Regarding claim 22, Tsai further teaches where a width of the trench (Item 56) at a top of the fin channel (Item 25) is greater than a width of the trench at a bottom of the one or more gate layers (Combination of Items 34 and 32) of the sacrificial gate structure (Paragraph 0041).
Regarding claim 23, Tsai further teaches where the angle between the tapered wall of the trench (Item 56 which includes air and Item 54) and the first direction is from about 45 degrees to about 80 degrees (Paragraph 0041).
Regarding claim 24, Tsai further teaches where the trench (Item 56 which includes air and Item 54) has a tapered wall (Paragraph 0041) having a tapered portion, wherein an angle between the tapered portion of the tapered wall of the trench and a first direction (Left to right across the page) perpendicular to a second direction (Up and down across the page) in which the fin channel (Item 25) protrudes from the substrate (Item 20) is from about 45 degrees to less than about 90 degrees (Paragraph 0041).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 2021/0125875) hereinafter “Tsai” in view of Tsai et al. (US 2020/0035800) hereinafter “Tsai2”.
Regarding claim 10, Tsai teaches all of the elements of the claimed invention as stated above except where the dielectric gate layer comprises a high-k dielectric gate layer.
Tsai2 teaches where a dielectric gate layer is made of a high-k dielectric material (Paragraph 0034).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric gate layer comprise a high-k dielectric layer because this material is known to act as a dummy gate dielectric material in a replacement gate process (Paragraph 0034) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 18, Tsai teaches all of the elements of the claimed invention as stated above except where the dielectric gate layer comprises a high-k dielectric gate layer.
Tsai2 teaches where a dielectric gate layer is made of a high-k dielectric material (Paragraph 0034).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric gate layer comprise a high-k dielectric layer because this material is known to act as a dummy gate dielectric material in a replacement gate process (Paragraph 0034) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 2021/0125875) hereinafter “Tsai” in view of Zhou et al. (US 2020/0126867) hereinafter “Zhou”.
Regarding claim 26, Tsai teaches all of the elements of the claimed invention as stated above.
Fig. 5A of Tsai further teaches where a gate spacer (Item 38) runs along side a gate (Item 30) in one direction such that the gate spacer (Item 38) is between a trench isolation (After processing, in the location where fin Item 25 is located) and a source/drain feature (Item 42).
While the drawings in Tsai seem to show the trench being formed such that a distance from the tapered wall of the trench to an adjacent source/drain feature is greater than a spacer thickness of a spacer disposed between the trench and the adjacent source/drain feature, Tsai does not explicitly teach where the trench is formed such that a distance from the tapered wall of the trench to an adjacent source/drain feature is greater than a spacer thickness of a spacer disposed between the trench and the adjacent source/drain feature.
Zhou teaches where a pitch between fins is between 25 and 60 nm and a thickness of a gate spacer is between 2 and 10 nm (Paragraph 0035).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a pitch between fins be between 25 and 60 nm and a thickness of a gate spacer between 2 and 10 nm because these are known to form effective Finfets having three dimensional configurations (Zhou Paragraph 0002).
As the tapered wall of the trench extending into the substrate is at least as narrow as a fin, in the location of a fin, and a source/drain feature has a side that coincides with a side of another fin, a distance between the tapered wall of the trench and the source/drain feature is effectively a pitch between fins (which when combined with Zhou is between 25 and 60 nm). Thus, when Zhou is combined with Tsai, the trench would be formed such that a distance from the tapered wall of the trench to an adjacent source/drain feature (25-60 nm) is greater than a spacer thickness (2-10 nm) of a spacer disposed between the trench and the adjacent source/drain feature.
Response to Arguments
Applicant's arguments filed 04/10/2026 have been fully considered but they are not persuasive.
Specifically, the Applicant argues that statement in Tsai from paragraph 0039 which states that the opening may be formed using “one or more suitable etching processes” means that a single continuous etching step is not used to form the trench. The Examiner disagrees. Firstly, the portion of Tsai paragraph 0039 recited by the Applicant states one OR more suitable etching processes. This means that Tsai anticipates that one suitable etching process may be appropriate to form the trench. Secondly, even if more than one suitable etching process may be used this does not prevent Tsai from reading on the claim language. The language of claim 6 merely requires a single continuous etching step. Northing in the claim requires that the same processing conditions (i.e. consistent temperature, consistent etchant) are used throughout the single continuous etching step. Paragraph 0045 of Tsai teaches where a single continuous plasma etching process may include multiple cycles using various etchants effective for the etching of the gate isolation openings. The Examiner avers that an etching step may include multiple etching processes and still be considered continuous as long as the etching of the structures is not interrupted by any additional processes. The Examiner uses an analogy of a triathalon. A triathalon is a continuous event which is made up of three different activities which all happen in succession. The Applicant also argues that the specification specifically distinguishes the Applicant’s invention from the prior art by stating that the inventive method utilizes a single continuous etching process as opposed to multistep etching. The Applicant specifically recites from their specification which states “Trench 814, including its portions 814A and 814B, are formed in a single continuous etching step using the same etching process.” However, as stated above, the claim language is silent as to any continuous processing conditions throughout the etching of the claimed trench into multiple structures. Therefore, the single continuous processing step may comprise multiple etching processing conditions which all take place successively to etch a single trench. As such, the Examiner does not find the Applicant’s arguments persuasive and maintains the reliance on Tsai to teach a single continuous etching step.
The Applicant next argues that Tsai does not teach “a width of the tapered trench at a top of the fin channel is greater than a width of the trench at a bottom of the one or more gate layers of the sacrificial gate structure.” The Applicant states that Tsai teaches contrary to the claimed width. The Examiner disagrees. Fig. 13 of Tsai specifically shows where the trench (Which the Examiner identifies as Item 56 which includes Items 54 inside of it) is tapered such that a top width of the trench is wider than a bottom width of the trench and that the trench uniformly narrows (has a consistent taper) as the depth of the trench increases. Fig. 11B makes this relationship even clearer where it identifies W1 as being at the top of the trench and W2 at the bottom of the trench and Paragraph 0041 which explicitly states “a gate isolation opening 56 may have an upper width W1 that is larger than its lower width W2”. The other embodiments discussed in Tsai, as stated by the Applicant in their arguments which may teach a different relationship does not negate the explicit teaching in Tsai of at least one embodiment where the trench narrows as it gets deeper into the structure. As such, the Examiner does not find the Applicant’s arguments persuasive and maintains the reliance on Tsai to teach the claimed relationship of the tapered trench width at the top vs the bottom.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
