DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed July 29th, 2022. Claims 1-20 are pending, of which claims 1-20 are currently rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/25/2024 is in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claims 4-9 are objected to because of the following informalities which recite grammatical issues:
Claim 4 line 3 “interpolation circuit” should be “interpolation logic circuit”
Claims 5-9 are objected to based on their dependence upon claim 4
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
The following limitations are interpreted as invoking 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
Claim 10, “input stage configured to receive an input floating-point element and provide the input floating-point element of the function unit”. The corresponding structure in the disclosure for performing the claimed receiving of an input floating-point element and providing the input floating-point element of the function unit is disclosed in [0016] of the instant specification.
Claim 10, “output stage configured to receive an output floating point element from the function unit and buffer the output floating-point element for transfer out of the device”. The corresponding structure in the disclosure for performing the claimed receiving of an output floating-point element from the function and buffer the output floating-point element for transfer out of the device is disclosed in [0018] of the instant specification.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “the second factor” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required.
Because claim 14 depends upon claim 13, claim 13 is additionally rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paul et al. (“A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations”, 2009) (hereinafter “Paul”).
Paul teaches:
A device comprising:
A function unit;
a controller configured to load a plurality of lookup table entries (Paul: Section III first paragraph “LUT-based approach”, section III, first paragraph; Pg. 273 Lines 6-9 LOD i.e. controller searches for a first “1” bit in order to determine which LUT entries to access i.e., load) into the function unit and to configure the function unit for a non-linear function (Paul: in the title “Logarithm”, “Antilogarithm” i.e., non-linear function);
an input stage configured to receive an input floating-point element and provide the input floating-point element to the function unit (Paul: Pg. 273 Fig. 5 input stage receives floating point numbers and provides to function unit, function unit being all the boxes starting from Look-Up Table and LOD and ending at ADD/SUB block, input stage indicated by box below); and
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an output stage configured to receive an output floating-point element from the function unit and buffer the output floating-point element for transfer out of the device (Paul: Pg. 273 Fig. 5 output stage at output of ADD/SUB block as evidenced by Pg. 273 Col. 1 Lines 15-19 after ADD/SUB shifting must occur for final output, buffer i.e., shifter; Pg. 274 Fig. 4 shows result is obtained after Adder, the result having output sign, mantissa, and exponent),
wherein the function unit is configured to:
interpolate an output mantissa based on the input mantissa of the input floating-point element and first and second sampled mantissas sampled from the non-linear function and retrieved from the lookup table entries (Paul: Pg. 271 k is the total number of MSBs in the mantissa used for the interpolation”; Pg. 271 Fig. 2 first and second mantissas as a and b respectively for samples i and i+1; Pg. 272 Fig. 4 shows interpolator that takes input mantissa to interpolate);
generate an output exponent based on an input exponent of the input floating-point element and the non-linear function (Paul: Pg. 269 Col. 2 Eqn (1) shows the format of the numbers used as disclosed, having an exponent, sign and mantissa; Pg. 272 Section C discusses the exponent part becoming part of the decimal of the mantissa, computations involve this part of the mantissa, therefore the output will include an output exponent);
generate an output sign based on an input sign of the input floating-point element the non-linear function (Paul: Pg. 269 Col. 2 Equation (1) and paragraph following shows input value X having an sign, interpolation for non-linear function is computed throughout the process, hence output value should also have a sign, the sign being positive since a logarithm is being computed); and
generate the output floating-point element comprising the output sign, the output exponent, and the output mantissa (Paul: Pg. 269 Col. 2 Eqn (1) shows the format of the numbers used as disclosed, having an exponent, sign and mantissa; Pg. 272 Section C discusses the exponent part becoming part of the decimal of the mantissa, computations involve this part of the mantissa, therefore the output will include an output exponent; Pg. 269 Col. 2 Equation (1) and paragraph following shows input value X having an sign, interpolation for non-linear function is computed throughout the process, hence output value should also have a sign, the sign being positive since a logarithm is being computed).
Allowable Subject Matter
Claims 1-3 and 18-20 are allowed.
Applicant claims a device and method wherein the device as in claim 1 comprises:
A memory configured to store a first lookup table of entries each comprising a starting index value and a number of samples corresponding to a respective segment of a function and a second lookup table of entries each comprising a respective sampled mantissa from the function;
an interpolation logic circuit configured to:
retrieve from the first lookup table a starting index value and a number of samples corresponding to a segment of the function corresponding to an input mantissa from an input floating-point element;
retrieve from the second lookup table a first sampled mantissa and a second sampled mantissa based on the starting index value and the number of samples retrieved from the first lookup table and the input mantissa; and
interpolate an output mantissa based on the first sampled mantissa, the second sampled mantissa, and the input mantissa;
an arithmetic logic circuit configured to perform an operation on an input exponent from the input floating-point element based on the function to generate an output exponent,
a sign logic circuit configured to perform an operation on an input sign from the input floating-point element based on the function to generate an output sign; and
a packing circuit configured to generate an output floating-point element comprising the output sign, the output exponent, and the output mantissa.
The specific reason for indication of allowable subject matter is the inclusion of a second look up table with sampled mantissas and retrieving from the second lookup table a first sampled mantissa and a second sampled mantissa based on the starting index and the number of samples retrieved from the first lookup table. Kadkol et al. (11106430) included in the IDS filed 04/25/2024 (hereinafter “Kadkol”) discloses a circuit and method for calculating a non-linear function of floating point numbers using look up tables for interpolation. Kadkol is silent as to the inclusion of a second look up table with sampled mantissas and retrieving from the second lookup table a first sampled mantissa and a second sampled mantissa based on the starting index and the number of samples retrieved from the first lookup table.
Claims 2-3 dependent on claim 1 are therefore also allowable.
Claims 4-9 are objected to as previously set forth in Claim Objections, but would be allowable if rewritten to overcome the claim objections.
Claims 11-12 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant claims a device for interpolation wherein the device as in claim 10 comprises:
A function unit;
a controller configured to load a plurality of lookup table entries into the function unit and to configure the function unit for a non-linear function;
an input stage configured to receive an input floating-point element and provide the input floating-point element to the function unit; and
an output stage configured to receive an output floating-point element from the function unit and buffer the output floating-point element for transfer out of the device,
wherein the function unit is configured to:
interpolate an output mantissa based on the input mantissa of the input floating-point element and first and second sampled mantissas sampled from the non-linear function and retrieved from the lookup table entries;
generate an output exponent based on an input exponent of the input floating-point element and the non-linear function;
generate an output sign based on an input sign of the input floating-point element the non-linear function; and
generate the output floating-point element comprising the output sign, the output exponent, and the output mantissa.
Wherein claim 11 is dependent on claim 10 further comprising:
wherein the plurality of lookup table entries comprises a first lookup table and a second lookup table, and
wherein the function unit is further configured to:
retrieve from the first lookup table a starting index value and a number of samples corresponding to a segment of the non-linear function corresponding to the input mantissa; and
retrieve from the second lookup table the first sampled mantissa and the second sampled mantissa based on the starting index value and the number of samples retrieved from the first lookup table and the input mantissa.
The specific reason for indication of allowable subject matter is the inclusion a second lookup table and retrieval of a first and second sampled mantissa from the second lookup table based on the starting index value and the number of samples retrieved from the first lookup table. Paul discloses the claimed invention according to the claim mappings above. Paul does not explicitly disclose a second lookup table from which a first and second sampled mantissa are retrieved for interpolation.
Claims 12 and 15-17 dependent on claim 1 are therefore also allowable.
Claims 13-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and rewritten in independent form to include all of the limitations of the base claim and any intervening claims.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xi et al. (US 2023/0161554 A1) (hereinafter "Xi") teaches a field programmable array for implementing a reciprocal function data path having a mantissa computation stage, an exponent computation stage, and a sign computation stage, the mantissa computation stage utilizing a look-up table for determining a slope value.
Mangnall et al. (US 2022/0229871 A1) (hereinafter "Mangnall") teaches a function approximation system for determining output floating point values using a plurality of look up tables for the various kinds of functions as well as a correction table.
Hickmann et al. (US 2019/0384575 A1) (hereinafter "Hickmann") teaches a method for storing a plurality of entries, and using this plurality of entries to determine an interpolation value for a power series approximation.
Conclusion
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151