Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Objection
Claim 1 is objected as it recites “some predetermined bits of the encrypted counter value” in the last line. As recited the word “some” is ambiguous, and the disclosure also does not clarify this ambiguity. Examiner assumes for the examination purpose it to be of full counter value.
Claim 13 is also objected to for the similar reasons as mentioned above for claim 1.
Response to Amendments and Arguments
Applicant amended independent claims 1 & 13. Examiner reviewed these amendments and found that these amendments have overcome 112 (a) rejections issued for claims 1 & 13. Hence rejections 112(a) issued for claims 1-20 in the previous office action have been withdrawn. The Applicant also argued in the remarks dated 06/17/2026 that cited True alone does not teach “transmitting a message comprising selected unencrypted lowest-order counter bits and predetermined bits of that encrypted counter value” as recited in the amended claim 1. Examiner considered these arguments but found them to be moot as Examiner has introduced new art.
Additionally, Examiner respectfully disagree with the statement that True does not teach encrypted counter value as True in fact teaches encrypting of counter value (bits in digital world) as well as encrypting of command and authentication values (bits) as illustrated below in this instant office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 & 13 are rejected under 35 USC 103 as being unpatentable over True (US 20100208894 A1 as mentioned in IDS dated 08/01/2022) in view of Gadarowski (US7120161B1)
Regarding claim 1, True teaches:
a device, comprising: a transmitter; a counter configured to provide a counter value indicated by a plurality of bits; a memory configured to store an operation key; [[0045] In an embodiment, a system for an encoder and decoder wireless transmission system is provided comprising an encoder and decoder, the encoder comprising, checker means adapted to check the logic state of encoder input lines and assembling these states into a command byte, storage means adapted to store the command byte, an authentication value, and a counter value, combiner means adapted for combining the command byte, the authentication value, and counter value into an n-bit data block, ] [0045] In an embodiment, a system for an encoder and decoder wireless transmission system is provided comprising an encoder and decoder, the encoder comprising, checker means adapted to check the logic state of encoder input lines and assembling these states into a command byte, storage means adapted to store the command byte, an authentication value, and a counter value, combiner means adapted for combining the command byte, the authentication value, and counter value into an n-bit data block, encryption means adapted to encrypt the n-bit data block forming an encrypted data block, transmitter means adapted to transmit the encrypted data block as a packet to the decoder, decrementer means adapted for decrementing the counter and encrypting the data block upon each packet transmission, the decoder comprising, storage means adapted to store a key and the counter value, receiver means adapted to receive the encrypted data block as a packet from the encoder, reader means adapted to read the key and the counter value, and decryption means adapted to decrypt the data block using the key and the block cipher to recover the command byte, setter means adapted to set the decoder output lines to the state corresponding to the command byte.
a processor coupled to the transmitter and memory, wherein the processor is configured to cause the device to perform operations that comprise: encrypt the counter value with the operation key to produce an encrypted counter value; [0046] In another embodiment, the system further comprises wherein the combiner means adapted to combine the command byte, authentication value, and counter value into a data block and the encryption means adapted to encrypt the data block comprises, combiner means adapted for combining the command byte, the authentication value, and counter value into an n-bit data block, divider means adapted for dividing the n-bit data block into two m-bit half-blocks plaintext A and plaintext B, respectively, encryption means adapted for encrypting each of the plaintext A and plaintext B generating ciphertext A'' and ciphertext B'', adder means adapted for adding a user identification value and a preamble value to each of the ciphertext A'' and ciphertext B'' generating packet A and packet B, respectively, transmitter means adapted to transmit packet A and packet B as a message to the decoder, and wherein the receiver means adapted for receiving the packet from the encoder, ]
transmit, via the transmitter, a message comprising some (could be all bits or full value) predetermined bits of the encrypted counter value. [0046] In another embodiment, the system further comprises wherein the combiner means adapted to combine the command byte, authentication value, and counter value into a data block and the encryption means adapted to encrypt the data block comprises, combiner means adapted for combining the command byte, the authentication value, and counter value into an n-bit data block, divider means adapted for dividing the n-bit data block into two m-bit half-blocks plaintext A and plaintext B, respectively, encryption means adapted for encrypting each of the plaintext A and plaintext B generating ciphertext A'' and ciphertext B'', adder means adapted for adding a user identification value and a preamble value to each of the ciphertext A'' and ciphertext B'' generating packet A and packet B, respectively, transmitter means adapted to transmit packet A and packet B as a message to the decoder, and wherein the receiver means adapted for receiving the packet from the encoder, reader means adapted for reading the key and the counter value, and decryption means adapted for decrypting the encoder data block using the key and recovering the command byte comprises, receiver means adapted for receiving the message including packet A and packet B from the encoder, remover means adapted for removing the preamble and identification value from each of packet A and packet B recovering ciphertext A'' and ciphertext B'', respectively, reader means adapted for reading the key and the counter value,]
Although, True teaches encrypted counter value and transmission of message incorporating encrypted counter value, he does not teach explicitly, however, Gadarowski teaches:
select a subset of the plurality of bits of the counter value, the subset comprising lowest-order bits of the value; [Col 13, lines 35-45: If the number of bits comprised in the external logic section status word is greater than unity, the processing section 262 in controller 24 may command the logic 500 in section 300 in adapter 26 to transmit serially the next lowest order bit (i.e., next to the LSB-selected lowest order bits) of the external logic section status word via the line 606, by executing the following operations
transmit, via the transmitter, the selected subset of the plurality of bits of value. [Col 13, lines 35-45: If the number of bits comprised in the external logic section status word is greater than unity, the processing section 262 in controller 24 may command the logic 500 in section 300 in adapter 26 to transmit serially the next lowest order bit (i.e., next to the LSB) of the external logic section status word via the line 606, by executing the following operations. It is obvious to an ordinary skilled person is that the combination of teachings of True and Gadarowski discloses “transmit, via the transmitter, a message comprising the selected subset of the plurality of bits of the counter value and some predetermined bits of the encrypted counter value”.
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True with the disclosure of Gadarowski. The motivation or suggestion would have been to implement improved system and method to increase the ability of respective host controllers to control and monitor different types of network adapters, and decrease the amount of design effort required to ensure host controller-network adapter compatibility, by providing in the different types of network adapters respective "standardized" control interfaces (abstract, Col 1 & 2, lines 15-65 & 01-35 respectively, Gadarowski)
Regarding claim 13, this claim is interpreted to be same as claim 13 and rejected for the same reasons as set forth for claim 1.
Claims 2-3 & 14 are rejected under 35 USC 103 as being unpatentable over True in view of Gadarowski and Kune (US20090292913)
Regarding claims 2 & 14, although, True and Gadarowski teach counter value, they does not explicitly teach, however, Kune teaches wherein the counter is a 128-bit counter and the plurality of bits includes 128 bits. [0040] As shown in FIG. 2, the controller 202 includes a counter 214. The counter 214 represents any suitable hardware, software, firmware, or combination thereof that increments or decrements a value. As a particular example, the counter 214 could represent a 128-bit counter. The value of the counter 214 can be used for various purposes, such as to support counter-based communications. As a particular example, the controller 202 could use the counter value to perform various encryption, decryption, or authentication functions. As another particular example, the controller 202 could include a subset of the bits from the counter value in messages transmitted by the wireless node 200. Additional details regarding these functions are provided below.
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True and Gadarowski with the disclosure of Kune. The motivation or suggestion would have been to implement improved system and method a for counter-based communications in wireless sensor networks and other networks. (abstract, para 0002-0012, Kune)
Regarding claim 3, although True and Gadarowski teach counter value they do not explicitly teach, however, Kune teaches wherein the operations further comprise after transmission of the message, increment the counter by one. [0032] In one aspect of operation, various nodes in a wireless network may engage in counter-based communications. Counter-based communications refer to communications that involve the use of a counter, such as when at least part of a counter value is included in a transmitted or received message or when a counter value is used to encrypt, decrypt, or authenticate a message. As a particular example, the leaf nodes and infrastructure nodes in FIG. 1 could support the EAX mode of encryption defined in the Advanced Encryption Standard (AES) from the National Institute of Standards and Technology (NIST). This standard defines a 128-bit counter that is incremented each time a message is transmitted. In some systems, the entire 128-bit counter value is included in each message that is transmitted by a wireless node. However, this can lead to wasted bandwidth and significant overhead, particularly when the transmitted messages are relatively small.]
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True and Gadarowski with the disclosure of Kune. The motivation or suggestion would have been to implement improved system and method a for counter-based communications in wireless sensor networks and other networks. (abstract, para 0002-0012, Kune)
Claims 4-5 & 15-16 are rejected under 35 USC 103 as being unpatentable over True in view of Gadarowski, and Timpe (US20070260777)
Regarding claims 4 & 15, although, True and Gadarowski teach counter value, they do not teach, however, Timpe teaches wherein the subset of the plurality of bits of the counter value is a predetermined number of lowest-order bits of the counter value. [0027] Furthermore, under certain circumstances, it is possible to store the total event counter 18 and the write pointer 20 in the same register to define a counter/write pointer 18a. According to one embodiment of the present invention, the starting address of the queue 12, which can be conceptualized as either a literal address or an offset to another memory address, is selected to be (0) and the size of the address space (number of addressable locations), denoted m, is selected to satisfy the equation: size m=2.sup.n where n is a positive integer. For example, if n is equal to 8, then the size of the address space m=256. Because the address space starts at address (0), the queue address range is 0-255, and can be tracked using the lowest order n bits (8 bits in this illustration) of the total event counter 18. The total event counter 18 is thus selected to be able to hold a count significantly higher than m (256 in this illustration). For example, by allowing the count value stored in the total event counter 18 to be represented as a thirty two bit word, approximately 4.3 billion writes to the queue 12 can occur before the total event counter 18 overflows. Note that as the counter is incremented, the lowest order 8 bits circularly count through a cycle of 0-255. On the 256.sup.th write to the total event counter 18, the lowest order 8 bits of the count roll back to zero. Where the write pointer 20 is encoded into the lowest order n bits of the total event counter 18, the system 10 does not need to maintain a separate physical register for the write pointer 20. Under this arrangement, the queue logic 14 writes to the total event counter 18 to update a count stored therein, and the queue logic 14 reads (at least the lowest order n bits) from the total event counter 18 to determine the next write position in the queue 12.]
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True and Gadarowski with the disclosure of Timpe. The motivation or suggestion would have been to implement improved system and method a for utilizing counter and tracking changing counter value in wireless communications environment. (abstract, para 0001-0008, Timpe)
Regarding claim 5 & 16, although, True and Gadarowski teach counter value, they do not teach, however, Timpe teaches wherein the predetermined number of lowest-order bits of the counter value is 8 bits. [0027] Furthermore, under certain circumstances, it is possible to store the total event counter 18 and the write pointer 20 in the same register to define a counter/write pointer 18a. According to one embodiment of the present invention, the starting address of the queue 12, which can be conceptualized as either a literal address or an offset to another memory address, is selected to be (0) and the size of the address space (number of addressable locations), denoted m, is selected to satisfy the equation: size m=2.sup.n where n is a positive integer. For example, if n is equal to 8, then the size of the address space m=256. Because the address space starts at address (0), the queue address range is 0-255, and can be tracked using the lowest order n bits (8 bits in this illustration) of the total event counter 18. The total event counter 18 is thus selected to be able to hold a count significantly higher than m (256 in this illustration). For example, by allowing the count value stored in the total event counter 18 to be represented as a thirty-two-bit word, approximately 4.3 billion writes to the queue 12 can occur before the total event counter 18 overflows. Note that as the counter is incremented, the lowest order 8 bits circularly count through a cycle of 0-255. On the 256.sup.th write to the total event counter 18, the lowest order 8 bits of the count roll back to zero. Where the write pointer 20 is encoded into the lowest order n bits of the total event counter 18, the system 10 does not need to maintain a separate physical register for the write pointer 20. Under this arrangement, the queue logic 14 writes to the total event counter 18 to update a count stored therein, and the queue logic 14 reads (at least the lowest order n bits) from the total event counter 18 to determine the next write position in the queue 12.]
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True and Gadarowski with the disclosure of Timpe. The motivation or suggestion would have been to implement improved system and method a for utilizing counter and tracking changing counter value in wireless communications environment. (abstract, para 0001-0008, Timpe)
Claims 6-10, & 17-20 are rejected under 35 USC 103 as being unpatentable over True in view of Gadarowski and Nowottnick (US20080270793)
Regarding claims 6 & 17, although True and Gadarowski teach encrypting counter value, they do not explicitly teach, however, Nowottnick teaches wherein the operations further comprise encrypt the counter value by a symmetric encryption type with the operation key. [0053] In this context, a block cipher is a type of symmetric-key encryption algorithm transforming a fixed-length block of plaintext (=unencrypted text) data into a block of ciphertext (=encrypted text) data of the same length. This transformation takes place under the action of a user-provided secret key. Decryption is performed by applying the reverse transformation to the ciphertext block using the same secret key (SK). The fixed length is called the block size, and for many block ciphers, the block size is 64 bits or--with processors becoming more sophisticated--128 bits. [0054] A stream cipher is a type of symmetric encryption algorithm generating a so-called keystream, i.e. a sequence of bits used as a key. Encryption is then accomplished by combining the keystream with the plaintext, usually with the bitwise XOR operation. The generation of the keystream can be independent of the plaintext and ciphertext, yielding what is termed a synchronous stream cipher, or it can depend on the data and its encryption, in which case the stream cipher is said to be self-synchronizing. Most stream cipher designs are for synchronous stream ciphers.]
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True and Gadarowski with the disclosure of Nowottnick. The motivation or suggestion would have been to implement improved system and method for secured and fast control of locking an unlocking of a vehicle or remote device. (abstract, para 0001-0012, Nowottnick)
Regarding claim 7 & 18, although True and Gadarowski teach encryption, they do not teach explicitly, however, Nowottnick teaches wherein the symmetric encryption type is based on the Advanced Encryption Standard (AES). [0059] Moreover, said EEPROM module 52 is designed for providing a first cipher unit 32 of the remote device 20 with a secret key SK on 128-bit basis wherein the first cipher unit 32 is operated on electronic codebook mode (so-called ECB mode), which is a special AES mode.[0060] Furthermore, the EEPROM module 52 is designed for providing a second cipher unit 36 of the remote device 20 with a secret key SK on 128-bit basis wherein the second cipher unit 36 is operated on output feedback mode (so-called OFB mode), which again is a special AES mode.]
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True and Gadarowski with the disclosure of Nowottnick. The motivation or suggestion would have been to implement improved system and method for secured and fast control of locking an unlocking of a vehicle or remote device. (abstract, para 0001-0012, Nowottnick)
Regarding claims 8 & 19, although True and Gadarowski teach encryption, they do not teach explicitly, however, Nowottnick teaches wherein the symmetric encryption type is based on AES-128 encryption. [0066] Moreover, the base station 10 comprises a first memory module 50, namely an EEPROM, for providing a first cipher unit 30 and a second cipher unit 34 with a secret key SK (symmetric key) on 128-bit basis wherein both cipher units 30, 34 are arranged at the base station 10.[0067] The first cipher unit 30 is operated by AES128 based on ECB mode and designed for providing the remote device 20 with a message authenticator MAC on 16-bit basis. The second cipher unit 34 of the base station 10 is operated by AES128 based on OFB mode.]
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True and Gadarowski with the disclosure of Nowottnick. The motivation or suggestion would have been to implement improved system and method for secured and fast control of locking an unlocking of a vehicle or remote device. (abstract, para 0001-0012, Nowottnick)
Regarding claim 9, True teaches wherein the message is associated with a command. [0045] In an embodiment, a system for an encoder and decoder wireless transmission system is provided comprising an encoder and decoder, the encoder comprising, checker means adapted to check the logic state of encoder input lines and assembling these states into a command byte, storage means adapted to store the command byte, an authentication value, and a counter value, combiner means adapted for combining the command byte, the authentication value, and counter value into an n-bit data block, encryption means adapted to encrypt the n-bit data block forming an encrypted data block, transmitter means adapted to transmit the encrypted data block as a packet to the decoder, decrementer means adapted for decrementing the counter and encrypting the data block upon each packet transmission, the decoder comprising, storage means adapted to store a key and the counter value, receiver means adapted to receive the encrypted data block as a packet from the encoder, reader means adapted to read the key and the counter value, and decryption means adapted to decrypt the data block using the key and the block cipher to recover the command byte, setter means adapted to set the decoder output lines to the state corresponding to the command byte.
Regarding claims 10 & 20, although True and Gadarowski teach message command, they do not teach explicitly, however, Nowottnick teaches wherein the command is a request to lock or unlock a vehicle. [0050] As shown in FIG. 1, an embodiment being implemented by means of the present invention as an electronic communication system 100 comprises, amongst other things, a remote device 20 in form of a data carrier which in turn is part of an immobilizer, in particular of a system for opening and closing the door locks of a motor vehicle. Said electronic communication system 100 is an authentication control system, further comprising a base station 10 being arranged in the motor vehicle (on the left side of FIG. 1).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True and Gadarowski with the disclosure of Nowottnick. The motivation or suggestion would have been to implement improved system and method for secured and fast control of locking an unlocking of a vehicle or remote device. (abstract, para 0001-0012, Nowottnick)
Claim 11 is rejected under 35 USC 103 as being unpatentable over True, in view of Gadarowski, Nowottnick and Flanagan (US20070036296)
Regarding claim 11, although True, Gadarowski and Nowottnick teach command, they do not teach clearly, however, Flanagan teaches, wherein the message further includes a data field that identifies the command. [0023] FIG. 5 illustrates an exemplary message 100 for transmitting encrypted phone numbers in accordance with an aspect of the present invention. The exemplary message 100 can be in the form of a packet, such as a VoIP packet, a Bluetooth, or IEEE 802.11 packet, a text message, or attached as part of a voice message. The exemplary message 100 includes a header portion 102, a command portion 104 (data field identifying the command), a party name 106, an encrypted phone number 108 and optionally a password protected key portion 110. The header portion 102 can include information associated with the type of message and the attached fields in the message. The command portion 104 can be a command, such as a command for adding the party name and encrypted phone number to an electronic phone list of a recipient. The command can be an add timer command in which a specified time period is attached, such that the party name and encrypted phone number expires at the end of the time period and is removed from the recipient's phone list and TCU at the end of the time period. The command can be a removal request command in which the party name and encrypted phone number is revoked and is removed from the recipient's phone list and TCU at receipt of the removal request command.]
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to combine the teachings of True, Gadarowski, and Nowottnick with the disclosure of Flanagan. The motivation or suggestion would have been to implement improved system and method for protecting sensitive data from unauthorized access of users or devices. (abstract, para 0001-0006, Flanagan)
Allowable Subject Matter
Claim 12 is objected to but would be allowable if its limitations are fully incorporated into the base claims including incorporating limitations of all the intervening claims and provided the Applicants rewrites the base claims to overcome the 112a rejection issued for these claims in this instant office action without broadening the scope of these claims.
Reasons of allowability will be provided whenever the Applicant further amends the claims and the case reaches the condition of allowability.
Conclusion
The prior art made of record and listed on the PTO-892 and not relied upon are considered pertinent to applicant’s disclosure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHER A KHAN whose telephone number is (571)272-8574. The examiner can normally be reached M-F 8:00 am-500pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eleni A Shiferaw can be reached at 571-272-3867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHER A KHAN/Primary Examiner, Art Unit 2497
Prosecution Insights