DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 08/01/2022. Claims 1-20 are currently pending, of which claims 1, 4, and 6 are currently rejected, and claims 2-3, 5, 7-10, and 15 are objected. Claims 11-14 and 16-20 are allowed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “determine a number of leading sign bits of an input datum in a fixed-point format” feature recited in claim 1, and the “shifting the input datum by the exponent of the input datum to produce a significand” feature recited in claim 11 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 15 is objected to because of the following informalities: Claim is missing a period at the end. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 6 is rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Wegener (U.S. Patent Application Publication No.: US 20130262539 A1), hereinafter “Wegener”.
Regarding Claim 6, Wegener teaches:
A data processing apparatus configured to:
determine an output shared exponent as a maximum of input exponents of a plurality of input data (¶0096, e.g., Exponent calculator 402 determines maximum exponent n_exp corresponding to samples; Fig. 11, e.g., n_exp is encoded and outputted as exp token 411 (output shared exponent)),
the input data representable by the plurality of input exponents and a corresponding plurality of input significands (¶0058, e.g., samples are floating-point numbers (includes exponents and significands));
determine output exponent differences between the output shared exponent and the plurality of input exponents (¶0086-0094, e.g., exponent differences are determined using n_exp(i) (output shared exponent) and n_exp(i-1) from previous samples);
encode the output exponent differences and the corresponding input significands to produce a plurality of output data (Fig. 11, e.g., shows Block Floating Point Encoder 400; ¶0096, e.g., Mantissas are encoded in Mantissa Packer 406; ¶0097, e.g., two or more exponent differences are jointly encoded),
an output datum of the plurality of output data including an encoding tag and a payload (¶0096, e.g., compressed group 410 includes four packed mantissas (payload) with appended sign bits (encoding tag)); and
store the plurality of output data and the output shared exponent (Fig. 11, e.g., Compressed group 410 stores exp token (output shared exponent) and mantissas (output data)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Sudharsanan et al. (U.S. Patent No.: US 6671796 B1), hereinafter “Sudharsanan”, further in view of Tang (U.S. Patent Application Publication No.: US 20190042243 A1), hereinafter “Tang”.
Regarding Claim 1, Sudharsanan teaches:
A data processing apparatus configured to:
determine a number of leading sign bits of an input datum in a fixed-point format (Fig. 5, e.g., shows circuit 510 for counting the number of leading zeros (leading sign bits); Column 6 Lines 44 - 53, e.g., RS1 in Fig. 5 stores Fixed point value (input datum in a fixed-point format). Circuit 510 Counts the number of leading zeros);
shift the input datum based on the number of leading sign bits to provide a significand (Fig. 5, e.g., shows output of Circuit 510 (leading sign bits) going into adder 530, then to left shifter 550, and output of left shifter 550 is stored as the mantissa of the floating point value; Column 6 Lines 50-65, e.g., Number of leading zeros (leading sign bits) is used to control the shift of the fixed point value through a control port);
determine an output exponent associated with an output datum based on the number of leading sign bits (Fig. 5, e.g., shows output of Circuit 510 (leading sign bits) going into adder 520, then to adder 540, and output of adder 540 is stored as the exponent of the floating point value);
Sudharsanan does not teach:
encode the significand to produce a payload and an encoding tag of the output datum; and
store the output exponent and the output datum.
However, Tang teaches:
encode the significand to produce a payload and an encoding tag of the output datum (¶0029, e.g., Floating point values are encoded; ¶0034; Figs. 1(A) and 1(B), e.g., shows EFP encoding format, which includes self-identifying field (encoding tag) and mantissa (payload)); and
store the output exponent and the output datum (¶0056, e.g., Operand in EFP format is stored).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the encoding of a floating point value to Elastic Floating-Point format as taught by Tang with the resulting floating point value converted from fixed point as taught by Sudharsanan. One would have been motivated to combine these references because both references disclose fixed-point/floating-point conversion, and Tang enhances the model of Sudharsanan because "Consequently, for a same data width, an EFP number can cover a larger numerical range of real numbers than a corresponding IEEE floating-point number." (Tang: ¶0030)
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sudharsanan in view of Tang, further in view of Wegener.
Regarding Claim 4, Sudharsanan in view of Tang teach:
The data processing apparatus of claim 1, where the input datum has a … fixed-point format (Sudharsanan: Column 6 Lines 44 - 53, e.g., RS1 in Fig. 5 stores Fixed point value), and where the data processing apparatus is further configured to:
determine a sign and an absolute value of the input datum (Fig. 5, e.g., Sign is received and outputted in the final result, and Absolute value circuit 507 receives value fx and generates an absolute value for fx; Column 6 Lines 44-50); and
set a sign bit of the output datum based on the sign of the input datum (Fig. 5, e.g., Sign is received and outputted in the final result).
Sudharsanan in view of Tang do not teach:
The data processing apparatus of claim 1, where the input datum has a two's complement, fixed-point format, …
However, Wegener teaches converting floating point values to Block floating-point, and teaches converting the floating-point input value into integer format, which can be fixed-point numbers. Wegener explains “The float to integer format converter 302 converts the floating-point numbers to corresponding integer numbers, or fixed-point numbers, having Nbits bits per sample” (Wegener: ¶0058). Wegener further explains how that integer number is represented in a binary Two’s complement format. See Wegener: ¶0068. Additionally, Sudharsanan uses a fixed point value that is represented by a sign bit. See Sudharsanan Fig. 5 and Column 7 Lines 1-4.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the fixed point value being represented in two’s complement as taught by Wegener with the fixed point value as taught by Sudharsanan in view of Tang. One would have been motivated to combine these references because both references disclose fixed-point/floating-point conversion, and Wegener enhances the model of Sudharsanan in view of Tang by allowing compatibility with fixed-point values using the standard two’s complement number representation.
Allowable Subject Matter
Claims 2-3, 5, 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-14 and 16-20 are allowed. Claim 15 would be allowed if rewritten to overcome the objection stated above. The following is a statement of reasons for the indication of allowable subject matter:
US 20210042087 A1 (Pugh et al.), hereinafter “Pugh” – teaches a reduced-delay circuit for converting a fixed point value into a block floating point value. The reduced-delay circuit 1900 includes multiplexers 1905 and 1945; OR gates 1910 and 1950; adders 1915 and 1925; a leading zero detector (LZD) 1920; subtractors 1930 and 1935; a shifter 1940; and a rounder 1955. Reduced-delay circuit 1900 receives a result of a multiplication of two floating point numbers, where the mantissa portion is left shifted by Z’ bits from the leading zero detector 1940. Rounder 1955 rounds the result of the shifter to produce a mantissa, and outputs an overflow signal to be used for the exponent selection. Exponent is selected in multiplexer 1945 based on the MSB and the overflow signal. See Fig. 19 and ¶0096-0105. Pugh does not teach or suggest shifting the input datum by the exponent of the input datum to produce a significand, and encoding the significand to produce a payload of the output datum and an encoding tag of the output datum. Instead, Pugh teaches shifting addition result from the adder 1915 is shifted left Z′ bits outputted from the leading zero detector, and outputting a sign bit, exponent portion, and mantissa portion of the fixed point to block floating point conversion without any encoding. Pugh, therefore, does not teach or suggest a combination as claimed in claim 11 including the limitations “shifting the input datum by the exponent of the input datum to produce a significand” and “encoding the significand to produce a payload of the output datum and an encoding tag of the output datum”.
US 6671796 B1 (Sudharsanan et al.), hereinafter “Sudharsanan” – teaches converting a fixed point value to floating point using circuitry within media functional units. Instructions to convert the fixed point value to floating point includes generating an absolute value of the fixed point input, left shifting the result by the number of leading zeros plus 1 to produce the mantissa portion of the floating point number, subtracting the 31 minus the number of leading zeros to determine an exponent, and outputting the same sign as the fixed point value for the floating point value. See Fig. 5 Column 6 Line 44 – Column 7 Line 4. Sudharsanan does not teach or suggest rounding the significand to a designated number of bits to produce a rounded significand and a carry bit, and encoding the significand to produce a payload of the output datum and an encoding tag of the output datum. Instead, Sudharsanan teaches outputting a floating point number using the standard format (sing, exponent, mantissa) without encoding, and there is no indication of rounding and outputting a carry bit used for the fixed point to floating point format conversion. Sudharsanan, therefore, does not teach or suggest a combination as claimed in claim 11 including the limitations “rounding the significand to a designated number of bits to produce a rounded significand and a carry bit; determining an exponent associated with an output datum based on the exponent of an input datum and the carry bit; encoding the significand to produce a payload of the output datum and an encoding tag of the output datum”.
US 20190042243 A1 (Tang), hereinafter “Tang” – teaches encoding a floating point number to be represented in an elastic floating point encoding format (EFP). This EFP format includes a sign bit, a self-identifying field, one or more bits to represent an exponent range, and one or more bits to indicate a mantissa. The self-identifying field represents the exponent range represented by the number. See Figs. 1(A) and 1(B), and ¶0034-0043. Tang does not teach or suggest shifting the input datum by the exponent of the input datum to produce a significand, rounding the significand to a designated number of bits to produce a rounded significand and a carry bit, and determining an exponent associated with an output datum based on the exponent of an input datum and the carry bit. Instead, Tang teaches encoding a floating point value into the EFP format to represent a wider range using the same amount of data as a regular floating point, however there is no disclosure regarding the shifting data by an exponent, or rounding and producing a carry bit. Tang, therefore, does not teach or suggest a combination as claimed in claim 11 including the limitations “shifting the input datum by the exponent of the input datum to produce a significand; rounding the significand to a designated number of bits to produce a rounded significand and a carry bit; determining an exponent associated with an output datum based on the exponent of an input datum and the carry bit”.
US 20130262539 A1 (Wegener), hereinafter “Wegener” – teaches floating point inputs to fixed point, then to Block Floating Point (BFP). Wegener teaches using a BFP encoder to encode the mantissa and exponent of input data and output data to form a compressed group. This data includes one exponent toke, three mantissas, and three appended sign bits (one for each mantissa). Wegener does not teach or suggest rounding the significand to a designated number of bits to produce a rounded significand and a carry bit, and determining an exponent associated with an output datum based on the exponent of an input datum and the carry bit. Instead, Wegener teaches rounding each scaled floating-point number to provide the output integer number, however there is no carry bit generated from the rounding. Wegener, therefore, does not teach or suggest a combination as claimed in claim 11 including the limitations “rounding the significand to a designated number of bits to produce a rounded significand and a carry bit; determining an exponent associated with an output datum based on the exponent of an input datum and the carry bit”.
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182