DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 2, 12) in the reply filed on 10/6/25 is acknowledged.
Claim 3, 13 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/6/25.
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 3/2/2023, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “number of semiconductor diodes is fewer than the total number of channels” (claims 8, 18) (FIG. 3 shows N of each) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 2, 11-12 objected to because of the following informalities:
Claims 2, 12 line 4 “and is provided from” should read “and the electrical current is provided from”.
Claim 11 final line “a reverse voltage” should read “the reverse voltage”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 8, 18 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 8, 18 describe the number of semiconductor diodes is fewer than the total number of channels in all multichannel electrical components combined. Specification does not appear to even mention this limitation, let alone discuss or show it in sufficient detail to satisfy the written description requirement. FIG. 3 shows N semiconductor diodes and N channels.
Claim 8, 18 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Specification does not enable number of semiconductor diodes fewer than total number of channels in multichannel electrical components.
Wands factors, MPEP 2164.01(a)
The claims are broad
Invention pertains to circuit with pulsed emitter(s) driven by semiconductor diode(s)
Prior art generally recognizes semiconductor diodes being equal to number of channels, with some exceptions where semiconductor diodes < channels
D, E. Levels of ordinary skill and predictability in the art are insufficient for enablement
F, G. Applicant provides very little direction and no working example for the invention described in claim 8, 18
H. As a result, level of experimentation would be high
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 9-12, 14, 19-20 is/are rejected under 35 U.S.C. 102a1/2 as being anticipated by Blazo US-4995044-A.
Regarding claim 1, Blazo discloses a method for providing a short electrical pulse using a switching circuit (fig. 1, Abstract), the method comprising: providing a forward current to at least one semiconductor diode electrically connected with and controlling electrical current to an electrical component within a circuit (annotated fig. 1 E-/R1/Ground provides forward current to semiconductor diode SRD electrically connected with and controlling electrical current to electrical component (everything within EC/to the right of SRD), col. 2 lines 35-50); and switching the at least one semiconductor diode into a reverse bias by applying a reverse voltage to the at least one semiconductor diode (annotated fig. 1 reverse current I1/voltage from Q2 switches SRD into reverse bias, col. 2 lines 35-50 + 60-65), thereby causing the at least one semiconductor diode to enter a reverse recovery state and controlling a destination of the electrical current and generating the short electrical pulse to the destination for the duration of the reverse recovery state (annotated fig. 1 SRD enters reverse recovery state after application of reverse voltage/current, electrical pulse I2 sent to destination inductor L for duration of reverse recovery state, col. 2 lines 35-65, see also Lemmon US-3428857-A col. 3 lines 25-60 and “Physical principles” section of “Step Recovery Diode” Wikipedia article, both cited in PTO-892 as evidentiary support for operation of step recovery diode); the duration of the reverse recovery state being based upon a value of the forward current and a value of the reverse voltage (Lemmon col. 3 lines 35-50, based upon forward current and reverse current (and therefore, reverse voltage)).
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Annotated fig. 1
Regarding claim 2, Blazo discloses the method of claim 1, wherein the at least one semiconductor diode is electrically in-line with the electrical component (annotated fig. 1 SRD in-line with EC); wherein, during the reverse recovery state/”RRS”, the destination of the electrical current is the electrical component and is provided from the at least one semiconductor diode (annotated fig. 1 during RRS, destination of current I2 is EC and provided from SRD, Blazo col. 2 lines 40-45); and wherein the duration of the electrical current provided to the electrical component is equal to the duration of the reverse recovery state, thereby providing the short electrical pulse to the electrical component (annotated fig. 1 I2 duration equal to RRS duration, occurs until SRD charge is depleted, pulse I2 sent to the inductor L within EC, Blazo col. 2 lines 40-65, Lemmon col. 3 lines 45-50, Wikipedia article “Anode current does not cease but reverses its polarity (i.e. the direction of its flow) and stored charge Qs starts to flow out of the device at an almost constant rate IR. All the stored charge is thus removed in a certain amount of time: this time is the storage time tS”, see also NPL Electrical Technology “What is Step Recovery Diode – SRD? Construction, Working & Applications” sections Working and Characteristics).
Regarding claim 4, Blazo discloses the method of claim 1, wherein the forward current is provided while a transistor electrically connected to the electrical component is switched off (annotated fig. 1 forward current via E-/R1/Ground provided while transistor Q1 electrically + indirectly connected to EC + switched off, Q1 off while SRD forward biased, Q1 not on until impulse trigger, col. 2 lines 15-25); and wherein the reverse voltage is provided while the transistor is switched on (fig. 1 reverse voltage/current to SRD provided while Q1 switched on, causing charge on SRD to transfer to inductor L because of reverse voltage, col. 2 lines 40-45 + 60-65).
Regarding claim 9, Blazo discloses the method of claim 1, wherein the providing a forward current is performed by a dedicated current source (annotated fig. 1 E-/R1/Ground provides forward current to semiconductor diode SRD, col. 2 lines 35-50).
“Dedicated current source” is combination of E-/R1/Ground.
Regarding claim 10, Blazo discloses the method of claim 1, wherein the electrical component comprises a light emitting device (annotated fig. 1 EC comprises light emitting device LD, col. 2 lines 25-30).
Regarding claim 11, Blazo discloses a device for providing a short electrical pulse using a switching circuit (fig. 1, Abstract), the device comprising: an electrical component receiving an electrical current (annotated fig. 1 EC receives electrical current I2, col. 2 lines 35-65); and at least one semiconductor diode electrically connected with the electrical component (annotated fig. 1 SRD electrically connected with EC), wherein the at least one semiconductor diode controls electrical current to the electrical component and wherein control of the at least one semiconductor diode controls a duration of the electrical current (annotated fig. 1 SRD controls current to EC and duration via operation of SRD, duration and amount of forward current and reverse current applied to SRD controls duration and amount of current from SRD to EC, col. 2 lines 35-65, see Lemmon US-3428857-A col. 3 lines 25-60, and “Physical principles” section of “Step Recovery Diode” Wikipedia article, both cited in PTO-892 as evidentiary support for operation of step recovery diode); wherein the control of the at least one semiconductor diode comprises providing a forward current to at least one semiconductor diode electrically connected with and controlling electrical current to an electrical component within a circuit (annotated fig. 1 control of SRD comprises providing forward current via E-/R1/Ground to SRD, SRD electrically connected with and controlling electrical current to EC) and switching the at least one semiconductor diode into a reverse bias by applying a reverse voltage to the at least one semiconductor diode (annotated fig. 1 switch SRD into reverse bias by applying reverse voltage via current I1 from Q2 to SRD, col. 2 lines 35-50 + 60-65), thereby causing the at least one semiconductor diode to enter a reverse recovery state and controlling a destination of the electrical current and generating the short electrical pulse to the destination for the duration of the reverse recovery state (annotated fig. 1 SRD enters reverse recovery state after application of reverse voltage/current, electrical pulse I2 sent to destination inductor L for duration of reverse recovery state); the duration of the reverse recovery state being based upon a value of the forward current and a value of a reverse voltage applied during the reverse bias (Lemmon col. 3 lines 35-50, based upon forward current and reverse current (and therefore, reverse voltage).
Regarding claim 12, Blazo discloses the device of claim 11, wherein the at least one semiconductor diode is electrically in-line with the electrical component (annotated fig. 1 SRD in-line with EC); wherein, during the reverse recovery state/”RRS”, the destination of the electrical current is the electrical component and is provided from the at least one semiconductor diode (annotated fig. 1 during RRS, destination of current I2 is EC and provided from SRD, Blazo col. 2 lines 40-45); and wherein the duration of the electrical current provided to the electrical component is equal to the duration of the reverse recovery state, thereby providing the short electrical pulse to the electrical component (annotated fig. 1 I2 duration equal to RRS duration, occurs until SRD charge is depleted, pulse I2 sent to the inductor L within EC, Blazo col. 2 lines 40-65, Lemmon col. 3 lines 45-50, Wikipedia article “Anode current does not cease but reverses its polarity (i.e. the direction of its flow) and stored charge Qs starts to flow out of the device at an almost constant rate IR. All the stored charge is thus removed in a certain amount of time: this time is the storage time tS”, see also (evidentiary support for SRD principles/operation) NPL Electrical Technology “What is Step Recovery Diode – SRD? Construction, Working & Applications” sections Working and Characteristics).
Regarding claim 14, Blazo discloses the device of claim 11, further comprising a transistor electrically connected to the electrical component (annotated fig. 1 transistor Q1 electrically + indirectly connected to EC, col. 2 lines 15-25); wherein the forward current is provided while the transistor is switched off (Q1 off while SRD forward biased, Q1 not on until impulse trigger, col. 2 lines 15-25), and wherein the reverse voltage is provided while the transistor is switched on (fig. 1 reverse voltage/current to SRD provided while Q1 switched on, causing charge on SRD to transfer to inductor L because of reverse voltage, col. 2 lines 40-45 + 60-65).
Regarding claim 19, Blazo discloses the device of claim 11, wherein the providing a forward current is performed by a dedicated current source (annotated fig. 1 E-/R1/Ground provides forward current to semiconductor diode SRD, col. 2 lines 35-50).
“Dedicated current source” is combination of E-/R1/Ground.
Regarding claim 20, Blazo discloses the device of claim 11, wherein the electrical component comprises a light emitting device (annotated fig. 1 EC comprises light emitting device LD, col. 2 lines 25-30).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blazo in view of NPL Hewlett Packard "Pulse and Waveform Generation with Step Recovery Diodes"/”HP”.
Regarding claim 5, Blazo discloses the method of claim 1.
Blazo does not disclose further comprising controlling at least one of a pulse intensity, pulse width, and pulse duration by adjusting the value of the forward current.
Blazo discloses a desire to provide short optical pulses (e.g. less than 40 ps) (col. 1 lines 10-20).
HP discloses the storage time required to remove the charge stored on the SRD (i.e. pulse time) depends on the forward current (pg. 2, section 1. Ideal Dynamic Characteristics, formulas 2 + 3, and fig. 1).
It is well known to optimize values to achieve desired results (MPEP 2144.05 II A/B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to control at least one of a pulse intensity, pulse width, and pulse duration by adjusting the value of the forward current to decrease pulse width/duration to make device more suitable for photodiode risetime testing, high resolution time domain reflectometry and dispersion and bandwidth testing on optical fiber (Blazo col. 1 lines 10-20) or to increase pulse/width duration for other purposes.
Regarding claim 15, Blazo discloses the device of claim 11.
Blazo does not disclose wherein the control further comprises controlling at least one of a pulse intensity, pulse width, and pulse duration by adjusting the value of the forward current.
Blazo discloses a desire to provide short optical pulses (e.g. less than 40 ps) (col. 1 lines 10-20).
HP discloses the storage time required to remove the charge stored on the SRD (i.e. pulse time) depends on the forward current (pg. 2, section 1. Ideal Dynamic Characteristics, formulas 2 + 3, and fig. 1).
It is well known to optimize values to achieve desired results (MPEP 2144.05 II A/B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to control at least one of a pulse intensity, pulse width, and pulse duration by adjusting the value of the forward current to decrease pulse width/duration to make device more suitable for photodiode risetime testing, high resolution time domain reflectometry and dispersion and bandwidth testing on optical fiber (Blazo col. 1 lines 10-20) or to increase pulse/width duration for other purposes.
Claim(s) 6, 8, 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blazo in view of Boenigk US-20230417881-A.
Regarding claim 6, Blazo discloses the method of claim 1, wherein the semiconductor diode is connected in series to and controls the channel of the single channel electrical component (annotated fig. 1 SRD connected in series to and controls EC, col. 2 lines 35-65).
Blazo does not disclose wherein the at least one semiconductor diode comprises a plurality of semiconductor diodes; wherein the electrical component comprises a multichannel electrical component; and wherein each of the plurality of semiconductor diodes is connected in series to and controls at least one channel of the multichannel electrical component.
Boenigk discloses a light emitting device with a plurality of semiconductor diodes, each semiconductor diode used to drive an associated light emitting diode of a plurality of light emitting diodes within a multichannel electrical component (fig. 1A plurality of diodes within 106-X, each diode in a 106-X drives associated 102-X of plurality of 102-X within multichannel electrical component 102, 0026-0031, 0085).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a plurality of semiconductor diodes, wherein the electrical component comprises a multichannel electrical component; and wherein each of the plurality of semiconductor diodes is connected in series to and controls at least one channel of the multichannel electrical component to provide more complex pulse signals by overlapping/combining individual emitter pulses in the electrical component. Also allows for continued use in case one emitter fails.
Regarding claim 8, modified Blazo discloses the method of claim 6.
Modified Blazo does not disclose wherein the number of semiconductor diodes is fewer than the total number of channels in all multichannel electrical components combined.
Boenigk discloses a light emitting device with fewer semiconductor diodes than channels (fig. 1E light emitting device has fewer semiconductor diodes 106-X than channels (four), 0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have fewer semiconductor diodes than channels to simplify the circuit layout/design while still enabling control of multiple light emitters (Boenigk 0037).
Regarding claim 16, Blazo discloses the device of claim 11, wherein the semiconductor diode is connected in series to and controls the channel of the single channel electrical component (annotated fig. 1 SRD connected in series to and controls EC, col. 2 lines 35-65).
Blazo does not disclose wherein the at least one semiconductor diode comprises a plurality of semiconductor diodes; wherein the electrical component comprises a multichannel electrical component; and wherein each of the plurality of semiconductor diodes is connected in series to and controls at least one channel of the multichannel electrical component.
Boenigk discloses a light emitting device with a plurality of semiconductor diodes, each semiconductor diode used to drive an associated light emitting diode of a plurality of light emitting diodes within a multichannel electrical component (fig. 1A plurality of diodes within 106-X, each diode in a 106-X drives associated 102-X of plurality of 102-X within multichannel electrical component 102, 0026-0031, 0085).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a plurality of semiconductor diodes, wherein the electrical component comprises a multichannel electrical component; and wherein each of the plurality of semiconductor diodes is connected in series to and controls at least one channel of the multichannel electrical component to provide more complex pulse signals by overlapping/combining individual emitter pulses in the electrical component. Also allows for continued use in case one emitter fails.
Regarding claim 18, modified Blazo discloses the device of claim 16.
Modified Blazo does not disclose wherein the number of semiconductor diodes is fewer than the total number of channels in all multichannel electrical components combined.
Boenigk discloses a light emitting device with fewer semiconductor diodes than channels (fig. 1E light emitting device has fewer semiconductor diodes 106-X than channels (four), 0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have fewer semiconductor diodes than channels to simplify the circuit layout/design while still enabling control of multiple light emitters (Boenigk 0037).
Claim(s) 7, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blazo in view of Boenigk and Dolganov US-20220299610-A1.
Regarding claim 7, modified Blazo discloses the method of claim 6.
Modified Blazo does not disclose wherein the value of the forward current for each of the plurality of semiconductor diodes is set independently from other of the plurality of semiconductor diodes.
Dolganov discloses a driver circuit for an array of optical emitters with a separate/independent current source for each row of emitters and different peak currents for each column of emitters (fig. 1 separate current source 106 for each row of emitters 102, 0016-0017, different peak currents 0021, 0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to set the value of the forward current for each of the plurality of semiconductor diodes independently from other of the plurality of semiconductor diodes to achieve a desired peak power for an optical pulse from one or more of the emitters in Blazo (Dolganov 0041).
Regarding claim 17, modified Blazo discloses the device of claim 16.
Modified Blazo does not disclose wherein the value of the forward current for each of the plurality of semiconductor diodes is set independently from other of the plurality of semiconductor diodes.
Dolganov discloses a driver circuit for an array of optical emitters with a separate/independent current source for each row of emitters and different peak currents for each column of emitters (fig. 1 separate current source 106 for each row of emitters 102, 0016-0017, different peak currents 0021, 0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to set the value of the forward current for each of the plurality of semiconductor diodes independently from other of the plurality of semiconductor diodes to achieve a desired peak power for an optical pulse from one or more of the emitters in Blazo (Dolganov 0041).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Ehrlich whose telephone number is (703)756-5716. The examiner can normally be reached M-F 8-5.
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/A.E./Examiner, Art Unit 2828
/MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828