DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Drawing Objections
Applicant has amended the claims at issue and the previous objections have therefore been withdrawn.
Claim Objections
Applicant has amended the claims at issue and the previous objections have therefore been withdrawn.
35 USC 101 Rejections
Applicant's arguments filed 3/5/2026 have been fully considered but they are not persuasive.
Applicant asserts the combination including input and output registers, and decoder coupling, of claim 11 shows structural connections to form a custom multiplier for the data that addresses the technical problem in the practical application of performing multiply-accumulate operations in a neural network processor. Examiner respectfully disagrees. The input registers generally link the data to the application of neural network processing. Furthermore, the coupling of the decoder is merely a natural resulting structure for performing the mathematical process; in other words, the coupling of elements is a result of structure that merely applies the format and mathematical calculations and does not impose any meaningful limits on practicing the abstract idea. The Examiner also notes the preamble of claim 11 is not given patentable weight.
Applicant asserts claims 21-22 provide a technological improvement of increased accuracy for the same amount of storage, or reduced storage for similar accuracy, and is thus integrated in a practical application. Examiner respectfully disagrees. The storage and registers are merely storing data that is recited to generally link the data to the application of neural network processing, and the multiplier and accumulator are recited at a high level of generality. Thus, the additional elements of the claim recite the equivalent of “apply it” to the application of neural network processing.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8, 10-17, 19-22 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 21, at Step 1, the claim is directed to a data processing apparatus, which is a statutory category of invention (Machine).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A data processing apparatus for a convolutional neural network (CNN) having one or more filters, where a filter of the one or more filters has a plurality of M-bit weights, where M is an integer (mathematical relationship), the CNN comprising:
storage for the one or more filters in an Extended Block Floating-Point (EBFP) format, where each filter includes a shared exponent and an M-bit word for each weight of the filter (mathematical relationship);
storage for a block of an input feature map (IFM) in the EBFP format, where each block includes a shared exponent and an M-bit word for each element of the block (mathematical relationship);
an EBFP multiplier including: a first M-bit input register configured to store an element of the block in EBFP format;
and a second M-bit input register configured to store a filter weight in EBFP format;
an accumulator having a width greater than M-bits, the accumulator configured to accumulate outputs from the EBFP multiplier to provide an accumulated value corresponding to an element of an output feature map (mathematical relationship),
wherein the M-bit word includes one or more tag bits, a sign bit and a number of bits for storing a payload indicative of either an exponent difference or an encoded significand (mathematical relationship),
and wherein the element of the output feature map is more accurate than if generated from a block is represented as a shared exponent and an M-bit significand (mathematical relationship).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitations “storage for the one or more filters in an Extended Block Floating-Point (EBFP) format”, “storage for a block of an input feature map (IFM) in the EBFP format”, “a first M-bit input register configured to store an element of the block in EBFP format”, and “a second M-bit input register configured to store a filter weight in EBFP format” are merely storing data. The limitations “data processing apparatus”, “an EBFP multiplier”, and “an accumulator” are merely recited at a high level of generality to provide conventional computer functions. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the functions of “storage for the one or more filters in an Extended Block Floating-Point (EBFP) format”, “storage for a block of an input feature map (IFM) in the EBFP format”, “a first M-bit input register configured to store an element of the block in EBFP format”, and “a second M-bit input register configured to store a filter weight in EBFP format” is storing information that is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Furthermore, the “data processing apparatus”, “an EBFP multiplier”, and “an accumulator” are the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 1, at Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
The data processing apparatus of claim 21, where the EBFP multiplier includes:
a decoder, coupled to the first and second input registers and configured to generate: a first exponent difference and at least a fractional part of a first significand based on a first tag and a first payload of a first operand (mathematical calculation, mental process) stored in the first input register, and a second exponent difference and at least a fractional part of a second significand based on a second tag and a second payload of a second operand (mathematical calculation, mental process) stored in the second input register;
a significand multiplier, coupled to the decoder and configured to generate an output significand as a product of the first significand and the second significand (mathematical calculation, mental process);
and an exponent combiner configured to: generate an output exponent by summing a shared exponent of the first operand and a shared exponent of the second operand, subtracting the first exponent difference, if not zero, and subtracting the second exponent difference, if not zero (mathematical calculation, mental process);
wherein the output from the EBFP multiplier includes the output exponent and at least a fractional part of the output significand (mathematical relationship).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitations decoder, significand multiplier, and exponent combiner are recited at a high level of generality such that they provide conventional computer functions (decoding, multiplication, and summation). Furthermore, the coupling of the elements are structures that are a consequence of the data format and mathematical process, such that the structure is merely arranged to apply the mathematical calculations. The limitations stored in the first input register and stored in the second input register are merely an insignificant extra-solution activity of storing information. For these reasons, claim 1 is not integrated into a practical application.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the additional elements of decoder, significand multiplier, and exponent combiner are the equivalent of merely adding the words “apply it” to the judicial exception. Furthermore, the storing is recognized by the courts as well understood, routine, and conventional components and activity. See MPEP 2106.05(d). For these reasons, claim 1 does not amount to significantly more than the abstract idea.
Regarding claim 2, it is directed to the mathematical concept and/or mental process of add one to the output exponent… and right-shift the output significand….
Under Step 2A Prong 2, the claim recites additional element “shifter”. The additional element does not integrate the abstract ideas into a practical application because the shifter is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 3, it is directed to the mathematical concept and/or mental process of the first operand includes… and generate the output sign as an “exclusive or” …
Under Step 2A Prong 2, the claim recites additional element “XOR logic unit”. The additional element does not integrate the abstract ideas into a practical application because the logic unit is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 4, the claim merely recites an order of operations that further mathematically limit the mathematical concepts of claim 1. They do not include additional elements that would require further analysis under steps 2A prong 2 and step 2B.
Regarding claim 5, it is directed to the mathematical concept and/or mental process of decoding the operands.
Under Step 2A Prong 2, the claim recites additional elements “first decoder” and “second decoder”. The additional elements do not integrate the abstract ideas into a practical application because the decoders are recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 6, it is directed to the mathematical concept and/or mental process of determine the first exponent difference based on at least the first payload, determine the first exponent difference based on the payload, and select between the first decoder and the second decoder….
Under Step 2A Prong 2, the claim recites additional elements “a first decoder”, “a second decoder”, and “a controller”. The additional elements do not integrate the abstract ideas into a practical application because the “a first decoder”, “a second decoder”, and “a controller” are recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claims 7-8, the claims merely recite functions for the decoders that further mathematically limit the mathematical concepts, or provide additional mathematical functions, of claim 6. They do not include additional elements that would require further analysis under steps 2A prong 2 and step 2B.
Regarding claim 10, it is directed to the mathematical concept and/or mental process of shift the output… and add the shifted significand…
Under Step 2A Prong 2, the claim recites additional element “shifter”. The additional element does not integrate the abstract ideas into a practical application because the “shifter” is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 11, at Step 1, the claim is directed to a system, which is a statutory category of invention (Machine).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A system for performing multiply-accumulate operations in a neural network processor, comprising:
an EBFP multiplier including:
a first register configured to store a filter weight of the plurality of filter weights of a neural network;
a second register configured to store an element of the one or more input feature maps of the neural network;
a decoder, coupled to the first and second registers and configured to: generate a first exponent difference and at least a fractional part of a first significand based on a first tag and a first payload of a filter weight of the plurality of filter weights (mathematical calculation, mental process), and generate a second exponent difference and at least a fractional part of a second significand based on a second tag and a second payload of an element of the one or more input feature maps (mathematical calculation, mental process);
a significand multiplier, coupled to the decoder and configured to generate an output significand as a product of the first significand and the second a significand (mathematical calculation, mental process);
an exponent combiner, coupled to the decoder and configured to generate an output exponent by summing a shared exponent of a first operand and a shared exponent of a second operand and subtracting the first exponent difference and the second exponent difference (mathematical calculation, mental process);
and an accumulator having one or more lanes and configured to: shift the output significand based on the output exponent to generate a shifted significand (mathematical calculation, mental process), and add the shifted significand to a selected lane of one or more lanes of the accumulator (mathematical calculation, mental process).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation decoder, significand multiplier, exponent combiner, and accumulator provide conventional computer functions (decoding, multiplication, summation, and accumulation) and the structures are recited at a high level of generality. The limitations first register configured to store and second register configured to store are merely an insignificant extra-solution activity of storing information. For these reasons, claim 11 is not integrated into a practical application.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception As set forth in step 2A prong 2 analysis, the additional elements of decoder, significand multiplier, exponent combiner, and accumulator are the equivalent of merely adding the words “apply it” to the judicial exception. Furthermore, the storing is recognized by the courts as well understood, routine, and conventional components and activity. See MPEP 2106.05(d). For these reasons, claim 11 does not amount to significantly more than the abstract idea.
Regarding claims 22, 12-17, the claims are directed to a method that would be practiced by the apparatus of claims 21, 1-3, 6-8, respectively. All steps performed by the method of claims 22, 12-17, are executed by the apparatus in claims 21, 1-3, 6-8, as configured. The analysis of claims 21, 1-3, 6-8 applies equally to claims 22, 12-17.
Regarding claim 19, the claim merely recites a mathematical relationship of the first operand to further mathematically limit the mathematical concepts of claim 12, They do not include additional elements that would require further analysis under steps 2A prong 2 and step 2B.
Regarding claim 20, the claim is directed to a method that would be practiced by the apparatus of claim 10. All steps performed by the method of claim 20 are executed by the apparatus in claim 10 as configured. The analysis of claim 10 applies equally to claim 20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Burger (US 20190057303 A1, hereinafter “Burger”) in view of Wegener (US 20110099295 A1, hereinafter “Wegener”).
As per claim 21, Burger teaches A data processing apparatus for a convolutional neural network (CNN) having one or more filters, where a filter of the one or more filters has a plurality of M-bit weights, where M is an integer (Burger: [0018]), the CNN comprising:
storage for the one or more filters in an Extended Block Floating-Point (EBFP) format, where each filter includes a shared exponent and an M-bit word for each weight of the filter (Burger: Fig. 8 element 806; [0051]);
storage for a block of an input feature map (IFM) in the EBFP format, where each block includes a shared exponent and an M-bit word for each element of the block (Burger: Fig. 8 element 804; [0051]);
an EBFP multiplier including: a first M-bit input register configured to store an element of the block in EBFP format (Burger: Fig. 9; [0057]);
and a second M-bit input register configured to store a filter weight in EBFP format (Burger: Fig. 9; [0057]);
an accumulator having a width greater than M-bits, the accumulator configured to accumulate outputs from the EBFP multiplier to provide an accumulated value corresponding to an element of an output feature map (Burger: Fig. 8 element 812),
and wherein the element of the output feature map is more accurate than if generated from a block is represented as a shared exponent and an M-bit significand (The structure results in the function).
However, while Burger teaches a processor for block floating point format ([0049]), Burger does not explicitly disclose the details of the block-floating point format. Thus, Burger does not teach wherein the M-bit word includes one or more tag bits, a sign bit and a number of bits for storing a payload indicative of either an exponent difference or an encoded significand,
Wegener teaches wherein the M-bit word includes one or more tag bits, a sign bit and a number of bits for storing a payload indicative of either an exponent difference or an encoded significand (Wegener: Fig. 2 element 410; Fig. 3b element 522; [0086]),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the block-floating point format of Burger with the enhanced block floating point format of Wegener. One would have been motivated to combine these references because both references disclose processors computing with data with shared exponents, and Wegener’s format enables more efficient use of resources ([0002]).
As per claim 22, the claim is directed to a method that implements the same or similar features as the apparatus of claim 21, and is therefore rejected for at least the same reasons therein.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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