DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/8/2025 has been entered.
REJECTIONS NOT BASED ON PRIOR ART
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “configure at least one original block of the one or more blocks into sub-blocks dynamically based on a usage pattern of the device comprising at least a need to store data in a space smaller than the at least one original block.” The specification does not adequately describe this limitation of the claim. Paragraph 0062 states “blocks may be divided into sub-blocks in response to a need for additional space, just prior to data being written to the blocks, and/or when usage patterns indicate that sub-blocks would provide more optimal operation performance.” The specification does not describe configuring at least one original block of the one or more blocks into sub-blocks dynamically based on a usage pattern of the device comprising at least a need to store data in a space smaller than the at least one original block. The specification describes dividing data into sub-blocks in response to a need for additional space and/or when usage patterns indicate that sub-blocks would provide more optimal operation performance. Therefore, claim 1 contains new matter. Applicant is required to cancel the new matter. The other independent claims are rejected for similar reasons. The dependent claims inherit this rejection.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable Chang et al (US 2014/0310447) in view of Lordello et al (US 8,688,948).
Regarding Claim 1, Chang teaches a device comprising:
a processor (processor subsystem 414 of Fig. 4);
a memory array comprising:
a plurality of memory devices (memory subsystem 426 of Fig. 4) wherein the memory devices are configured into one or more blocks (“erasable blocks,” Paragraph 0013); and
a sub-block management logic configured to:
configure at least one original block of the one or more of the blocks into sub-blocks wherein the sub-blocks generated from each block are related sub-blocks within the at least one original block (“the status data partitions each erasable block of the memory array into a plurality of [related] sub-blocks,” Paragraph 0022);
operate the sub-blocks as individual blocks (each sub-block has a particular status, Paragraph 0023, and can receive erase commands individually, step 220 of Fig. 2, and therefore the sub-blocks are operated as individual blocks);
receive a command to erase a particular sub-block (the command corresponding to “a request to erase a selected sub-block of a particular erasable block,” step 220 of Fig. 2);
determine a status of all related sub-blocks of the particular sub-block, wherein the determination evaluates the related sub-blocks for an erase-ready state comprising at least an unallocated or released state of a related sub-block (“are other [related] sub-blocks of the particular erasable block invalid [erase-ready/released]?” step 220 of Fig. 2);
in response to the status determination, erasing both the particular sub-block (“YES” at step 220 of Fig. 2), and any related sub-blocks that are in an erase-ready state (step 230 of Fig. 2), wherein the particular sub-block and any related are within the at least one original block (Paragraph 0013).
However, the cited prior art does not explicitly teach to configure at least one or more blocks into sub-blocks dynamically based on a usage pattern of a device comprising at least a need to store data in a space smaller than the at least one original block.
Lordello teaches to configure at least original block of the one or more blocks (“monolithic blocks,” C21 L10-42) into sub-blocks (“one or more of these monolithic blocks may be converted a fragmented block,” the fragments corresponding to sub-blocks, C21 L10-42) dynamically based on a usage pattern of a device comprising at least a need to store data in a space smaller than the at least one original block (when the pattern of data is such that data to be stored is of “a size less than the size of the monolithic blocks, the hardware controller 110 will fragment an available monolithic block (using, e.g., the fractal fragmentation process described above) so as to generate a fragmented block with different order block segments available for mapping,” C21 L10-42).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the configuring of sub-blocks of Lordello in the cited prior art in order to increase storage efficiency.
Regarding Claim 2, the cited prior art teaches the device of claim 1, wherein, the sub-block management logic is further configured to update the state of the related sub-blocks to an erased status (the blocks are marked as free/erased at step 235 of Fig. 2).
Regarding Claim 3, the cited prior art teaches the device of claim 1, wherein each block is configured into two sub-blocks (Paragraph 0022).
Regarding Claim 4, the cited prior art teaches the device of claim 3, wherein each sub-block has one related sub-block (Paragraph 0022).
Regarding Claim 5, the cited prior art teaches the device of claim 1, wherein each block is configured into four sub-blocks (Paragraph 0022).
Regarding Claim 6, the cited prior art teaches the device of claim 5, wherein each block has three related sub-blocks (Paragraph 0022).
Regarding Claim 7, the cited prior art teaches the device of claim 1, wherein the erasing of the particular sub-block and related sub- blocks comprises erasing the entire regular block (step 230 of Fig. 2).
Regarding Claim 8, the cited prior art teaches the device of claim 1, wherein the erasing is completed in one erasing action (the one erasing action corresponding to the “erase command” of step 230 of Fig. 2).
Regarding Claim 9, the cited prior art teaches the device of claim 8, wherein the one erasing action erases the entire block comprising the particular sub-block and related sub-blocks (step 230 of Fig. 2).
Regarding Claim 10, the cited prior art teaches the device of claim 1, wherein the erasing action is paused until all related sub-blocks are in an unallocated state (the erasing action corresponding to the steps of Fig. 2, which is paused for the block at step 240 until a new erase request is received at step 220 of Fig. 2).
Regarding Claim 11, Chang teaches a device comprising:
a processor (processor subsystem 414 of Fig. 4);
a memory array comprising:
a plurality of memory devices (memory subsystem 426 of Fig. 4) wherein the memory devices are configured into one or more blocks (“erasable blocks,” Paragraph 0013); and
a sub-block management logic configured to:
configure at least one original block of the one or more of the blocks into sub-blocks wherein the sub-blocks generated from each block are related sub-blocks within the at least one original block (“the status data partitions each erasable block of the memory array into a plurality of [related] sub-blocks,” Paragraph 0022);
operate the sub-blocks as individual blocks (each sub-block has a particular status, Paragraph 0023, and can receive erase commands individually, step 220 of Fig. 2, and therefore the sub-blocks are operated as individual blocks);
determine that a particular sub-block should be released (the command corresponding to “a request to erase a selected sub-block of a particular erasable block” at step 220 of Fig. 2, it is a determination that a sub-block should be erased [released]);
check the release status of all related sub-blocks of the particular sub-block (“are other [related] sub-blocks of the particular erasable block invalid [released]?” step 220 of Fig. 2);
determine a status of all related sub-blocks of the particular sub-block, wherein the determination evaluates the related sub-blocks for an erase-ready state (“are other [related] sub-blocks of the particular erasable block invalid [erase-ready]?” step 220 of Fig. 2);
in response to the status determination, erasing both the particular sub-block (“YES” at step 220 of Fig. 2), and any related sub-blocks that are in an erase-ready state (step 230 of Fig. 2), wherein the particular sub-block and any related sub-blocks are within the at least one original block (Paragraph 0013).
However, the cited prior art does not explicitly teach to configure at least one or more blocks into sub-blocks dynamically based on a usage pattern of a device comprising at least a need to store data in a space smaller than the at least one original block.
Lordello teaches to configure at least original block of the one or more blocks (“monolithic blocks,” C21 L10-42) into sub-blocks (“one or more of these monolithic blocks may be converted a fragmented block,” the fragments corresponding to sub-blocks, C21 L10-42) dynamically based on a usage pattern of a device comprising at least a need to store data in a space smaller than the at least one original block (when the pattern of data is such that data to be stored is of “a size less than the size of the monolithic blocks, the hardware controller 110 will fragment an available monolithic block (using, e.g., the fractal fragmentation process described above) so as to generate a fragmented block with different order block segments available for mapping,” C21 L10-42).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the configuring of sub-blocks of Lordello in the cited prior art in order to increase storage efficiency.
Regarding Claim 12, the cited prior art teaches the device of claim 11, wherein the erasing is completed in one erasing action (the one erasing action corresponding to the “erase command” of step 230 of Fig. 2).
Regarding Claim 13, the cited prior art teaches the device of claim 12, wherein the one erasing action erases the entire block comprising the particular sub-block and related sub-blocks (step 230 of Fig. 2).
Regarding Claim 14, the cited prior art teaches the device of claim 11, wherein the sub-block management logic is further configured to update the state of the related sub-blocks to an erased status (step 235 of Fig. 2).
Regarding Claim 15, Chang teaches a method erasing sub-blocks, the method comprising:
configuring at least one original block of one or more blocks (“erasable blocks,” Paragraph 0013) within a memory array (memory subsystem 426 of Fig. 4) of a storage device (storage subsystem of Fig. 4) into sub- blocks wherein the sub-blocks are generated from each block are related sub- blocks within the at least one original block (“the status data partitions each erasable block of the memory array into a plurality of [related] sub-blocks,” Paragraph 0022);
operate the sub-blocks as individual blocks within the storage device (each sub-block has a particular status, Paragraph 0023, and can receive erase commands individually, step 220 of Fig. 2, and therefore the sub-blocks are operated as individual blocks);
receive a command to erase a particular sub-block (the command corresponding to “a request to erase a selected sub-block of a particular erasable block,” step 220 of Fig. 2);
check a status of all related sub-blocks of the particular sub-block, wherein the check evaluates the related sub-blocks for an erase-ready state (“are other [related] sub-blocks of the particular erasable block invalid [erase-ready]?” step 220 of Fig. 2);
in response to status determination, erasing both the particular sub-block, and any related sub-blocks in a single erasing action (YES path after step 220 and step 230 of Fig. 2), wherein the particular sub-block and any related sub-blocks are within the at least one original block (Paragraph 0013).
However, the cited prior art does not explicitly teach to configure at least one or more blocks into sub-blocks dynamically based on a usage pattern of a device.
Lordello teaches to configure at least one or more blocks (“monolithic blocks,” C21 L10-42) into sub-blocks (“one or more of these monolithic blocks may be converted a fragmented block,” the fragments corresponding to sub-blocks, C21 L10-42) dynamically based on a usage pattern of a device (when the pattern of data is such that data to be stored is of “a size less than the size of the monolithic blocks, the hardware controller 110 will fragment an available monolithic block (using, e.g., the fractal fragmentation process described above) so as to generate a fragmented block with different order block segments available for mapping,” C21 L10-42).
Regarding Claim 16, the cited prior art teaches the method of claim 15, wherein, the sub-block management logic is further configured to update the state of the related sub-blocks to an erased status (step 235 of Fig. 2).
Regarding Claim 17, the cited prior art teaches the method of claim 15, wherein the release status of all related sub-blocks of the particular sub-block is checked (“are other [related] sub-blocks of the particular erasable block invalid [released]?” step 220 of Fig. 2).
Regarding Claim 18, the cited prior art teaches the method of claim 17, wherein the method determines if all related sub-blocks are released prior to erasing (“are other [related] sub-blocks of the particular erasable block invalid [released]?” step 220 of Fig. 2).
Regarding Claim 19, the cited prior art teaches the method of claim 15, wherein the erasing is completed in one erasing action (the one erasing action corresponding to the “erase command” of step 230 of Fig. 2).
Regarding Claim 20, the cited prior art teaches the method of claim 19, wherein the one erasing action erases the entire block comprising the particular sub-block and related sub-blocks (step 230 of Fig. 2).
ARGUMENTS CONCERNING NON-PRIOR ART REJECTIONS/OBJECTIONS
Rejections - USC 112
Applicant's arguments/amendments with respect to claims 15-20 have been considered and have overcome the Examiner’s prior rejections and thus are withdrawn.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
On page 8 of the submitted remarks, applicant argues the cited prior art fails to teach “in response to the status determination, erasing both the particular sub-block, and any related sub-blocks that are in an erase- ready state, wherein the particular sub-block and any related sub-blocks are within the at least one original block” because Chang teaches an “all-or-nothing” approach where the system either erases the entire parent block or performs no physical erase at all.
This argument has been considered but is not persuasive.
Though the examiner acknowledges Chang teaches an approach where the system either erases the entire parent block or performs no physical erase at all, the claim language does not capture the concept of “an opportunistic partial erase.” Claim 1 recites “in response to the status determination, erasing both the particular sub-block, and any related sub-blocks that are in an erase-ready state, wherein the particular sub-block and any related sub-blocks are within the at least one original block.” The examiner maintains that when sub-blocks are erased at step 240 of Fig. 2 of Chang, the erased blocks are “within the at least one original block” in the broadest reasonable interpretation, as all the sub-blocks are part of the at least one original block. Therefore, the cited prior art teaches the independent claims as amended and the rejections have been maintained. Additionally, the examiner notes partial block erases are known in the art – see, for example, Kim (US 2008/0219053), particularly Figs. 8 and 9.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have been rejected.
DIRECTION OF FUTURE CORRESPONDENCE
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on (571) 272 - 5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135