DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“hardware logic to concurrently process a number of workloads” in claim 1, which will be interpreted as execution resources of a processor according to [00341] of the specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Response to Amendment
This office action is in response to the amendment filed on 01/21/2026. Claims 1-24 are pending. Claims 1, 5-9, and 13-24 are amended.
Response to Arguments
Applicant's arguments filed 01/21/2026 have been fully considered but they are not persuasive.
On page 10 of the Remarks, Applicant argues that the amendment to claim 1 clarifies that each compute hardware context is mapped to a partition of hardware within a processor, not software.
However, this argument is not persuasive because the broadest reasonable interpretation of the term “execution resources of a processor” would include any resources used by a processor for execution. Das teaches that the operating system 104 of the computing device 102 (i.e., a processor) may be capable of executing threads, see [0041]-[0042], thus the operating systems of Das are execution resources of a processor.
On page 10-11 of the Remarks, Applicant argues that “Using identifier to associate a subset of execution resources of a processor as recited in the amended claim 1 is unrelated to identifying a software in configuring a data module to collect the corresponding performance data related to the OS.” and that “These identifiers are used to configure for which entity the performance data is to be received by the data module 304 in Das, and it does not specify an identifier associated with a subset of execution resources of a processor, where the identifier is included in commands or hardware messages to provide corresponding performance monitoring data. Das appears to be silent about the command or hardware messages to collect performance data from different entities.”
However, this argument is not persuasive because the broadest reasonable interpretation of “commands or hardware messages to provide corresponding performance monitoring data” would include any set of signals that includes the identifier specified by the data module to receive performance monitoring data as taught by Das [0075].
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “compute hardware contexts” in lines 10-11. It is unclear whether these are the same as the plurality of compute hardware contexts introduced in line 3 or if they are different.
Claim 1 recites “the plurality of compute hardware contexts” in lines 11-12. It is unclear whether this refers to the compute hardware contexts introduced in line 3 or lines 11-12.
Claim 3 recites “the plurality of compute hardware contexts” in line 3. It is unclear which of the compute hardware contexts introduced in claim 1 this refers to.
Claim 4 recites “the plurality of compute hardware contexts” in line 3. It is unclear which of the compute hardware contexts introduced in claim 1 this refers to.
Claim 5 recites “the compute hardware contexts” in line 3. It is unclear which of the compute hardware contexts introduced in claim 1 this refers to.
Claim 9 recites “compute hardware contexts” in lines 9-10. It is unclear whether these are the same as the plurality of compute hardware contexts introduced in line 2 or if they are different
Claim 9 recites “the plurality of compute hardware contexts” in line 10-11. It is unclear whether this refers to the plurality of compute hardware contexts introduced in line 2 or lines 9-10.
Claim 11 recites “the plurality of compute hardware contexts” in line 3. It is unclear which of the compute hardware contexts introduced in claim 9 this refers to.
Claim 12 recites “the plurality of compute hardware contexts” in line 3. It is unclear which of the compute hardware contexts introduced in claim 9 this refers to.
Claim 13 recites “the compute hardware contexts” in line 3. It is unclear which of the compute hardware contexts introduced in claim 9 this refers to.
Claim 17 recites “compute hardware contexts” in line 11-12. It is unclear whether these are the same as the plurality of compute hardware contexts introduced in line 4 or if they are different.
Claim 17 recites “the plurality of compute hardware contexts” in line 12-13. It is unclear whether this refers to the compute hardware contexts introduced in line 4 or line 11-12.
Claim 19 recites “the plurality of compute hardware contexts” in line 4. It is unclear which of the compute hardware contexts introduced in claim 17 this refers to.
Claim 20 recites “the plurality of compute hardware contexts” in lines 3-4. It is unclear which of the compute hardware contexts introduced in claim 17 this refers to.
Claim 21 recites “the plurality of compute hardware contexts” in line 3. It is unclear which of the compute hardware contexts introduced in claim 17 this refers to.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-10, 16-18, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Das US 2017/0109251 in view of King US 6,986,137.
Regarding claim 1, Das teaches:
1. An apparatus comprising:
hardware logic to concurrently process a number of workloads (the processor (i.e., hardware logic) concurrently processes threads corresponding to the operating systems, see [0055] describing concurrently executing threads and [0060] describing the operating systems executing threads, where the work corresponding to each operating system is a workload), the compute hardware logic to be subdivided into a plurality of compute hardware contexts, each of the plurality of compute hardware contexts comprising a subset of execution resources of a processor (by sharing the processor among the multiple operating systems, see [0061], the processor is subdivided into a plurality of contexts comprising the operating systems, each operating system is a subset of execution resources of the computing device 102/processor); and
programmable performance monitoring circuitry (Fig. 2, 110 and 210) to be dynamically partitioned to perform parallel performance monitoring operations to monitor performance of each of the plurality of compute hardware contexts while the number of workloads are concurrently processed ([0062]-[0063] describes that each memory table 210 is associated with an operating system and that a new memory table is instantiated when a new operating system is created, which dynamically partitions the performance monitoring circuitry, see also [0055] describing concurrent execution and [0083] describing that the performance data is obtained concurrently/in parallel, which indicates that the performance monitory circuitry performs parallel performance monitoring of the operating systems/contexts while the workloads (corresponding to the operating systems) are concurrently processed), the programmable performance monitoring circuitry to differentiate between performance monitoring data of different compute hardware contexts based on a unique identifier that is associated with each of the plurality of compute hardware contexts and included in commands or hardware messages to provide corresponding performance monitoring data ([0075]: the data module may specify the operating system to receive its performance data, which indicates that the performance monitoring circuitry differentiates between performance monitoring data of different operating systems/contexts based on a unique operating system identifier associated with each of the operating systems, where any signals used by the data module to specify the operating system is a command or hardware message used to provide the corresponding performance monitoring data).
Das does not teach subdividing the processor based on the number of workloads;
However, King teaches a workload manager that redistributes processing resources to logical partitions based on a logical partition (analogous to the operating systems of Das) being added or removed from a group (i.e., based on the number of workloads corresponding to the logical partitions), see col 7 lines 31-65.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Das to redistribute processing resources of the processor based on the number of operating systems (having corresponding workloads). One of ordinary skill in the art would have been motivated to make this modification to ensure that each operating system has processing resources.
Claim 9 is directed to a method performing the steps of the apparatus of claim 1 and is rejected for the same reasons as claim 1.
Claim 17 is directed to program code stored on a non-transitory machine-readable medium that causes a machine to perform the operations of claim 1 and is rejected for the same reasons as claim 1.
Regarding claim 2, Das in view of King teaches:
2. The apparatus of claim 1, wherein the programmable performance monitoring circuitry includes a hardware security state machine to enter into a selected context-specific state indicated by a selected unique identifier associated with a selected hardware context, the programmable performance monitoring circuitry to provide performance monitoring data associated with the selected hardware context only in response to requests from the selected hardware context (Das Fig. 6 shows storing performance data in the memory tables at step 606 and reading performance data from the memory tables at step 608, which indicates a state machine of the monitoring circuitry (i.e., a state in which the memory tables are written and a state in which the memory tables are read), and since a memory table may only be read by an associated operating system, see [0062], the state machine is a hardware security state machine and the state in which an operating system reads its associated memory table is a selected context-specific state indicated by a unique identifier associated with the operating system/context, see [0075] describing that the data module (of an operating system) specifies which performance data to receive by specifying the operating system (i.e., a selected unique identifier)).
Claim 10 is directed to a method performing the steps of the apparatus of claim 2 and is rejected for the same reasons as claim 2.
Claim 18 is directed to program code stored on a non-transitory machine-readable medium that causes a machine to perform the operations of claim 2 and is rejected for the same reasons as claim 2.
Regarding claim 8, Das in view of King teaches:
8. The apparatus of claim 1 wherein the hardware logic is to be subdivided into a new plurality of compute hardware contexts in response to a change in the number of workloads (Das [0063]: a new operating system may be created, which is a change in the number of workloads (associated with the operating systems), and in the combination with King, the processor resources would be redistributed/subdivided into a new plurality of contexts), and wherein the programmable performance monitoring circuitry is to be dynamically re-configured to perform parallel performance monitoring operations to monitor performance of each of the new plurality of compute hardware contexts (Das [0063]: a new memory table is instantiated for the new operating system, which dynamically reconfigured the monitoring circuitry (by adding the new memory table) to monitor performance of the new plurality of operating systems/contexts in parallel).
Claim 16 is directed to a method performing the steps of the apparatus of claim 8 and is rejected for the same reasons as claim 8.
Claim 24 is directed to program code stored on a non-transitory machine-readable medium that causes a machine to perform the operations of claim 8 and is rejected for the same reasons as claim 8.
Claims 3-7, 11-15, 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Das US 2017/0109251 in view of King US 6,986,137 and Cole US 2021/0096855.
Regarding claim 3, Das in view of King teaches:
3. The apparatus of claim 2
Das in view of King does not teach:
wherein the programmable performance monitoring circuitry comprises a command streamer interface to couple the programmable performance monitoring circuitry to command streamers of the plurality of compute hardware contexts.
However, Cole teaches a command streamer that provides commands to each core, see [0053].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Das to include command streamers that provide commands to each core as taught by Cole. In this combination, the command streamers would be used by the operating systems to provide commands to the cores, and the interface of the performance metric capture device and the processor (Das Fig. 2) is a command streamer interface that would couple the performance monitoring circuitry to the command streamers of the operating systems. One of ordinary skill in the art would have been motivated to make this modification to enable streaming commands to the cores which would reduce stalling.
Claim 11 is directed to a method performing the steps of the apparatus of claim 3 and is rejected for the same reasons as claim 3.
Claim 19 is directed to program code stored on a non-transitory machine-readable medium that causes a machine to perform the operations of claim 3 and is rejected for the same reasons as claim 3.
Regarding claim 4, Das in view of King and Cole teaches:
4. The apparatus of claim 3 wherein the programmable performance monitoring circuitry is to perform performance monitoring operations for a particular compute hardware context of the plurality of compute hardware contexts based on commands received from a command streamer associated with the particular compute hardware context (Das [0062] teaches memory tables that capture performance monitoring data for a particular operating system/context; in the combination with Cole, the performance monitoring would monitor the execution of commands received from a command receiver of the operating system).
Claim 12 is directed to a method performing the steps of the apparatus of claim 4 and is rejected for the same reasons as claim 4.
Claim 20 is directed to program code stored on a non-transitory machine-readable medium that causes a machine to perform the operations of claim 4 and is rejected for the same reasons as claim 4.
Regarding claim 5, Das in view of King and Cole teaches:
5. The apparatus of claim 4 wherein the programmable performance monitoring circuitry is to individually monitor performance of each of the compute hardware contexts (Das [0062]: the memory tables individually monitor performance of each of the operating systems/contexts).
Claim 13 is directed to a method performing the steps of the apparatus of claim 5 and is rejected for the same reasons as claim 5.
Claim 21 is directed to program code stored on a non-transitory machine-readable medium that causes a machine to perform the operations of claim 5 and is rejected for the same reasons as claim 5.
Regarding claim 6, Das in view of King and Cole teaches:
6. The apparatus of claim 5
Das in view of King and Cole does not teach:
wherein the programmable performance monitoring circuitry is to individually monitor performance of a plurality of render hardware contexts.
However, Cole further teaches ray tracing/rendering cores for ray tracing applications, see [0068].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Das to include ray tracing applications as taught by Cole such that the combination would include render hardware contexts that would be individually monitored by the performance monitoring circuitry. One of ordinary skill in the art would have been motivated to make this modification to support more types of applications.
Claim 14 is directed to a method performing the steps of the apparatus of claim 6and is rejected for the same reasons as claim 6.
Claim 22 is directed to program code stored on a non-transitory machine-readable medium that causes a machine to perform the operations of claim 6 and is rejected for the same reasons as claim 6.
Regarding claim 7, Das in view of King and Cole teaches:
7. The apparatus of claim 6 wherein the programmable performance monitoring circuitry is to globally monitor performance of the apparatus (Das [0062]: the memory tables 210a-n store the captured performance data for all the operating systems (i.e., globally monitor performance)).
Claim 15 is directed to a method performing the steps of the apparatus of claim 7 and is rejected for the same reasons as claim 7.
Claim 23 is directed to program code stored on a non-transitory machine-readable medium that causes a machine to perform the operations of claim 7 and is rejected for the same reasons as claim 7.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/KASIM ALLI/Examiner, Art Unit 2182 /JYOTI MEHTA/ Supervisory Patent Examiner, Art Unit 2183