DETAILED ACTION
This action is responsive to the communication filed 2 September 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election with traverse of the Species A/Subspecies I, Species B/Subspecies I, and Species C/Subspecies I embodiment in the reply filed on 8 April 2025 is acknowledged.
The requirement for restriction mailed 14 February 2025 was made FINAL in the Office Action mailed 11 June 2025.
Claims 6, 7, and 20 are withdrawn from consideration.
Response to Arguments
Applicant's arguments filed 16 January 2026 have been fully considered but they are not persuasive.
Regarding independent claim 1: The Examiner respectfully asserts that Yamamura renders independent claim 1 obvious even in light of Applicant’s amendments to independent claim 1, detailed in the 35 U.S.C. § 103 rejection of claim 1, below.
Drawings
The objection to the drawings is withdrawn, responsive to Applicant’s cancellation of the claims.
Claim Rejections - 35 USC § 112
The rejection of claims 3-5, 11, and 15 under § 112(a) is withdrawn, responsive to Applicant’s cancellation of the claims.
The rejection of clams 3-5 and 24 under § 112(b) is withdrawn, responsive to Applicant’s cancellation of claims 3-5 and amendment of claim 24.
A new rejection of claim 26 under § 112(a) appears below.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 26 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 26: claim 26 recites, in relevant part: “wherein the signal line is arranged in an interlayer insulating layer of the first substrate, and wherein the voltage line is arranged in an interlayer insulating layer of the second substrate.” Nowhere in the original disclosure does Applicant disclose the specific configuration of the signal line and voltage line outside of generally stating that the various lines of the device may be arranged in the wiring structures. See, e.g., [0042] of the instant application (“The light emitting element 201 can be arranged on a second surface S2 of the first substrate 11, the driving transistor 202 can be arranged in the first substrate 11, and the Vdd 204 and the Vss 205 can be arranged in a first wiring structure 512. . . . The write transistor 203 can be arranged in the second substrate 12, and the scanning line 106 and the signal line 107 can be arranged in the second wiring structure 522.”). Moreover, other descriptions of the configuration of the signal line and voltage line appear to conflict with the claimed configuration. Compare, e.g., claim 26 of the instant application (“The device according to claim 1, wherein the signal line is arranged in an interlayer insulating layer of the first substrate, and wherein the voltage line is arranged in an interlayer insulating layer of the second substrate.”) with, e.g., [0042] of the instant application, which appears to suggest the lines are not disposed in the interlayer insulating film (“From another viewpoint, the light emitting element 201, the driving transistor 202, the Vdd 204, and the Vss 205 can be arranged in the first structure formed from the first substrate 11 and the first wiring structure 512. . . . From another viewpoint, the write transistor 203, the scanning line 106, and the signal line 107 can be arranged in the second structure formed from the second substrate 12 and the second wiring structure 522.”). Accordingly, nowhere in the specification or any of FIGS. 1-22 does Applicant show, disclose, or reference the abovementioned configuration of the interlay insulating layer and the signal and voltage lines in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Thus, claim 26 is directed to subject matter the specification fails to describe.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2, 8, 12, 14, 17, 18, and 21-26 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Publication No. 2022/0102452 (filed Sept. 18, 2019) (hereinafter “Yamamura”).
Regarding independent claim 1, Yamamura discloses: A light emitting device (FIGS. 1/2, display apparatus 100, [0067]) having a structure in which a first substrate (FIG. 2, either of first semiconductor substrate 101 or second semiconductor substrate 102, [0068]) and a second substrate (FIG. 2, either of first semiconductor substrate 101 or second semiconductor substrate 102, [0068]) are stacked (FIG. 2, depicting wherein the first semiconductor substrate 101 and the second semiconductor substrate 102 have a structure (i.e., a configuration) wherein the semiconductor substrates 101/102 are stacked), the light emitting device comprising:
a plurality of light emitting elements (FIGS. 1/2/3, depicting pixel area 20 including a plurality of light emitting units 21, the light emitting units 21 including a plurality of light emitting devices 210 each separately driven by a corresponding pixel circuit 22, [0052]) arranged on the first substrate (FIG. 2, depicting wherein the light emitting devices 210 are arranged on the first semiconductor substrate 101 and second semiconductor substrate 102); and
a driving circuit configured to drive the plurality of light emitting elements (FIG. 3, depicting a circuit configured to drive each of the light emitting devices 210),
wherein the driving circuit includes a first transistor (FIG. 3, drive transistor TRDrv, [0056]), a second transistor (FIG. 3, image signal writing transistor TRSig, [0056]), and a third transistor (FIG. 3, first light-emission-control transistor TREL_C1, [0056]),
wherein
(1) the second transistor is arranged to connect a signal line and a node to which the first transistor is connected (FIG. 3, depicting wherein the image signal writing transistor TRSig is arranged to connect a data line DTL and a node to which the drive transistor TRDrv is connected, [0058]),
(2) the first transistor is arranged to supply one of the plurality of light emitting elements with a current in accordance with a signal input to the node (FIG. 3, depicting wherein the drive transistor TRDrv is arranged to supply the light emitting device 210 with a current according to an image signal input to the node between the image signal writing transistor TRSig and the drive transistor TRDrv, [0057]), and
(3) the third transistor is arranged to control connection between a voltage line and the first transistor, and to control light emission/non-light emission of the one of the plurality of light emitting elements (FIG. 3, depicting wherein the first light-emission-control transistor TrEL_C1 is arranged to control connection between drive voltage Vcc and the drive transistor TRDrv, and thus to control light emission/non-light emission, [0059]).
While Yamamura discloses in [0070] that “At least one of the four transistors (TrDrv, TrSig, TrEL_c1, TrEL_C2) of the pixel circuit 22 described with reference to FIG. 3 is formed in the first pixel circuit 221, and the other transistor(s) is/are formed in the second pixel circuit 222,” Yamamura does not specifically disclose wherein the first transistor and the second transistor are arranged in the first substrate, wherein the third transistor is arranged in the second substrate.
Regarding the relative locations of the transistors, however, it is well-established that “when there is motivation to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP § 2143(I)(E) (quoting KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, (2007)).
Currently, there is a recognized need in the art to create display devices that maximize performance and minimize cost, often accomplished by using fewer or more efficient processes to form the device such that the device is formed relatively quickly and efficiently, but which also meets desired performance specifications. In the present case, there are a finite number of identified, predictable potential solutions for meeting the abovementioned need in the context of material usage, including forming one of the transistors in first pixel circuit and forming three of the transistors in the second pixel circuit, forming two of the transistors in first pixel circuit and forming two of the transistors in the second pixel circuit, or forming three of the transistors in first pixel circuit and forming one of the transistors in the second pixel circuit, each having a reasonable expectation of success regardless of which known potential solution is pursued.
Accordingly, it would have been obvious to try forming two of the transistors in first pixel circuit and forming two of the transistors in the second pixel circuit, including the various possible combinations of transistors in each of the first and second pixel circuits, which includes a combination wherein the drive transistor TRDrv and image signal writing transistor TRSig are formed in the first pixel circuit 221 and the TrEL_C1 is formed in the second pixel circuit 222.
Moreover, formation of the drive transistor TRDrv and image signal writing transistor TRSig in the first pixel circuit 221 and formation of the first light-emission-control transistor TrEL_C1 in the second pixel circuit 222 would result in a configuration wherein the signal line is arranged in the first substrate (FIG. 3, depicting wherein at least a portion of the data line DTL must be formed in the substrate 101 to be connected to the image signal writing transistor TRSig), and wherein the voltage line is arranged in the second substrate (FIG. 3, depicting wherein at least a portion of the drive voltage line Vcc must be formed in the second substrate 102 to be connected to the first light-emission-control transistor TrEL_C1).
Regarding claim 2, Yamamura further discloses wherein the second transistor (FIGS. 1/2/3, image signal writing transistor TRSig) is arranged to write the signal to the node (FIGS. 1/2/3, depicting wherein the node between the image signal writing transistor TRSig and the drive transistor TRDrv would receive the signal from the image signal writing transistor TRSig; [0058]: “The image signal writing transistor TrSig is a row selection transistor that switches a signal voltage. The image signal writing transistor TrSig includes the other source/drain area to be connected to the image signal output circuit 25 via the data line DTL, and a gate to be connected to the scanning circuit 23 via the scanning line SCL.”), and wherein the node includes a gate of the first transistor (FIGS. 1/2/3, depicting wherein the node between the image signal writing transistor TRSig and the drive transistor TRDrv is electrically connected to the gate of the driving transistor TRDrv).
Regarding claim 8, Yamamura further discloses wherein the plurality of light emitting elements (FIGS. 1/2/3, depicting pixel area 20 including a light emitting unit 21, the light emitting unit 21 including a plurality of light emitting devices 210 arranged in a matrix) are arranged to form a plurality of rows and a plurality of columns (FIGS. 1/2/3, depicting pixel area 20 including a light emitting unit 21, the light emitting unit 21 including a plurality of light emitting devices 210 arranged in a matrix, the matrix formed from rows and columns of light emitting devices 210, [0052]: “As will be described below, the light emitting unit 21 includes a plurality of light emitting devices 210 arranged in a matrix in the horizontal direction (see FIG. 3).”), and wherein a plurality of signal lines (FIG. 3, depicting wherein each of the plurality of pixel circuits 22 includes a plurality of signal lines, for example, data line DTL and scanning line SCL, [0056]) extending in a column direction are provided for each column (FIG. 3, depicting wherein each of the plurality of pixel circuits 22 for each of the columns of the matrix are provided with a data line DTL and scanning line SCL extending in a column direction).
Regarding claim 12, Yamamura further discloses wherein the driving circuit further includes:
a first capacitive element (FIG. 3, first capacity unit C1, [0056]) arranged to electrically connect the first transistor to a connection node of the first transistor and the third transistor (FIG. 3, depicting wherein the capacity unit C1 electrically connects the driving transistor TRDrv to a connection node between the driving transistor TRDrv and the first light-emission-control transistor TrEL_C1); and
a second capacitive element (FIG. 3, second capacity unit C2, [0056]) arranged to electrically connect the connection node to the voltage line (FIG. 3, depicting the second capacity unit C2 electrically connects the connection node between the driving transistor TRDrv and the first light-emission-control transistor TrEL_C1 to the drive voltage line Vcc).
Regarding claim 14, Yamamura does not specifically disclose wherein the first capacitive element and the second capacitive element are arranged on the first semiconductor substrate.
In [0070], however, Yamamura states: “The first pixel circuit 221 [(in the first semiconductor substrate 101)] constitutes a first drive circuit that drives a light emitting unit 210, and the second pixel circuit 222 [(in the second semiconductor substrate 102)] constitutes a second drive circuit that drives the light emitting unit 210. At least one of the four transistors (TrDrv, TrSig, TrEL_c1, TrEL_C2) of the pixel circuit 22 described with reference to FIG. 3 is formed in the first pixel circuit 221, and the other transistor(s) is/are formed in the second pixel circuit 222. Similarly, at least one of the two capacity units (C1 and C2) constituting the pixel circuit 22 are formed in the first pixel circuit 221 or the second pixel circuit 222.” Regarding formation of the various capacity units in the various semiconductor substrates 101, 102, in [0092], Yamamura states: “As described above, in the display apparatus 100 according to this embodiment, the surface of the first semiconductor substrate 101 including the first pixel circuit 221 and the surface of the second semiconductor substrate 102 including the second pixel circuit 222 are bonded to each other to constitute the pixel circuit 22. By forming the pixel circuit 22 of originally-separated substrates, i.e., the first semiconductor substrate 101 and the second semiconductor substrate 102, the area necessary for forming the pixel circuit 22 is expanded in the thickness direction of the display apparatus 100. Therefore, it is possible to reduce the area of the pixel area 20 occupying the display surface 101 a.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to arrange both of the first and second capacity units in only one of the semiconductor substrates, such as the first semiconductor substrate 101 (See, e.g., FIG. 6, depicting wherein both the first and second capacity units C1 and C2 are formed in the same semiconductor substrate 102), as disclosed in [0070] of Yamamura, in order to reduce the area of the pixel area occupying the display surface. See Yamamura [0092].
Regarding claim 17, Yamamura further discloses wherein the plurality of light emitting elements (FIGS. 1/2/3, depicting pixel area 20 including a light emitting unit 21, the light emitting unit 21 including a plurality of light emitting devices 210 arranged in a matrix) include
(1) a plurality of light emitting elements of a first type (FIGS. 1/2/3, depicting pixel area 20 including a plurality of light emitting units 21, the light emitting units 21 including a plurality of light emitting devices 210 each separately driven by a corresponding pixel circuit 22, wherein groups of light emitting devices 210 constitute pixels, each pixel including for example, three sub-pixels (a red light emitting sub-pixel that emits red light, a green light emitting sub-pixel that emits green light, and a blue light emitting sub-pixel that emits blue light), wherein a light emitting device 210 emitting light of a first color may be a first type of light emitting device 210, [0002], [0052], [0063]) and
(2) a plurality of light emitting elements of a second type (FIGS. 1/2/3, depicting pixel area 20 including a plurality of light emitting units 21, the light emitting units 21 including a plurality of light emitting devices 210 each separately driven by a corresponding pixel circuit 22, wherein groups of light emitting devices 210 constitute pixels, each pixel including for example, three sub-pixels (a red light emitting sub-pixel that emits red light, a green light emitting sub-pixel that emits green light, and a blue light emitting sub-pixel that emits blue light), wherein a light emitting device 210 emitting light of a second color that is different from a first color may be a second type of light emitting device 210, [0002], [0052], [0063]), and
wherein the first type of light emitting element and the second type of light emitting element are configured to express different colors (FIGS. 1/2/3, depicting pixel area 20 including a plurality of light emitting units 21, the light emitting units 21 including a plurality of light emitting devices 210 each separately driven by a corresponding pixel circuit 22, wherein groups of light emitting devices 210 constitute pixels, each pixel including for example, three sub-pixels (a red light emitting sub-pixel that emits red light, a green light emitting sub-pixel that emits green light, and a blue light emitting sub-pixel that emits blue light), wherein a light emitting device 210 emitting light of a first color may be a first type of light emitting device 210, and a light emitting device 210 emitting a light of a second color that is different from a first color may be a second type of light emitting device 210, [0002], [0052], [0063]).
Yamamura further discloses wherein the first type of light emitting element and the second type of light emitting element are arranged adjacent to each other (FIGS. 1/2/3/4, depicting wherein the light emitting devices 210 are arranged adjacent to each other).
Regarding claim 18, Yamamura further discloses wherein the first type of light emitting element and the second type of light emitting element are arranged adjacent to each other (FIGS. 1/2/3, depicting wherein the light emitting devices 210 are arranged adjacent to each other).
Regarding claim 21, Yamamura further discloses wherein the light emitting device (FIGS. 1/2, display apparatus 100, [0067]) is configured as a display device (See, e.g., FIG. 12, wherein the display device is configured as a television apparatus 500, [0146])
Regarding claim 22, Yamamura further discloses a photoelectric conversion device (FIG. 15, video camera 800, [0149]) comprising: an image sensor configured to receive light having passed through an optical unit (FIG. 15, wherein the video camera 800 includes “a lens 820 for imaging an object, which is provided on the front side of the main body 810,” [0149]); and a display unit configured to display an image captured by the image sensor (FIG. 15, display unit 840, [0149]), wherein the display unit includes a light emitting device according to claim 1 ([0149]: “The display unit 840 includes the display apparatus according to any of the above-mentioned embodiments.”).
Regarding claim 23, Yamamura further discloses electronic equipment (FIG. 16, electronic apparatus, [0150]) comprising: a light emitting device according to claim 1 (FIG. 16, display 940, [0150]: “The display 940 or the sub-display 950 includes the display apparatus according to any of the above-mentioned embodiments.”); a housing provided with the light emitting device (FIG. 16, upper housing 910 and/or lower housing 920, [0150]); and a communication unit provided in the housing and configured to perform external communication (FIG. 16, the electronic apparatus is configured as a mobile phone 900, [0150]).
Regarding claim 24, Yamamura further discloses an illumination device comprising: a light emitting device according to claim 1 (FIG. 12, [0188]: “The television device 330 includes, for example, a video display screen unit 331 including a front panel 332 and a filter glass 333, and the video display screen unit 331 includes the display device 10, 10A according to any one of the first and second embodiments and the variations thereof described above.”); and one or both of (1) a light-diffusing unit (FIG. 12, front panel 332, [0188]) configured to transmit light emitted by the light emitting device (FIG. 12, depicting wherein the front panel 332 and filter glass 333 are configured to transmit light emitted by the display screen unit 331) and (2) an optical film (FIG. 12, filter glass 333, [0188]) configured to transmit light emitted by the light emitting device (FIG. 12, depicting wherein the front panel 332 and filter glass 333 are configured to transmit light emitted by the display screen unit 331).
Regarding claim 25, Yamamura further discloses a moving body (FIG. 16, electronic apparatus configured as a mobile phone 900 configured to move/rotate about a hinge 930, [0150]) comprising: a lighting appliance including a light emitting device according to claim 1 (FIG. 16, [0150]: “The display 940 or the sub-display 950 includes the display apparatus according to any of the above-mentioned embodiments.”); and a main body provided with the lighting appliance (FIG. 16, [0150]: “The display 940 or the sub-display 950 includes the display apparatus according to any of the above-mentioned embodiments.”).
Regarding claim 26, Yamamura further discloses wherein the signal line is arranged in an interlayer insulating layer of the first substrate (FIG. 3, depicting wherein at least a portion of the data line DTL must be formed in the substrate 101 to be connected to the image signal writing transistor TRSig), and wherein the voltage line is arranged in an interlayer insulating layer of the second substrate (FIG. 3, depicting wherein at least a portion of the drive voltage line Vcc must be formed in the second substrate 102 to be connected to the first light-emission-control transistor TrEL_C1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: U.S. Patent Publication Nos.: 2021/0142734 (disclosing a driving circuit having a configuration similar to the driving circuit of claim 1); 2016/0204179 (disclosing a driving circuit having a configuration similar to the driving circuit of claim 1); 2021/0193691 (disclosing a driving circuit having a configuration similar to the driving circuit of claim 1); 2023/0247864 (disclosing a multilayer wiring configuration similar to the structure of claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights