DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/21/2026 has been entered.
Response to Amendment
Claims 1-3, 5, 8-9, 12-13, 16-17, 22-23, 30-31, 40, 46, 48, 50, and 53 remain pending in the application, and claims 4, 6-7, 10-11, 14-15, 18-21, 24-29, 32-39, 41-45, 47, 49, 51-52, and 54-55 have been canceled. Applicant’s amendments to the Claims have overcome every 102 and 103 rejection previously set forth in the Final Office Action mailed 10/31/2025.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 46, and 48 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 9-10, 23, 30-31, 40, 46, 48, and 50 are rejected under 35 U.S.C. 103 as being unpatentable over Morita (US 20040246635 A1) in view of Nate (US 20070263420 A1).
Regarding independent claim 1, Morita discloses a balancing circuitry (Fig. 5: voltage detection circuit 60) for balancing a set of N cells (B1-B3) in a battery, the balancing circuitry comprising:
a switch network (61-66) configured to be coupled to the cells; and
a set of capacitors (67-69) coupled in parallel between the switch network and a common node (connecting node N4), wherein the balancing circuitry is configured to perform a cell balancing operation in which charge is transferred between subsets of the plurality of cells of the battery and the set of capacitors in consecutive first and second phases of operation (¶[15] and Figs. 1 and 5: examiner interprets phase one when capacitor 37 is coupled to cell B1, and capacitor 38 is coupled to cell B2 in balancing circuit 30 in Fig. 1 as applicable to the detection circuit 60 where phase 1 is when capacitors 67-68 are coupled to cell B1, and capacitors 68-69 are coupled to cell B2),
wherein the switch network is configured such that:
during the first phase of operation of the balancing circuitry (60) in a cell balancing operation, the set of capacitors (67-69) is coupled to a first subset comprising N-1 adjacent cells (B1-B2) of the set of N cells (B1-B3); (Fig. 5 has structure capable of performing the balancing process as described in ¶0015 and Fig. 1) and
during the second phase of operation of the balancing circuitry in the cell balancing operation the set of capacitors (67-69) is coupled to a second subset (B2-B3) comprising N-1 adjacent cells of the set of N cells (B1-B3) (Figs. 1 and 5 and ¶0015), wherein the second subset is different from the first subset,
and wherein, in operation of the balancing circuitry while it is performing the cell balancing operation, a reference voltage is supplied, intermittently, periodically or permanently to the common node by a reference voltage source (Fig. 5: N4 receives a voltage from any of the capacitors it is connected to. ¶[136]: The common node can have zero volts).
Morita does not disclose in operation of the balancing circuitry while it is performing the cell balancing operation, a reference voltage is supplied, intermittently, periodically or permanently to the common node by a reference voltage source external to the set of capacitors and the set of N cells.
Nate discloses a charging circuit that uses a reference voltage powered by an external source (¶[94] and Fig. 3: external power supply Vdc causes reference voltage source 52, BGR in Fig. 3, to generate predetermined reference voltage Vref).
Morita and Nate both disclose battery circuits. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to incorporate the reference voltage using an external source as disclose in Nate into the common node of Morita, for the purpose of provide a stable reference voltage for energy transfer control between the cells of Morita, and since it has been held to be within the general skill of a worker in the art to apply a known technique to a known device (method, or product) which was ready for improvement in order to yield results predictable by one of ordinary skill the art. KSR International Co. v Teleflex Inc., 550 U.S. 398, 127 S. Ct. 1727, 82 USPQ2d 1385, 1395-97 (2007).
Regarding independent claim 46, Morita discloses a balancing circuitry (Fig. 5: voltage detection circuit 60) for balancing a plurality of cells (B1-B3) of a battery, the balancing circuitry comprising:
a switch network (61-66) configured to be coupled to the cells;
a set of capacitors (67-69) coupled in parallel between the switch network and a common node;
wherein the balancing circuitry is configured to perform a cell balancing operation in which charge is transferred between different subsets of the plurality of cells of the battery and the set of capacitors (¶[15] and Figs. 1 and 5: examiner interprets phase one when capacitor 37 is coupled to cell B1, and capacitor 38 is coupled to cell B2 in balancing circuit 30 in Fig. 1 as applicable to the detection circuit 60 where phase 1 is when capacitors 67-68 are coupled to cell B1, and capacitors 68-69 are coupled to cell B2);
wherein, in operation of the balancing circuitry while it is performing the cell balancing operation, a reference voltage is supplied, intermittently, periodically or permanently, to the common node by a reference voltage source (Fig. 5: N4 can receive a voltage from any of the capacitors it is connected to. ¶[136]: The common node can have zero volts).
Morita does not disclose in operation of the balancing circuitry while it is performing the cell balancing operation, a reference voltage is supplied, intermittently, periodically or permanently to the common node by a reference voltage source external to the set of capacitors and the set of N cells.
Nate discloses a charging circuit that uses a reference voltage powered by an external source (¶[94] and Fig. 3: external power supply Vdc causes reference voltage source 52, BGR in Fig. 3, to generate predetermined reference voltage Vref).
Morita and Nate both disclose battery circuits. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to incorporate the reference voltage using an external source as disclose in Nate into the common node of Morita, for the purpose of provide a stable reference voltage for energy transfer control between the cells of Morita, and since it has been held to be within the general skill of a worker in the art to apply a known technique to a known device (method, or product) which was ready for improvement in order to yield results predictable by one of ordinary skill the art. KSR International Co. v Teleflex Inc., 550 U.S. 398, 127 S. Ct. 1727, 82 USPQ2d 1385, 1395-97 (2007).
Regarding independent claim 48, Morita discloses a balancing circuitry (Fig. 5: voltage detection circuit 60) for balancing a plurality of cells (B1-B3) of a battery, the balancing circuitry comprising a common node (connecting node N4), wherein the balancing circuitry is configured to perform a cell balancing operation in which charge is transferred between different subsets of the plurality of cells (¶[15] and Figs. 1 and 5: examiner interprets phase one when capacitor 37 is coupled to cell B1, and capacitor 38 is coupled to cell B2 in balancing circuit 30 in Fig. 1 as applicable to the detection circuit 60 where phase 1 is when capacitors 67-68 are coupled to cell B1, and capacitors 68-69 are coupled to cell B2), and wherein, in operation of the balancing circuitry while it is performing the cell balancing operation, a reference voltage is supplied, intermittently, periodically or permanently, to the common node by a reference voltage source (Fig. 5: N4 can receive a voltage from any of the capacitors it is connected to. ¶[136]: The common node can have zero volts).
Morita does not disclose in operation of the balancing circuitry while it is performing the cell balancing operation, a reference voltage is supplied, intermittently, periodically or permanently to the common node by a reference voltage source external to the set of capacitors and the set of N cells.
Nate discloses a charging circuit that uses a reference voltage powered by an external source (¶[94] and Fig. 3: external power supply Vdc causes reference voltage source 52, BGR in Fig. 3, to generate predetermined reference voltage Vref).
Morita and Nate both disclose battery circuits. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to incorporate the reference voltage using an external source as disclose in Nate into the common node of Morita, for the purpose of provide a stable reference voltage for energy transfer control between the cells of Morita, and since it has been held to be within the general skill of a worker in the art to apply a known technique to a known device (method, or product) which was ready for improvement in order to yield results predictable by one of ordinary skill the art. KSR International Co. v Teleflex Inc., 550 U.S. 398, 127 S. Ct. 1727, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 2, Morita discloses the balancing circuitry according to claim 1, wherein N is at least 3 (Fig. 5, B1-B3).
Regarding claim 3, Morita discloses the balancing circuitry according to claim 2, wherein:
the set of capacitors comprises N capacitors (Fig. 5: 67, 68, 69) and the switch network comprises a single tier of switching modules (61, 62, 63, 64, 65, 66); or
the set of capacitors comprises N-2 capacitors and the switch network comprises first and second tiers of switching modules (claim language sets this limitation as an alternative).
Regarding claim 5, Morita discloses the balancing circuitry according to claim 3, wherein the balancing circuitry comprises one capacitor and one switching module per cell of the battery pack (Fig. 5 shows one capacitor 67 and one switching module (switches 61 and 62) for one cell B1, and corresponding capacitors and switching modules for cells B2 and B3).
Regarding claim 9, Morita discloses the balancing circuitry according to claim 3, wherein each switching module (Fig. 5: pairs of switches coupled to each battery B1-B3) comprises a high-side switch (61, 63, 65) and a low-side switch (62, 64, 66) connected in series between first and second input nodes, wherein an output node of the switching module is coupled to a node (N1, N2, N3 respectively between 61 and 62, 63 and 64, and 65 and 66) between the high-side switch and the low-side switch.
Regarding claim 23, Morita discloses the balancing circuitry according to claim 1, wherein the common node is coupled to the reference voltage during a third phase of operation of the balancing circuitry, wherein:
the third phase of operation immediately follows the first phase or the second phase of operation (Fig. 5: the node N4 is always coupled to the reference voltage including during an arbitrarily defined third phase) (Claim language sets the following limitations of claim 23 as alternatives);
the third phase of operation follows a plurality of cycles of the first and second phases of operation;
the third phase of operation occurs during the first or second phase of operation;
the third phase of operation coincides with the first or second phase of operation so as to occupy the same amount of time as the first or second phase of operation;
the third phase of operation occupies a portion of the period of time occupied by the first or second phase of operation; or
the third phase of operation occurs during a beginning portion, a middle portion or an end portion of the first or second phase.
Regarding claim 30, Morita discloses the balancing circuitry according to claim 1, wherein the switch network is operable to connect two or more of the set of capacitors in parallel (Fig. 5).
Regarding claim 31, Morita discloses the balancing circuitry according to claim 1, further comprising control circuitry (Fig. 5: control section 39) for controlling the switch network.
Regarding independent claim 50, Morita discloses an integrated circuit comprising a switch network for the balancing circuitry according to claim 1 and, optionally, control circuitry for controlling the switch network (See rejection for claim 1).
Regarding independent claim 40, Morita does not explicitly disclose a balancer comprising a package containing a plurality of instances of the cell balancing circuitry according to claim 1, each instance of cell balancing circuitry being configured to couple to a different module of a battery pack for balancing cells of that module.
However, it would have been obvious to a person with ordinary skill in the art before the effective filing date to modify the balancing circuit of Morita into a plurality of instances of cell balancing circuitry to couple and perform balancing on multiple different modules of battery packs. Doing so would increase the energy capacity of the balancer of Morita and allow for the additional batteries to be balanced.
Claims 12-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Morita view of Nate, and further in view of Ferber (US 20110221398 A1).
Regarding claim 12, Morita discloses the balancing circuitry according to claim 1.
Morita does not disclose the balancing circuitry comprises voltage divider circuitry for generating the reference voltage, wherein an output node of the voltage divider circuitry is coupled to the common output node.
Ferber discloses a balancing circuitry comprising voltage divider circuitry for generating the reference voltage, wherein an output node of the voltage divider circuitry is coupled to the common output node (Fig. 8: overvoltage status output 720 and undervoltage status output 735 are generated by comparators 715 and 730 receiving voltages from the rail capacitor 230 via a resistor network and references 710 and 725. The examiner considers the rail capacitor analogous to the common node).
Both Morita and Ferber disclose circuits for balancing batteries. It would have been obvious to a person with ordinary skill in the art before the effective filing date to incorporate the reference voltage source, rail capacitor, and their arrangement in the circuit of Ferber into the circuit of Morita to finely control the voltages used for balancing the adjacent cells.
Regarding claim 13, Morita in view of Ferber discloses the balancing circuitry according to claim 12, wherein Ferber further discloses the voltage divider circuitry comprises first and second resistors (Fig. 8 shows two resistors connected to each comparator) or first and second switched capacitor circuitry.
Regarding claim 16, Morita in view of Ferber discloses the balancing circuitry according to claim 12, wherein Ferber further discloses the voltage divider circuitry is coupled in parallel with the switch network such that, in use of the balancing circuitry, the reference voltage is based on a voltage of the battery pack (Fig. 8: The circuit is arranged such that the voltage source 705, the resister network and comparators, the capacitors in the impedance balancer 200 are wired in parallel, which provides the ability to base the reference voltage on the voltage of the battery pack).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Morita in view of Nate, and further in view of De Vries (US 20140139184 A1).
Regarding claim 8, Morita discloses the balancing circuitry according to claim 3, wherein: the first tier of switching modules comprises one switching module per cell of the battery pack (Fig. 5);
Morita does not disclose balancing circuitry wherein:
the second tier of switching modules comprises one switching module for every two switching modules of the first tier of switching modules; and
the set of capacitors comprises one capacitor for every switching module of the second tier of switching modules.
De Vries discloses a balancing circuitry wherein
the second tier of switching modules comprises one switching module for every two switching modules of the first tier of switching modules (Fig. 4 has two tiers of switches S1-Sn and S2-Sn. The examiner interprets a first tier switching module as having one switch, S1-high or S1-low. ); and
the set of capacitors comprises one capacitor for every switching module of the second tier of switching modules (Each pair of high and low switches is coupled to respective capacitors C1-cell-1 to C1-cell-n and C2-cell-1 to C2-cell-n).
Morita and De Vries all disclose a circuit for battery balancing. It would have been obvious to a person with ordinary skill in the art before the effective filing date to incorporate the arrangement of switches and capacitors of the circuit in De Vries into the circuit of Morita, to manage current to flow more directly from a cell with higher charge level to a cell with a lower charge level (¶0023).
Claims 17 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Morita in view of Nate and Ferber, and further in view of Posamentier (US 20120194133 A1).
Regarding claim 17, Morita discloses the balancing circuitry according to claim 1.
Morita does not explicitly disclose wherein the common node is coupled to a DC-DC converter, wherein the DC-DC converter is configured to supply a fixed or variable voltage to the common node.
Ferber discloses a common node (Fig. 8: rail capacitor 230) coupled to a power source (voltage supply 705) configured to charge the rail capacitor 230 to a desired level (¶0058).
Both Morita and Ferber disclose a balancing circuit. It would have been obvious to a person with ordinary skill in the art before the effective filing date to incorporate the power source connected to the common node in the circuit of Ferber into the circuit of Morita to provide direct control over the reference voltage and its use to balance the battery cells.
Morita in view of Ferber does not disclose that the power source is a DC-to-DC converter.
Posamentier discloses a balancing circuit 104 that includes a DC-to-DC converter 202 (Fig. 2 and ¶0020).
Morita modified and Posamentier disclose balancing circuits for balancing cells. It would have been obvious to a person with ordinary skill in the art before the effective filing date to substitute the DC-DC converter of Posamentier into Morita modified to provide finer voltage control and efficient energy transfer to the balance circuit.
Regarding claim 22, Morita in view of Ferber and Posamentier discloses the balancing circuitry according to claim 17, wherein the DC-DC converter is operable to adjust the voltage supplied to the common node between the end of the first phase and the beginning of the second phase.
(Adjusting the voltage supplied to the common node when phases transition falls within the scope of Morita and Posamentier)
Claim 53 is rejected under 35 U.S.C. 103 as being unpatentable over Morita in view of Nate, and further in view of Lin (US 20140097787 A1).
Regarding independent claim 53, Morita discloses a host device comprising the balancing circuitry of claim 1,
Morita does not disclose wherein the host device comprises an electric vehicle, an electric bicycle, an electric scooter, a cordless power tool, a computing device, a laptop, netbook, notebook or tablet computer, a portable battery powered device, a mobile telephone or an accessory device for such a host device.
Lin discloses a host device (¶0006: electric vehicles (EV)) comprising balance circuitry (Battery management system).
Both Lin and Morita discloses systems for balancing batteries. It would have been obvious to a person with ordinary skill in the art before the effective filing date to substitute the circuitry of Morita into the EV of Lin for the purpose of balancing cells in an EV.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200014219 A1 discloses tiers of switches connecting cells in series to capacitors (Fig. 4).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryu-Sung Peter Weinmann whose telephone number is (703)756-5964. The examiner can normally be reached Monday-Friday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julian Huffman, can be reached at (571) 272-2147. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Ryu-Sung P. Weinmann/Examiner, Art Unit 2859 May 6, 2026
/JULIAN D HUFFMAN/Supervisory Patent Examiner, Art Unit 2859
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