DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claim 1 has been amended by Applicant. No claims have been cancelled or added. Claims 1-4 are currently pending.
Response to Arguments
Claim Rejections under 35 U.S.C. 103
The rejection of claims 1-4, under 35 U.S.C. 103 has been withdrawn in view of Applicant’s amendment to independent claim 1. However, upon further consideration and in view of said amendment a new grounds of rejection has been made herein.
Applicant's arguments filed 10/27/2025 have been fully considered but they are not persuasive.
Applicant argues (in page 5 of Applicant’s remarks) that the combination of Shin in view of Tran does not distinctly disclose the limitation “…a plurality of N/B many level cell (MLC) …wherein…N is the number of bits in the weight vector or synapse (Yi)”.
Examiner respectfully disagrees with Applicant’s argument above. As set forth in the Non-Final Rejection dated 3/12/2025, the combination of Shin in view of Tran was shown to teach …a plurality of N/B many level cell (MLC)… …wherein…N is the number of bits in the weight vector or synapse (Yi)… . To this effect, Tran, Paragraph [0062] was shown to teach FIG. 9 depicts neuron VMM 900, which is particularly suited for memory cells of the type shown in FIG. 2, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM 900 comprises a memory array 903 of non-volatile memory cells, reference array 901, and reference array 902.; Tran, Paragraph [0063], further teaches memory array 903 serves two purposes. First, it stores the weights that will be used by the VMM 900. Second, memory array 903 effectively multiplies the inputs(current inputs provided in terminals BLR0-3; reference arrays 901 and 902 convert these current inputs into the input voltages to supply to wordlines WL0-3) by the weights stored in the memory array to produce the output; Tran, Paragraph [0072] teaches flash memory cells (i.e., reading on MLC); Tran, Paragraph [0079] teaches bit lines forming a neuron – reading on N, as claimed; As further noted in the rejection Shin had already been shown to teach many level cells (MLC) at Paragraph [0064] and Figs. 7B and 7C, and further teaches “B” at Paragraphs [0056] and [0065].
It is further noted that the combination of Shin in view of Tran and Lin was further shown to teach the limitation storing the N digital bits…in order of significance from LSB to MSB. To that effect, Lin, Paragraph [0027] was shown to teach the first embodiment stated above may also be applied to any kind of MLC non-volatile memory. Taking a 4LC non-volatile memory, where any storage cell stores 2 bits, as an example. The page jumper only selects the LSB page formed from the least significant bit (LSB) of the 2 bits to be stored in one temporary data storage block, and selects the MSB page formed from the most significant bit (MSB) of the 2 bits to be stored in the other temporary data storage block.
Applicant’s arguments with respect to teaching the amended limitation in claim 1 reciting “wherein N/B is an integer representing the exact number of many-level-cell(MLC) non-volatile memory cells required for each synapse, and wherein each of the N/B MLC cells stores exactly B consecutive bits of the N-bit weight vector in order of significance from LSB to MSB”, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
As stated above, the rejection of claims 1-4 (as amended), under 35 U.S.C. 103 has been withdrawn in view of Applicants amendments to independent claim 1, and a new grounds of rejection has been made under 35 U.S.C. 103 over the combination of Shin, Tran, and Lin in further view of Mittal. (See rejection of claim 1 (as amended) under 35 U.S.C. 103, as stated below.)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 4 (as amended) are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 20140380129 A1) in view of Tran et al. (US 20190287631 A1), Lin (US 20120311243 A1), and Mittal, “A survey of ReRAM-Based Architectures for Processing -in-Memory and Neural Networks (30 April 2018)
Regarding claim 1, Shin teaches a method for operating a set of many-level-cell (MLC) non-volatile memory cells in a neuron (Note: “for operating …” understood as intended use language not limiting the structure of the claim. See MPEP 2111.02(II)) comprising:
providing a plurality of … many level cell (MLC) non-volatile memory cells for each synapse (Yi) connected to a bit line (Shin, Paragraph [0056], teaches referring to FIGS. 4 and 5, when the memory cell array 120 of FIG. 4 is assumed to be a NAND flash memory, wherein each of the blocks BLK0 to BLKa-1 includes two or more strings STR of memory cells MCEL are connected in series in the direction of bit lines BL0 to BLd-1.; See Figs. 4 and 5) wherein the plurality of non-volatile memory cells are ordered from a most significant bits cell (MSB's) to a least significant bits cell (LSB's) (Shin, Figures 3 and 4 teach non-volatile cells ordered from MSB to LSB) …, and B is the bit storage capacity per non-volatile memory cell (Shin, Paragraph [0064] teaches the non-volatile memory system 100 according to an embodiment of the inventive concept may include a non-volatile memory device MEM in which two or more bits of data is set in each threshold voltage range, that is, each threshold voltage distribution, as illustrated in FIG. 7B or 7C. A NAND flash memory having this structure is referred to as a multi-level cell (MLC) NAND flash memory. Two or more bits of data may be programmed in each memory cell MCEL of the MLC NAND flash memory [i.e., reading on N is the number of bits]; Shin, Paragraph [0065] teaches a NAND flash memory in which 3-bit data is programmed in a memory cell may be referred to as a triple-level cell (TLC) NAND flash memory [i.e., here the memory cell is being taught as having a storage capacity of 3 bits, hence teaches “B”]. However, for the convenience of description, hereinafter, NAND flash memories in which two or more bits of data is programmed in a memory cell will be collectively referred to as an MLC NAND flash memory [i.e., here the memory cell is being taught as having a storage capacity of 2 or more bits, hence teaches “B”]. In the MLC NAND flash memory, a hard read voltage may be set as three or more voltage levels in order to identify four or more threshold voltage distributions.)) …;
providing a set of weight vectors, wherein each weight vector is stored across many MSB to LSB non-volatile memory cells … (Shin, Paragraph [0064] teaches the non-volatile memory system 100 according to an embodiment of the inventive concept may include a non-volatile memory device MEM in which two or more bits of data is set in each threshold voltage range, that is, each threshold voltage distribution, as illustrated in FIG. 7B or 7C. A NAND flash memory having this structure is referred to as a multi-level cell (MLC) NAND flash memory. Two or more bits of data may be programmed in each memory cell MCEL of the MLC NAND flash memory. In the MLC NAND flash memory, two or more pages may be set at each word line of FIG. 5.; Shin, Paragraph [0075] further teaches the non-volatile memory system may allocate a weight of strong 1 to the data (bit) that is read from the memory cell having a threshold voltage included in the period in which the reliability data RDTA is identified as “11”. The non-volatile memory system may allocate a weight of weak 1 to the data (bit) that is read from the memory cell having a threshold voltage included in this period in which the reliability data RDTA is identified as “10” [Note: Par. [0064] and [0075] understood to read on providing a set of weight vectors, as claimed; Shin, Figures 3 and 4 teach the limitation across many MSB to LSB non-volatile memory cells); and
storing the N digital bits of the weight vector, such that B bits are stored in each non-volatile memory cell,… (Shin, Paragraph [0075] teaches the non-volatile memory system may allocate [i.e., store] a weight of strong 1 to the data (bit) that is read from the memory cell having a threshold voltage included in the period in which the reliability data RDTA is identified as “11”. The non-volatile memory system may allocate [i.e., store] a weight of weak 1 to the data (bit) that is read from the memory cell having a threshold voltage included in this period in which the reliability data RDTA is identified as “10”; Shin, Paragraph [0065] teaches a NAND flash memory in which 3-bit data is programmed [i.e., stored] in a memory cell may be referred to as a triple-level cell (TLC) NAND flash memory [NOTE: here the memory cell is being taught as having a storage capacity of 3 bits, hence teaches “B” programmed [stored] in a NAND flash memory cell]. However, for the convenience of description, hereinafter, NAND flash memories in which two or more bits of data is programmed in a memory cell will be collectively referred to as an MLC NAND flash memory [NOTE: here the memory cell is being taught as having a storage capacity of 2 or more bits, hence teaches “B” programmed [stored] in a NAND flash memory cell].
However, Shin does not distinctly disclose:
…a plurality of N/B many level cell (MLC)… …wherein…N is the number of bits in the weight vector or synapse (Yi)…
…connected to a bit line forming a neuron…
providing an input vector (Xi) for each synapse (Yi), wherein each input vector (Xi) is translated into an equivalent electrical signal;
providing an electrical signal to each synapse sub-circuit;
…weight vector assigned to each synapse (Yi)…
storing the N digital bits…in order of significance from LSB to MSB
and wherein N/B is an integer representing the exact number of many-level-cell(MLC) non-volatile memory cells required for each synapse, and wherein each of the N/B MLC cells stores exactly B consecutive bits of the N-bit weight vector in order of significance from LSB to MSB.
Nevertheless, the combination of Shin in view of Tran teaches:
…a plurality of N/B many level cell (MLC)… …wherein…N is the number of bits in the weight vector or synapse (Yi)… (Tran, Paragraph [0062] teaches FIG. 9 depicts neuron VMM 900, which is particularly suited for memory cells of the type shown in FIG. 2, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM 900 comprises a memory array 903 of non-volatile memory cells, reference array 901, and reference array 902.; Tran, Paragraph [0063], further teaches memory array 903 serves two purposes. First, it stores the weights that will be used by the VMM 900. Second, memory array 903 effectively multiplies the inputs(current inputs provided in terminals BLR0-3; reference arrays 901 and 902 convert these current inputs into the input voltages to supply to wordlines WL0-3) by the weights stored in the memory array to produce the output; Tran, Paragraph [0072] teaches flash memory cells (i.e., reading on MLC); Tran, Paragraph [0079] teaches bit lines forming a neuron – reading on N, as claimed; [Note: As previously stated, Shin teaches many level cells (MLC) at Paragraph [0064] and Figs. 7B and 7C, and further teaches “B” at Paragraphs [0056] and [0065]))
…connected to a bit line forming a neuron… (Tran, Paragraph [0079] teaches a sourceline or a bitline can be used as the neuron output (current summation output))
providing an input vector (Xi) for each synapse (Yi), wherein each input vector (Xi) is translated into an equivalent electrical signal (Tran, Paragraph [0006] teaches the neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells…; Tran, Paragraph [0062] teaches FIG. 9 depicts neuron VMM 900, which is particularly suited for memory cells of the type shown in FIG. 2, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM 900 comprises a memory array 903 of non-volatile memory cells, reference array 901, and reference array 902. Reference arrays 901 and 902 serve to convert current inputs flowing into terminals BLR0-3 into voltage inputs WL0-3.; Tran, Paragraph [0063] further teaches memory array 903 serves two purposes. First, it stores the weights that will be used by the VMM 900. Second, memory array 903 effectively multiplies the inputs (current inputs provided in terminals BLR0-3; reference arrays 901 and 902 convert these current inputs into the input voltages to supply to wordlines WL0-3) by the weights stored in the memory array to produce the output, which will be the input to the next layer or input to the final layer.;
providing an electrical signal to each synapse sub-circuit (Tran, Paragraph [0066] teaches FIG. 12 depicts operating voltages for VMM 1100. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program.; Tran, Paragraph [0067] further teaches FIG. 13 depicts neuron VMM 1300, which is particularly suited for memory cells of the type shown in FIG. 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM 1300 comprises a memory array 1301 of non-volatile memory cells, reference array 1302 (providing reference converting input current into input voltage for even rows), and reference array 1303 (providing reference converting input current into input voltage for odd rows).
…MLC non-volatile cells assigned to each synapse (Yi)… (Tran, Paragraph [0006] teaches the neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells…; Figure 9 teaches non-volatile memory cells; [Note: Shin has been shown to teach MLC non-volatile memory cells, as previously stated].)
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified the memory system and method, as taught by Shin, with the analog non-volatile memory for deep neural networks, as taught by Tran, in order to overcome drawbacks in the prior art by reducing costs and consuming less energy. (Tran, Paragraph [0005])
However, the combination of Shin in view of Tran does not distinctly disclose: storing the N digital bits…in order of significance from LSB to MSB
, and wherein N/B is an integer representing the exact number of many-level-cell(MLC) non-volatile memory cells required for each synapse, and wherein each of the N/B MLC cells stores exactly B consecutive bits of the N-bit weight vector in order of significance from LSB to MSB.
Nevertheless, Lin teaches storing the N digital bits…in order of significance from LSB to MSB (Lin, Paragraph [0027] teaches the first embodiment stated above may also be applied to any kind of MLC non-volatile memory. Taking a 4LC non-volatile memory, where any storage cell stores 2 bits, as an example. The page jumper only selects the LSB page formed from the least significant bit (LSB) of the 2 bits to be stored in one temporary data storage block, and selects the MSB page formed from the most significant bit (MSB) of the 2 bits to be stored in the other temporary data storage block.).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to have modified the memory system and method, as taught by Shin and Tran, to further include the storing of bits in from LSB to MSB, as taught by Lin, in order to select the fastest programming speed and an order bit page or an LSB page with the best reliability, and render the normally used data storage block to only use the LSB page, in order to reduce the frequency of erasing of the data storage block, thereby the life of use of the data storage block can be elongated, and the life of use of the multi-level cell type non-volatile memory can be elongated too. (Lin, Paragraph [0034])
However, the combination does not distinctly disclose:
wherein N/B is an integer representing the exact number of many-level-cell(MLC) non-volatile memory cells required for each synapse, and wherein each of the N/B MLC cells stores exactly B consecutive bits of the N-bit weight vector in order of significance from LSB to MSB.
Nevertheless, the combination in view of Mittal teaches wherein N/B is an integer representing the exact number of many-level-cell(MLC) non-volatile memory cells required for each synapse, and wherein each of the N/B MLC cells stores exactly B consecutive bits of the N-bit weight vector in order of significance from LSB to MSB (Mittal, pg. 83 teaches a 16-bit synaptic weight is stored in 16/w w-bits cells of a single row (e.g., w = 2) [Note: If we were to divide the 16 bit weight among cells that each hold 2 bits, then we divide into exactly 16/2 = 8 cells; Note: Shin has already been shown to teach providing a plurality of … many level cell (MLC) non-volatile memory cells for each synapse (Yi) connected to a bit line and Lin has already been shown to teach in order of significance from LSB to MSB]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to have modified the memory system and method, as taught by Shin in view of Tran and Li, to further include the memory architectures for NN inference, as taught by Mittal, as it would have been obvious that, if we’re going to divide the 16 bit weight among cells that each hold 2 bits, then we divide into exactly 16/2 = 8 cells, no matter what kind of memory we are using. (See MPEP 2141 (III) - Examples of rationales that may support a conclusion of obviousness include: (F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;)
Regarding claim 4, the combination of Shin in view of Tran, Lin, and Mittal teaches all of the limitations of claim 1, and the combination further teaches wherein the non-volatile memory cell is a flash memory cell (Shin, Paragraph [0036] further teaches in certain embodiments of the inventive concept, the non-volatile memory device of FIG. 2 may be a NAND flash memory, and will include one or more memory cell arrays 120.; Paragraph [0012] teaches Fig. 4 is a diagram illustrating an example of a structure of a memory cell array included in a flash memory according to an embodiment of the inventive concept;).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Tran, Lin, and Mittal, as applied to claim 1, and further in view of Mappouras et al., “Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 37 (July 18, 2018)
Regarding claim 2, the combination of Shin in view of Tran, Lin, and Mittal teaches all of the limitations of claim 1, and the combination further teaches wherein the step of providing an electrical signal to each synapse sub-circuit further comprises: providing an input current IDACi to each synapse sub-circuit (Tran, Paragraph [0065] teaches VMM 1100 comprises a memory array 1103 of non-volatile memory cells, reference array 1101, and reference array 1102. VMM 1100 is similar to VMM 900 except that in VMM 1100 the word lines run in the vertical direction. There are two reference arrays 1101 (at the top, which provides a reference converting input current into voltage for the even rows) and 1102 (at the bottom, which provides a reference converting input current into voltage for the odd rows).),…
Motivation to combine same as stated for claim 1.
However, the combination does not distinctly disclose:
from (20*k)*IDAci, (21*k)*lDACi , (22*k )*IDACi wherein k = log2 (L), wherein L is the number of levels possible per non-volatile memory cell.
Nevertheless, Mappouras teaches from (20*k)*IDAci, (21*k)*lDACi , (22*k )*IDACi wherein k = log2 (L), wherein L is the number of levels possible per non-volatile memory cell (Mappouras, pg. 2463, Section II, teaches flash memory is organized in blocks, and each block contains some number of pages (e.g., 256 pages/block). Each page contains some number of flash cells (e.g., 8192 cells/page) that are used to store bits…Flash cells can have more than two levels, and 4-level cells (MLCs) are most common. In uncoded usage, a cell with L levels can hold log2(L) bits [i.e., teaching k=log2(L), as claimed].)
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to have modified the memory system and method, as taught by Shin in view of Tran, Lin, and Mittal to further include the flash memory teachings in uncoded usage, as taught by Mappouras, as flash memory provide the benefits of low latency, high bandwidth, and high density alternative to hard disk drives. (Mappouras, pg. 2463, Section II)
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Tran, Lin, and Mittal, as applied to claim 1, and further in view of Bhattacharyya (US 20070045711 A1) and Mappouras et al.
Regarding claim 3, the combination of Shin in view of Tran, Lin, and Mittal teaches all of the limitations of claim 1, however the combination does not distinctly disclose wherein the step of providing an electrical signal to each synapse sub-circuit further comprises: providing an input pulse TPULSEi to each synapse sub-circuit, from (20*k)*TPULSEi, (21*k)*TPULSEi , (22*k )*TPULSEi, and wherein k = log2 (L), wherein L is the number of threshold voltage levels or resistance levels possible per non-volatile memory cell.
Nevertheless, Bhattacharyya teaches wherein the step of providing an electrical signal to each synapse sub-circuit further comprises: providing an input pulse TPULSEi to each synapse sub-circuit, , (Bhattacharyya, Paragraph [0070] teaches clock pulses as triggers for data access.)
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to have modified the memory system and method, as taught by Shin in view of Tran, Lin, and Mittal to further include the high performance multi-level non-volatile memory, taught by Bhattacharyya, in order to overcome the drawbacks of high programming voltage requirements. (Bhattacharyya, Paragraph [0005]).
However, the combination of Shin in view of Tran, Lin, Mittal and Bhattacharyya does not distinctly disclose:
from (20*k)*TPULSEi, (21*k)*TPULSEi , (22*k )*TPULSEi, wherein k = log2 (L), wherein L is the number of threshold voltage levels or resistance levels possible per non-volatile memory cell.
Nevertheless, Mappouras teaches from (20*k)*IDAci, (21*k)*lDACi , (22*k )*IDACi wherein k = log2 (L), wherein L is the number of levels possible per non-volatile memory cell (Mappouras, pg. 2463, Section II, teaches flash memory is organized in blocks, and each block contains some number of pages (e.g., 256 pages/block). Each page contains some number of flash cells (e.g., 8192 cells/page) that are used to store bits…Flash cells can have more than two levels, and 4-level cells (MLCs) are most common. In uncoded usage, a cell with L levels can hold log2(L) bits [i.e., teaching k=log2(L), as claimed].)
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to have modified the memory system and method, as taught by Shin, Tran, Lin, Mittal and Bhattacharyya, to further include the flash memory teachings in uncoded usage, as taught by Mappouras, as flash memory provide the benefits of low latency, high bandwidth, and high density alternative to hard disk drives. (Mappouras, pg. 2463, Section II)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/B.R.B./Examiner, Art Unit 2146
/USMAAN SAEED/Supervisory Patent Examiner, Art Unit 2146