DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because do not include the following reference sign mentioned in the description: figure 2 multiplier module 210.
Furthermore, the drawings must show every feature of the invention specified in the claims. Therefore removing a sign bit with a predetermined length from an output of a result of the accumulation must be shown is in claim 10, and claim 21 or the feature canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities. Paragraph [0104], last sentence appears to be a duplicate of the immediately preceding sentence.
Appropriate correction is required.
Claim Objections
Claims 6-7 are objected to because of the following informalities. Claim 6 line three appears to have a typographical error in the middle of the word “the” immediately preceding the word “previous”. Claim 7 inherits the same deficiency as claim 6 based on dependence. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10,15, 23-25, and 26-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-10, 23-25, and 26-27 do not provide a discernable boundary as to what part of the processor performs the claim functions, rendering the bounds of the claim unclear. With the exception of the one or more multipliers to perform multiplying, the functions which the processor is configured to carry out do not follow from structure recited in the claim, rendering it unclear whether the function requires some other structure or is simply a result of operating the processor in a certain manner. Therefore, one of ordinary skill in the art would not be able to draw a clear boundary between what is and is not covered by the claims. See MPEP 2173.05(g).
Claim 4 line 2, and claim 15 line 2 recite “adding the exponent value”. It is unclear what is meant by adding a single exponent value. For purposes of examination, Examiner interprets as multiple values of the exponent value being added.
Claim 26 line 3 recites “multiply the plurality of data”. This limitation lacks antecedent basis. It is unclear whether the plurality of data is the same plurality of data subsequently recited. For purposes of examination, Examiner interprets as “multiply a plurality of data”. Claim 27 inherits the same deficiency as claim 26 based on dependence.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10, and 12-27 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Regarding claim 1, under the Alice framework Step 1, the claim falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process, machine, manufacture or a composition of matter.
Under the Alice framework Step 2A prong 1, the claim recites mathematical concepts of mathematical calculations and mathematical relationships for a multiply-accumulate calculation. Specifically, claim 1 recites the following mathematical calculations and mathematical relationships:
multiply the plurality of data;
perform a first alignment on a result of the multiplication based on an exponent value of the plurality of data;
add a result of the first alignment; and
perform a second alignment on a result of the addition based on the exponent value and an operation result
Under the Alice framework Step 2A prong 2 analysis, claim 1 recites the following additional elements: an apparatus with multi-format data support, the apparatus comprising: a receiver configured to receive a plurality of data corresponding to a plurality of data formats; one or more processors, one or more multipliers, a previous cycle of an operation. These elements are recited at a very high level of generality, wherein mathematical calculations and mathematical relationships are merely “applied” in one or more processors, and wherein generically recited multipliers are claimed merely to perform the mathematical operation: multipliers to multiply. Furthermore a receiver configured to receive a plurality of data corresponding to a plurality of data formats, a multiplier to multiply, and an operation with respect to a previous cycle merely comprise and insignificant extra solution activity. For these reasons, claim 1 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, claim 1 considered individually and as an ordered combination does not include additional elements that are sufficient to amount to significantly more than the abstract idea. As stated in the Step 2A prong 2 analysis, the claim does no more than merely generally link the use of the mathematical concepts in processors in a manner that merely recites “apply it”, and uses a generically recited multiplier to multiply. Furthermore a receiver configured to receive a plurality of data corresponding to a plurality of data formats, a multiplier to multiply, and an operation with respect to a previous cycle comprise well understood, routine, and conventional activity. See D.A. Patterson et al., Computer Organization and Design: the Hardware/Software Interface, Elsevier Science & Technology, 2007 (hereinafter “Patterson”), fig 1.5, which discloses an input (receiver) configured to receive data in multiple formats as one of the five classic components of a computer. See also p. 177-181, 189, fig 3.5 which shows a arithmetic pipeline including a multiplier performing operations by cycle. For these reasons claim 1 does not amount to significantly more than the abstract idea.
Claims 2-10 are rejected for at least the reasons set forth with respect to claim 1. Claims 2-10 merely further mathematically limit the mathematical concepts of claim 1. Claims 2-10 contain no further additional elements beyond those recited in claim 1 that would require further analysis under step 2A prong 2 and step 2B.
Claim 12 is directed to a method that would be practiced by the apparatus as in claim 1. All steps performed by the method as in claim 12 is performed by the apparatus as in claim 1 as configured. The claim 1 analysis applies equally to claim 12.
Claims 13-21 are rejected for at least the reasons set forth with respect to claim 12. Claims 13-21 merely further mathematically limit the mathematical concepts of claim 12. Claims 13-21 contain no further additional elements beyond those recited in claim 12 that would require further analysis under step 2A prong 2 and step 2B.
Claim 22 is directed to a computer-readable storage medium storing instructions that when executed by one or more processors, configure the one or more processors to perform the method as in claim 12. The claim 12 analysis applies equally to claim 22.
Regarding claim 23, under the Alice framework Step 1, the claim falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process, machine, manufacture or a composition of matter.
Under the Alice framework Step 2A prong 1, the claim recites mathematical concepts of mathematical calculations and mathematical relationships for a multiply-accumulate calculation. Specifically, claim 23 recites the following mathematical calculations and mathematical relationships:
multiply a plurality of data corresponding to a plurality of formats;
perform a first alignment on a result of the multiplication based on a difference between a maximum exponent value among exponent values of the plurality of data and a sum of remaining exponent values;
add a result of the first alignment; and
perform a second alignment on a result of the addition based on a difference between the maximum exponent value and an exponent value of an operation result
Under the Alice framework Step 2A prong 2 analysis, claim 1 recites the following additional elements: an apparatus with multi-format data support, the apparatus comprising: one or more processors, one or more multipliers, a previous cycle of an operation. These elements are recited at a very high level of generality, wherein mathematical calculations and mathematical relationships are merely “applied” in one or more processors, and wherein generically recited multipliers are claimed merely to perform the mathematical operation: multipliers to multiply. Furthermore a multiplier to multiply, and an operation with respect to a previous cycle merely comprise and insignificant extra solution activity. For these reasons, claim 23 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, claim 23 considered individually and as an ordered combination does not include additional elements that are sufficient to amount to significantly more than the abstract idea. As stated in the Step 2A prong 2 analysis, the claim does no more than merely generally link the use of the mathematical concepts in processors in a manner that merely recites “apply it”, and uses a generically recited multiplier to multiply. Furthermore, a multiplier to multiply and an operation with respect to a previous cycle comprise well understood, routine, and conventional activity. See D.A. Patterson, p 177-181, 189, fig 3.5 which shows a arithmetic pipeline including a multiplier performing operations by cycle. For these reasons claim 23 does not amount to significantly more than the abstract idea.
Claims 24-25 are rejected for at least the reasons set forth with respect to claim 23. Claims 24-25 merely further mathematically limit the mathematical concepts of claim 23. Claims 24-25 contain no further additional elements beyond those recited in claim 23 that would require further analysis under step 2A prong 2 and step 2B.
Regarding claim 26, under the Alice framework Step 1, the claim falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process, machine, manufacture or a composition of matter.
Under the Alice framework Step 2A prong 1, the claim recites mathematical concepts of mathematical calculations and mathematical relationships for a multiply-accumulate calculation. Specifically, claim 26 recites the following mathematical calculations and mathematical relationships:
multiply a plurality of data based on a plurality of formats;
perform a first alignment on a result of the multiplication based on an exponent value of the plurality of data;
add a result of the first alignment; and
perform a second alignment on a result of the addition based on the exponent value of an operation result
Under the Alice framework Step 2A prong 2 analysis, claim 26 recites the following additional elements: an apparatus with multi-format data support, the apparatus comprising: one or more processors, routing data of a plurality of data corresponding to a plurality of data formats to one or more multipliers of a multiplier-accumulator (MAC) array, a previous cycle of an operation. These elements are recited at a very high level of generality, wherein mathematical calculations and mathematical relationships are merely “applied” in one or more processors, and wherein generically recited multipliers of a MAC array are claimed merely to perform the mathematical operation: multipliers to multiply. Furthermore a multiplier to multiply of a MAC array, routing data, and an operation with respect to a previous cycle merely comprise and insignificant extra solution activity. For these reasons, claim 26 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, claim 26 considered individually and as an ordered combination does not include additional elements that are sufficient to amount to significantly more than the abstract idea. As stated in the Step 2A prong 2 analysis, the claim does no more than merely generally link the use of the mathematical concepts in processors in a manner that merely recites “apply it”, and uses a generically recited multiplier to multiply in a MAC array. Furthermore, a multiplier to multiply in a MAC array and an operation with respect to a previous cycle comprise well understood, routine, and conventional activity. See D.A. Patterson, fig 1.5, which discloses an input (receiver) configured to receive route data as one of the five classic components of a computer. See also p. 177-181, 189, fig 3.5 which shows a arithmetic pipeline including a MAC including a multiplier performing operations by cycle. For these reasons claim 23 does not amount to significantly more than the abstract idea.
Claim 27 is rejected for at least the reasons set forth with respect to claim 26. Claims 27 merely further mathematically limit the mathematical concepts of claim 26. Claims 24-25 contain no further additional elements beyond those recited in claim 23 that would require further analysis under step 2A prong 2 and step 2B.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by H. Abdel-Aziz et al., Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators, arXiv:2101.11748v1 [cs.AR], 27 Jan 2021 (hereinafter “Abdel-Aziz”).
Regarding claim 1, Abdel-Aziz teaches the following:
a receiver configured to receive a plurality of data corresponding to a plurality of data formats (section 2 second paragraph mixed precision IPU allows INT4, signed/unsigned and larger precision, fig 1, input lines to the IPU for receiver); and
one or more processors (fig 1 multiplier, shift, adder, accumulation logic pipeline for one or more processors) configured to:
multiply the plurality of data using one or more multipliers (section 2, 5bx5b sign multipliers, fig 1 multipliers);
perform a first alignment on a result of the multiplication based on an exponent value of the plurality of data (section 2.2 local alignment, fig 1 r-shift following multipliers, wherein r-shift is controlled by exponent handling unit);
add a result of the first alignment (section 2.1, fig 1 adder tree); and
perform a second alignment on a result of the addition based on the exponent value and an operation result of a previous cycle (section 2.2 the accumulator operations, accumulation logic, including output from accumulation logic fed back into second r-shift inside accumulation logic for second alignment based on the exponent value and an operation result of a previous cycle).
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis, Abdel-Aziz teaches the following:
wherein, for the multiplying, the one or more processors are configured to:
multiply a first bit input and a second bit input included in the plurality of data (section 2 second paragraph, nibble iterations, first iteration for multiply a first bit input and a second bit input included in the plurality of data);
convert a sign of a result of the multiplication of the first bit input and the second bit input (section 2 second paragraph, signed multiplication); and
combine the result of the multiplication of the first bit input and the second bit input with the converted sign to generate the result of the multiplying of the plurality of data (fig 1 output of multiplier thru r0shift and adder tree for combing the result).
Regarding claim 3, in addition to the teachings addressed in the claim 1 analysis, Abdel-Aziz teaches the following:
wherein, for the multiplying, the one or more processors are configured to multiply a plurality of first bit inputs of the plurality of data(section 2 second paragraph, nibble iterations).
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, Abdel-Aziz teaches the following:
wherein the one or more processors (fig 3, fig 5 Exponent Handling Unit within processor apparatus) are configured to:
add the exponent value (section 2.2.local alignment (1) element-wise summation of the operands unbiased exponents, section 3.2 3rd paragraph, appendix B pseudocode line 4);
obtain a maximum exponent value based on the exponent value (section 2.2. local alignment (2) computing the maximum of the product exponents, section 3.2 3rd paragraph, appendix B pseudocode line 5);
determine a sum of remaining exponent values (section 2.2. local alignment (3) computing all the product exponents with respect to the maximum, section 3.2 3rd paragraph, appendix B pseudocode line 4 ); and
determine a difference between the maximum exponent value and the sum (section 2.2 local alignment (3) computing the difference between all the product exponents and the maximum exponent, section 3.2 3rd paragraph, appendix B pseudocode line 9).
Regarding claim 5, in addition to the teachings addressed in the claim 1 analysis, Abdel-Aziz teaches the following:
wherein, for the performing of the first alignment, the one or more processors are configured to shift the result of the multiplication based on a difference between a maximum exponent value obtained based on the exponent value and a sum of remaining exponent values (section 2.2. local alignment. alignment shift amount as the different between the product exponent and the maximum exponent, fig 1).
Regarding claim 6, in addition to the teachings addressed in the claim 2 analysis, Abdel-Aziz teaches the following:
wherein, for the performing of the second alignment, the one or more processors are configured to shift the result of the addition based on a maximum exponent value obtained based on the exponent value and the operation result of the previous cycle (fig 1 r-shift in accumulation logic shifting accumulator result based on max exp in).
Regarding claim 7, in addition to the teachings addressed in the claim 6 analysis, Abdel-Aziz teaches the following:
wherein, for the shifting of the result of the addition, the one or more processors are configured to shift the result of the addition based on a difference between the maximum exponent value and an exponent value stored according to the operation result of the previous cycle section 2.2 the accumulator operations, accumulation logic, including output from accumulation logic fed back into second r-shift inside accumulation logic for second alignment based on the exponent value and an operation result of a previous cycle (section 2.2 the accumulator operations, accumulation logic, including output from accumulation logic fed back into second r-shift inside accumulation logic for second alignment based on the max exponent, exponent value and an operation result of a previous cycle).
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis, Abdel-Aziz teaches the following:
wherein, for the performing of the second alignment (figure 1 accumulation logic), the one or more processors are configured to:
extend a sign bit of the plurality of data based on a predetermined radix point (fig 1 right top, extended sign bits into swap unit, section 2.2.the accumulator operations); and
add the extended sign bit to the exponent value (fig 1 accumulator adding extended sign bits to exponent value from exponent handling unit, section 2.2. the accumulator operations first paragraph, accumulators keep two values including exponent).
Regarding claim 9, in addition to the teachings addressed in the claim 1 analysis, Abdel-Aziz teaches the following:
wherein the one or more processors are configured to accumulate a result of the second alignment (fig 1 accumulator following r-shift, section 2.2.accumulator operations).
Regarding claim 10, in addition to the teachings addressed in the claim 9 analysis, Abdel-Aziz teaches the following:
wherein the one or more processors are configured to:
remove a sign bit with a predetermined length from an output of a result of the accumulation (fig 1 extended sign bits removed from the accumulation, input to accumulation); and
perform normalization on the output in which the sign bit is removed (section 2.2. the accumulator operations, first paragraph, the result of the accumulator is normalized, before being reformatted (to the signed representation).
Regarding claim 11, in addition to the teachings addressed in the claim 1 analysis, Abdel-Aziz teaches the following:
wherein the one or more processors comprises:
one or more multipliers configured to perform the multiplying of the plurality of data (figure 1 multipliers);
a first aligner configured to perform the first alignment on a result of the multiplication (fig 1 r-shifts following multipliers);
an adder tree configured to perform the adding of the result of the first alignment (fig 1 adder tree); and
a second aligner configured to perform the second alignment on the result of the addition (fig 1 r-shift in accumulator logic).
Claims 12-16, and 19-21 are directed to a method that would be practiced by the apparatus as in claims 1-5, and 8-10 respectively. All steps performed by the method as in claims 12-16, and 19-21 performed by the apparatus as in claims 1-5, and 8-10 respectively as configured. The claim 1-5, and 8-10 analysis applies equally to claims 12-16, and 19-21 respectively.
Claim 22 is directed to a computer-readable storage medium storing instructions that when executed by one or more processors, configure the one or more processors to perform the method as in claim 12. The claim 12 analysis applies equally to claim 22.
Regarding claim 23, Abdel-Aziz teaches the following:
one or more processors (fig 1 multiplier, shift, adder, accumulation logic pipeline for one or more processors) configured to:
multiply the plurality of data corresponding to a plurality of data formats using one or more multipliers (section 2, second paragraph mixed precision IPU allows INT4, signed/unsigned and larger precision, 5bx5b sign multipliers, fig 1 multipliers);
perform a first alignment on a result of the multiplication based on a difference between a maximum exponent value among exponent values of the plurality of data and a sum of remaining exponent values (section 2.2 local alignment, fig 1 r-shift following multipliers, wherein r-shift is controlled by exponent handling unit, section 2.2 local alignment (3) computing the difference between all the product exponents and the maximum exponent, section 3.2 3rd paragraph, appendix B pseudocode line 4, 9);
add a result of the first alignment (section 2.1, fig 1 adder tree); and
perform a second alignment on a result of the addition based on the difference between the maximum exponent value and an operation result of a previous cycle (section 2.2 the accumulator operations, accumulation logic, including output from accumulation logic fed back into second r-shift inside accumulation logic for second alignment based on the exponent value and an operation result of a previous cycle, max exponent into the accumulation logic).
Regarding claim 17, in addition to the teachings addressed in the claim 12 analysis, Abdel-Aziz teaches the following:
wherein, for the performing of the second alignment comprises shifting the result of the addition based on a maximum exponent value obtained based on the exponent value and the operation result of the previous cycle (fig 1 r-shift in accumulation logic shifting accumulator result based on max exp in).
Regarding claim 18, in addition to the teachings addressed in the claim 17 analysis, Abdel-Aziz teaches the following:
wherein the shifting the result of the addition based on a difference between the maximum exponent value and an exponent value stored according to the operation result of the previous cycle section 2.2 the accumulator operations, accumulation logic, including output from accumulation logic fed back into second r-shift inside accumulation logic for second alignment based on the exponent value and an operation result of a previous cycle (section 2.2 the accumulator operations, accumulation logic, including output from accumulation logic fed back into second r-shift inside accumulation logic for second alignment based on the max exponent, exponent value and an operation result of a previous cycle).
Regarding claim 24, in addition to the teachings addressed in the claim 23 analysis, Abdel-Aziz teaches the following:
wherein the first alignment comprises a right-shift and the second alignment comprises a left-shift (fig 2 r-shift following multipliers for first alignment comprises a right shift, section 2.2. local alignment, swap-r-shift in accumulation logic for second alignment comprises a left-shift, section 2.2 accumulator operations 3rd paragraph, a swap operation followed by a right shift is applied whenever a left shift is needed).
Regarding claim 25, in addition to the teachings addressed in the claim 23 analysis, Abdel-Aziz teaches the following:
wherein the one or more processors are configured to:
add a predetermined value to an exponent value of an output of a result of an accumulation of a result of the second alignment (fig 1 extended sign bits added to accumulator value); and
perform normalization on the output in which the sign bit is removed (fig 1 section 2.2. accumulator operations, first paragraph, extended sign bits removed from the accumulation, input to accumulation, the result of the accumulator is normalized, being before reformatted (to singed representation).
Regarding claim 26, Abdel-Aziz teaches the following:
one or more processors (fig 1 multiplier, shift, adder, accumulation logic pipeline for one or more processors) configured to:
multiply the plurality of data by routing data of a plurality of data corresponding to a plurality of data formats to one or more corresponding multipliers of a multiplier-accumulator (MAC) array determined based on the plurality of data formats (multipliers, adder tree, accumulator for MAC array, section 2, 5bx5b sign multipliers, fig 1 multipliers, section 2 second paragraph mixed precision IPU allows INT4, signed/unsigned and larger precision, fig 1 for plurality of data formats, input lines for routing data);
perform a first alignment on a result of the multiplication based on an exponent value of the plurality of data (section 2.2 local alignment, fig 1 r-shift following multipliers, wherein r-shift is controlled by exponent handling unit);
add a result of the first alignment (section 2.1, fig 1 adder tree); and
perform a second alignment on a result of the addition based on the exponent value and an operation result of a previous cycle (section 2.2 the accumulator operations, accumulation logic, including output from accumulation logic fed back into second r-shift inside accumulation logic for second alignment based on the exponent value and an operation result of a previous cycle).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Abdel-Aziz in view of A. Garofalo et al., XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions, EDAA 2020 (hereinafter “Garofolo”).
Regarding claim 27, in addition to the teachings addressed in the claim 26 analysis, Abdel-Aziz teaches the following:
wherein the multipliers of the MAC array comprise a plurality of multipliers (fig 1 multipliers).
Abdel-Aziz does not, however, explicitly disclose wherein a plurality of multipliers correspond to a larger bit input and another multiplier correspond to a smaller bit input. However, in the same field of endeavor, Garofolo discloses an apparatus similar to Abdel-Aziz comprising a plurality of multipliers represented sized to operate on smaller nibbles of data (fig 3, introduction, section I, section III.A). Garofolo further discloses wherein a plurality of multipliers correspond to a larger bit input and another multiplier correspond to a smaller bit input (fig 3, 17b multipliers, 5b multiplier). It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute different size multipliers as in Garofolo for the same size multipliers of Abdel-Aziz. It would have been obvious to achieve the benefit of increased efficiency in dot product operations based on the operation performed (abstract, section III.B. first three paragraphs, section IV).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 12197887 B2 DiCecco et al., (hereinafter “DiCecco”) discloses circuitry for decomposing block floating-point numbers into lower precision floating-point numbers, and circuitry including multiplication and accumulation (abstract, fig 3-fig 5).
US 10726514 B2 Ould-Ahmed-Vall et al., (hereinafter “Ould-Ahmed-Vall”) discloses an apparatus including a dynamic floating-point unit which includes computational logic to output data at multiple precisions, including multiplication and addition (abstract, fig 14-fig 16).
US 6564238 B1 Kim et al., (hereinafter “Kim”) discloses an apparatus that performs different word-length arithmetic operations using the same hardware, wherein the operations include multiplication and accumulation (abstract, fig 5-fig 9).
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