DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 07/06/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 07/06/2026 in reply to the non-final rejection mailed on 04/03/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claim 28 is canceled. Accordingly, pending in this Office action are claims 1-17.
Claims Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 13, the limitation “wherein the gate line is a select line or a word line which is connected to a memory block” is unclear as to what the Applicant intends to claim. The Applicant’s specification (see, e.g., para.0047) and drawings (see, e.g., fig. 5) describe the memory block be included in the memory device and may include the isolation layers, the gate structures, and the cell plug of the memory device. In another figure (see, e.g. fig. 1, para.0024-0028) a memory cell array of the same device is described and connected by word lines and select lines. It is unclear whether the limitation intends to claim the memory cell array of fig. 1 as the memory block, and the word lines and select lines are the gate lines of each gate structure, or if the intent is to redefine the memory device of fig. 5 as the memory block. In the latter case, were the memory device of fig. 5 to be redefined as the memory block, the connection of the gate lines to the memory block would already be present in the claim, as the gate lines are claimed to be a structure of the memory device in Claim 1, on which Claim 13 depends.
Claims Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14, & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Alsmeier (US 20120001247) in view of Zhang (US 20150357413).
Alsmeier (see, e.g., para.0026) states figs. 35-42 show the manufacturing steps for the device shown in fig. 28b. Figs. 28b & 35-42 and their respective paragraphs are used in conjunction as an embodiment, hereinafter “first embodiment,” for the following rejections.
Regarding Claim 1, Alsmeier (see, e.g., fig. 42, annotated figure 1) shows a memory device comprising:
isolation layers 143 (143a & 143b, see, e.g., para.0121) and gate structures (9, 9a, 9b, & 7), alternately stacked on a lower structure 100 (see, e.g., para.0121);
a tunnel isolation layer 11 (see, e.g., para.0124) penetrating the isolation layers and the gate structures;
a channel layer 1 (see, e.g., para.0118) formed along an inner wall of the tunnel isolation layer;
and a core plug 2 (see, e.g., para.0118) formed along an inner wall of the channel layer,
wherein each of the gate structures (9, 9a, 9b, & 7) includes:
a floating gate 9 (9a & 9b, see, e.g., para.0120) surrounding an outer wall of the tunnel isolation layer;
a first dielectric layer 7 (hereinafter “7a”, see, e.g., para.0122) surrounding an outer wall of the floating gate (see, e.g., annotated figure 1);
and a gate line 3 (see, e.g., para.0122) formed between the isolation layers,
wherein each of the gate structures is spaced apart in a stacking direction (vertical direction) of the isolation layers and the gate structures,
and the floating gate positioned adjacent to the first dielectric layer is disposed between the isolation layers (9a & 9b vertically and alternately stacked between layers 143a & 143b),
Alsmeier, however, fails to show,
a second dielectric layer surrounding an outer wall of the first dielectric layer;
a third dielectric layer surrounding an outer wall of the second dielectric layer;
the gate line filling a region surrounded at least in part by the third dielectric layer,
wherein the third dielectric layer includes
a first portion;
a second portion
and a third portion,
wherein the second portion is disposed at one end of the first portion and the third portion is disposed at another end of the first portion,
wherein the first portion contacts a sidewall of the second dielectric layer,
wherein the second portion and the third portion extend in a direction away from the floating gate,
and wherein the gate line is disposed between the second portion and the third portion.
wherein a top surface of the second portion contacts a first isolation layer of the isolation layers and a bottom surface of the third portion contacts a second isolation layer of the isolation layers.
Zhang (see, e.g., fig. 1b, para.0027) in a similar device to Alsmeier teaches the dielectric layer 7 can be comprised of multiple dielectric layers. The duplication of the first dielectric layer of Alsmeier to teach a second and a third dielectric layer, and their subsequent missing limitations, would be an obvious design choice. Unless a new and unexpected result is produced from the duplication of parts, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to duplicate the first dielectric layer of the device of Alsmeier, in view of the device of Zhang, as an obvious design choice, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Therefore, Alsmeier (see, e.g., annotated figure 1), in view of Zhang, shows
a second dielectric layer 7 (hereinafter “7b”) surrounding an outer wall of the first dielectric layer;
a third dielectric layer 7 (“hereinafter “7c”) surrounding an outer wall of the second dielectric layer;
the gate line 3 filling a region (inside the u-shape of 7c) surrounded at least in part by the third dielectric layer 7c,
wherein the third dielectric layer includes
a first portion (labeled “first portion”, see, e.g., annotated figure 1);
a second portion (labeled “second portion”, see, e.g., annotated figure 1
and a third portion (labeled “third portion”, see, e.g., annotated figure 1),
wherein the second portion is disposed at one end of the first portion and the third portion is disposed at another end of the first portion (u-shape, see, e.g., annotated figure 1),
wherein the first portion contacts a sidewall of the second dielectric layer 7b (see, e.g., annotated figure 1),
wherein the second portion and the third portion extend in a direction away from the floating gate (away from the core plug 2),
and wherein the gate line 3 is disposed between the second portion and the third portion (inside the u-shape of 7c, now formed by the first, second, and third portions).
wherein a top surface of the second portion contacts a first isolation layer (hereinafter “143a1”) of the isolation layers and a bottom surface of the third portion contacts a second isolation layer (hereinafter “143b1”) of the isolation layers.
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Regarding Claim 2, Alsmeier (see, e.g., figs. 36a-b), in view of Zhang, shows the memory device of claim 1,
wherein the core plug 2 is formed in a cylindrical shape (shown in top view),
the channel layer 1 is formed in a tubular shape surrounding a side surface of the core plug 2 (outer wall of the core plug, top view shows tubular shape of 1, see, e.g., figs. 36a-b),
and the tunnel isolation layer 11 is formed in a tubular shape surrounding a side surface of the channel layer 1 (outer wall of the channel layer, top view shows tubular shape of 11, see, e.g., figs. 36a-b).
Regarding Claim 3, Alsmeier (see, e.g., para.0118), in view of Zhang, shows the memory device of claim 1,
wherein: the core plug 2 is formed of an isolation material (“insulating fill material” see, e.g., para.0118),
The first embodiment of Alsmeier, in view of Zhang, however, fails to show
the channel layer is formed of poly-silicon,
and the tunnel isolation layer is formed of silicon oxide.
Alsmeier, in a second embodiment, shows
the channel layer 1 is formed of poly-silicon (see, e.g., para.0071),
and the tunnel isolation layer 11 is formed of silicon oxide (see, e.g., para.0048).
Alsmeier, in the second embodiment, shows the materials for the channel layer and tunnel isolation layer would provide the proper insulation and semi conductivity to operate the memory device.
The materials of the second embodiment of Alsmeier is incorporated into the device of the first embodiment of Alsmeier, in view of Zhang.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the materials of the second embodiment of Alsmeier in the first embodiment of Alsmeier in view of Zhang to provide the proper insulation and semi conductivity to operate the memory device and because the combination is a simple substitution of known materials of a channel layer and tunnel isolation layer in order to obtain predictable results – materials of the channel layer and tunnel isolation layer shown in one embodiment of an invention for another.
Regarding Claim 4, Alsmeier (see, e.g., fig. 36a-b), in view of Zhang, shows the memory device of claim 1,
wherein the floating gate 9 (9a & 9b) is formed in a tubular shape surrounding the tunnel isolation layer (top view shows tubular shape, see, e.g., figs. 36a-b).
Regarding Claim 5, Alsmeier (see, e.g., para.0112), in view of Zhang, shows the memory device of claim 1,
wherein the floating gate 9 (9a & 9b) comprises a material capable of storing electrons (“charge storage material” see, e.g., para.0112).
Regarding Claim 6, Alsmeier, in view of Zhang, shows the memory device of claim 1,
The first embodiment of Alsmeier, in view of Zhang, however, fails to show
wherein the floating gate comprises at least one of titanium nitride (TiN) and tantalum nitride (TaN).
Alsmeier, in a second embodiment, shows
wherein the floating gate comprises at least one of titanium nitride (TiN) and tantalum nitride (TaN) (see, e.g., para.0049).
Alsmeier, in the second embodiment, shows the materials for the floating gate would provide the proper charge storage properties to operate the memory device.
The materials of the second embodiment of Alsmeier is incorporated into the device of the first embodiment of Alsmeier, in view of Zhang.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the materials of the second embodiment of Alsmeier in the first embodiment of Alsmeier in view of Zhang to provide the proper charge storage properties to operate the memory device and because the combination is a simple substitution of known materials of a floating gate in order to obtain predictable results – materials of the floating gate shown in one embodiment of an invention for another.
Regarding Claim 7, Alsmeier, in view of Zhang (see, e.g., para.0037). shows the memory device of claim 1,
wherein the first dielectric layer 7a comprises a material having a permittivity lower than a permittivity of each of the second 7b and third dielectric layers 7c.
Zhang (see, e.g., para.0037) teaches the first, second, and third dielectric layers can comprise a variety of materials, such as silicon oxide, silicon nitride, and aluminum oxide respectively. Thus Alsmeier, in view of Zhang, would satisfy the limitation and render the claim obvious.
Regarding Claim 8, Alsmeier, in view of Zhang (see, e.g., para.0037), shows the memory device of claim 1,
wherein the first dielectric layer 7a comprises a material having an energy band gap higher than an energy band gap of the second dielectric layer 7b.
Zhang (see, e.g., para.0037) teaches the first and second dielectric layers can comprise a variety of materials, such as silicon oxide and silicon nitride respectively. Thus Alsmeier, in view of Zhang, would satisfy the limitation and render the claim obvious.
Regarding Claim 9, Alsmeier, in view of Zhang (see, e.g., para.0037), shows the memory device of claim 1,
wherein the first dielectric layer 7a comprises a silicon oxide (see, e.g., para.0037).
Regarding Claim 10, Alsmeier, in view of Zhang (see, e.g., para.0037). shows the memory device of claim 1,
wherein: the second dielectric layer 7b has a permittivity higher than a permittivity of the first dielectric layer 7a and a permittivity of the third dielectric layers 7c,
and the second dielectric layer 7b has an energy band gap lower than an energy band gap of the first dielectric layer 7a and lower than an energy band gap of the third dielectric layer 7c.
Zhang (see, e.g., para.0037) teaches the first, second, and third dielectric layers can comprise a variety of materials, such as silicon oxide, hafnium oxide, and aluminum oxide respectively. Thus Alsmeier, in view of Zhang, would satisfy the limitation and render the claim obvious.
Regarding Claim 11, Alsmeier, in view of Zhang (see, e.g., para.0037), shows the memory device of claim 1,
wherein the second dielectric layer 7b comprises at least one of silicon nitride, hafnium oxide, zirconium oxide, zirconium silicate, and hafnium silicate.
Regarding Claim 12, Alsmeier, in view of Zhang (see, e.g., para.0037), shows the memory device of claim 1,
wherein the third dielectric layer 7c comprises an aluminum oxide.
Regarding Claim 14, Alsmeier (see, e.g., para.0122), in view of Zhang, shows the memory device of claim 1,
wherein the gate line 3 comprises a conductive layer or a semiconductor layer (“depositing a conductor” see, e.g., para.0122).
Regarding Claim 15, Alsmeier (see, e.g., para.0122), in view of Zhang, shows the memory device of claim 1,
wherein the gate line 3 comprises at least one of tungsten (W), tungsten nitride (WN), titanium nitride, molybdenum (Mo), cobalt (Co), nickel (Ni), silicon (Si), and poly-silicon (Poly-Si) (see, e.g., para.0122).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Alsmeier (US 20120001247) in view of Zhang (US 20150357413) and further in view of Choi (US 20210210505).
Regarding Claim 13, Alsmeier, in view of Zhang, shows the memory device of claim 1,
Alsmeier, in view of Zhang, however, fails to show
wherein the gate line is a select line or a word line, which is connected to a memory block.
Choi (see, e.g., fig. 7, figs. 25-27, para.0074, para.0121), in a similar device to Alsmeier, in view of Zhang, shows a configuration
wherein the gate line is a select line or a word line WL1-N, which is connected to a memory block 510.
Choi (see, e.g., para.0074, para.0121-0123) states fig. 7 shows a nonvolatile memory device and figs. 25-26 are a cross-sectional view of another embodiment of fig. 7. Fig. 27 shows a memory device system including “the nonvolatile memory device according to some embodiments” and the memory device system includes the memory block 510. Choi states the configuration would provide additional elements which provide voltage and word line voltage, transfer data to the memory block, and input/output data between the memory device and the memory block.
The configuration of Choi is combined with the device of Alsmeier, in view of Zhang.
It would have been obvious at the time of filing the invention to one of ordinary skill to combine the configuration of Choi with the device of Alsmeier, in view of Zhang, to provide additional elements which provide voltage and word line voltage, transfer data to the memory block, and input/output data between the memory device and the memory block.
Claims 16 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Alsmeier (US 20120001247) in view of Zhang (US 20150357413) and further in view of Baraskar (US 20200388688).
Regarding Claim 16, Alsmeier, in view of Zhang, shows the memory device of claim 1, further comprising
Alsmeier, in view of Zhang, however, fails to show
a barrier layer formed between the gate line and the third dielectric layer.
Baraskar (see, e.g., figs. 14c-d, para.0201) in a similar device to Alsmeier, in view of Zhang, that a barrier layer 46a formed on surfaces of the gate line 46b between the gate line and the dielectric layer 44 would promote adhesion between the gate line and the dielectric layer.
It would have been obvious at the time of filing the invention to one of ordinary skill to one of ordinary skill in the art to use the barrier layer of Baraskar, in the device of Alsmeier, in view of Zhang, to promote adhesion between the gate line 3 and the first, second and third dielectric layers 7a, 7b & 7c.
By incorporating the barrier layer 46a between the gate line 3 and all dielectric layers 7a, 7b & 7c, the limitation “a barrier layer formed between the gate line and the third dielectric layer” is rendered obvious
Regarding Claim 17, Alsmeier, in view of Zhang and further in view of Baraskar (see, e.g., para.00201), shows the memory device of claim 16,
wherein the barrier layer comprises tungsten nitride (WN) or titanium nitride (TiN).
Response to Arguments
Applicant's arguments filed 07/06/2026 have been fully considered but they are not persuasive.
The amended limitation “wherein a top surface of the second portion contacts a first isolation layer of the isolation layers and a bottom surface of the third portion contacts a second isolation layer of the isolation layers” warrants further search and/or examination of the prior art of record. The prior art of record (Alsmeier, in view of Zhang) is reinterpreted to define the positions of the first, second and third dielectric layers, and by extension the position of the second and third portion of the third dielectric layer. As shown in paragraphs 8-13 above and in annotated figure 1, the amended limitation is shown by the prior art of record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
