DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1, 3, and 5-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Byrne et al (hereafter Byrne)(US Pat. 6,487,672).
5. As to claim 1, Byrne discloses a sample rate converter (SRC) for implementing a rate conversion R, wherein the SRC receives input samples at an input rate Fin and outputs samples at an output rate Fort = Fin x R, and wherein R is a fractional value greater than 1 (abstract and column 2, lines 47-67), the SRC comprising:
a plurality of filters to process the received input samples (fig. 1 and 4);
a multiplier-adder block to generate the output samples for the SRC based on respective delta values and outputs of the plurality of filters, wherein each of the delta values is associated with a time interval from one of the received input samples (column 4, lines 44-49 multipliers/adders; column 5, lines 1-10; column 8, lines 32-61 intervals); and
a plurality of buffers to buffer samples between the plurality of filters and the multiplier-adder block based at least in part on N buffer read pointers, where N is an integer greater than 1 (column 7, line 18-column 8, line 13); and
resampler control circuitry to generate N delta values of the delta values and the N buffer read pointers in parallel based on R (column 9, lines 30-64 operated in parallel).
6. As to claim 3, Byrne discloses wherein each buffer of the plurality of buffers stores output samples of a respective one of the plurality of filters, and wherein the stored samples are read from each buffer based on the N buffer read pointers (column 4, lines 63-67 From sample rate converter 12 the interpolated samples are output to elastic buffer 20 where they are stored for subsequent access by data detector 22).
7. As to claims 5 and 19, Byrne discloses wherein the resampler control circuitry operates based on a clock signal divided from Fout based on N, and wherein the N delta values and the N buffer read pointers are generated in parallel within one clock cycle of the clock signal (column 7, line 26-column 8 line 13, each cycle).
8. As to claim 6, Byrne discloses wherein the resampler control circuitry increments a base accumulation value by Nx1/R and generates the N delta values and the N buffer read pointers based on the incremented base accumulation value (column 5, line 45-column 6, line 6).
9. As to claims 7 and 16, Byrne discloses wherein the resampler control circuitry applies a modulo operation to the base accumulation value before the incrementing (column 6, lines 7-29).
10. As to claims 8, 17, and 20, Byrne discloses wherein the resampler control circuitry generates the N delta values by adding k x 1/R to the incremented base accumulation value, where k varies from 0 to N-1 (column 6, lines 7-29).
11. As to claim 9, Byrne discloses a base accumulator to increment a base accumulation value by N x 1/R; and N adders each generating one of the N delta values and an offset for a corresponding buffer read pointer of the N buffer read pointers by adding k x R_int to the incremented base accumulation value, where k varies from 0 to N-1 and R_int corresponds to 1/R represented as a P-bit integer value (column 7, line 26-column 8, line 6).
12. As to claim 10, Byrne discloses wherein an output of a first adder of the N adders includes: a first bit portion corresponding to a respective one of the N delta values; and a second bit portion corresponding to an offset for a respective one of the N buffer read pointers (column 7, line 26-column 8, line 6).
13. As to claim 11, Byrne discloses a sample rate converter (SRC) for implementing a rate conversion R, wherein the SRC receives input samples at an input rate Fin and outputs samples at an output rate Fort=Fin/R, and wherein R is a fractional value greater than 1 (abstract and column 2, lines 47-67), the SRC comprising:
a multiplier block to multiply each of the received input samples by a respective one of delta values, wherein each of the delta values is associated with a time interval from a sample time of one of the SRC output samples; integration and dump circuitry to sum outputs of the multiplier block (column 4, lines 44-49 multipliers/adders; column 5, lines 1-10; column 8, lines 32-61 intervals); and
resampler control circuitry to generate N delta values of the delta values and N buffer write pointers in parallel, wherein N is an integer greater than 1; a plurality of filters; and a plurality of buffers to buffer samples between the integration and dump circuitry and the plurality of filters based at least in part on the N buffer write pointers (column 7, line 18-column 8, line 13 and column 9, lines 30-64).
14. As to claim 12, Byrne discloses wherein the integration and dump circuitry comprises a plurality of integration and dump sub-circuitries each coupled to a respective filter of the plurality of filters to generate a sample for input to the respective filter based on a sum of a first output and a second output of the outputs of the multiplier block (column 11, line 63-column 12, line 11).
15. As to claim 13, Byrne discloses wherein the integration and dump circuitry sums the outputs of the multiplier block by multiplying a first output of the outputs of the multiplier block by a value based on a comparison between two successive buffer write pointers of the N buffer write pointers to produce a product value and summing a second output of the outputs of the multiplier block (column 7, line 26-column 8, line 13).
16. As to claim 14, Byrne discloses wherein output samples of the integration and dump circuitry for each of the plurality of filters are stored at a respective one of the plurality of buffers based on the N buffer write pointers, and wherein the stored samples are read from each buffer for processing by a respective filter of the plurality of filters (column 7, line 26-column 8, line 13).
17. As to claim 15, Byrne discloses wherein the resampler control circuitry operates based on a clock signal divided from Fin based on N, and wherein the N delta values and the N buffer write pointers are generated in parallel within one clock cycle of the clock signal (column 7, line 26-column 8 line 13, each cycle).
18. As to claim 18, the claim is rejected for similar reasons as to claims 1 and 11 above.
Claim Rejections - 35 USC § 103
19. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
20. Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byrne in view of Tsutsui (US Pub. 2012/0066280).
21. As to claim 2, Byrne doesn’t disclose wherein each one of the plurality of filters is associated with a different polynomial order.
However, Tsutsui discloses wherein each one of the plurality of filters is associated with a different polynomial order ([0030]-[0031], polynomial order).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Byrne with each one of the plurality of filters is associated with a different polynomial order as in Tsutsui for the benefit of sample rate conversion that use a polynomial interpolator with minimax stopband attenuation (Tsutsui abstract).
22. As to claim 4, the combination of Byrner and Tsutsui discloses the resampler control circuitry further comprises N multiplexers (MUXs), each of the N MUXs having inputs connected to respective outputs of a first buffer of the plurality of buffers and outputs connected to the multiplier-adder block; and the resampler control circuitry further generates a selection signal to each of the N MUXs based on a respective one of the N buffer read pointers ([0065]-[0068] multiplexer).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pat. 6,141,671 – related to circuits for converting data samples received at a first sample rate into corresponding data samples provided at a second rate. More particularly, the invention is a sample rate converter capable of converting a sequence of digital data samples presented at an input sample rate into a different sequence of digital data provided at an output sample rate which is not a rational multiple or submultiple of the input sample rate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/Primary Examiner, Art Unit 2151