Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Restriction/Election Requirement
Applicant’s election, without traverse, of Group I, Species B, Claims 1-10, 17-20 on 4/14/2025, has been acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it is not clear how "a first internal side surface of the first cavity" is "vertically spaced from a first floor of the first cavity" and "a second internal side surface of the second cavity" is "vertically spaced from a second floor of the second cavity", because it appears that the first/second internal side surface of the first/second cavity shown in Fig. 6 of current application are connected to the first/second floor of the first/second cavity rather than being spaced from the first/second floor of the first/second cavity. Furthermore, it is not clear what a "floor" of the first and second cavity refers to, because a cavity is an empty space, and therefore, a cavity does not exactly have a floor. Claims 2-10 and 17-20 depend on claim 1, and therefore, claims 2-10 and 17-20 are also indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-10, 17-20 are rejected under 35 U.S.C. 102 as being unpatentable in view of Shen et al. (US 20200043817 A1).
Regarding claim 1, Shen et al. disclose a semiconductor device assembly (504, FIG. 5A/5B) comprising:
a substrate (wiring substrate 120, protective substrate 410) with a first cavity (414) having a first connective element (130) at a first internal side surface of the first cavity vertically spaced from a first floor of the first cavity; a second cavity having a second connective element (130) at a second internal side surface of the second cavity vertically spaced from a second floor of the second cavity (FIG. 12);
A first semiconductor die (110, FIG. 3E) disposed in the first cavity and having a third connective element at a first edge surface of the first semiconductor die;
A second semiconductor die (110, FIG. 3E) disposed in the second cavity and having a fourth connective element at a second edge surface of the second semiconductor die, wherein the first semiconductor die and the second semiconductor die are electrically coupled through the first connective element, the second connective element, the third connective element, and the fourth connective element.
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Regarding claim 2, Shen et al. disclose a semiconductor device assembly (504) further comprising an interposer (wiring substrate 120.1) and coupling the first connective element to the second connective element (140.1, FIG. 5A/5B).
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Regarding claim 3, Shen et al. disclose a semiconductor device assembly (504) wherein the first connective element and the third connective element comprise a conductive contact; wherein the semiconductor device assembly further comprises a solder joint (140) coupling the first connective element and the third connective element (140.1).
Regarding claim 6, Shen et al. disclose a semiconductor device assembly wherein an upper surface of the first semiconductor die (120) is recessed from an upper surface of the substrate (protective substrate 410, substrate 410S, FIG. 1).
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Figure 1 Semiconductor Device Assembly
Regarding claim 7, Shen et al. disclose a semiconductor device assembly further comprising a third semiconductor die mounted to the upper surface of the interposer substrate (120.1S, FIG. 1).
Regarding claim 8, Shen et al. disclose a semiconductor device assembly wherein the first and second connective elements (130) are spaced from an upper surface of the interposer substrate (120.1S, FIG. 1).
Regarding claim 9, Shen et al. disclose a semiconductor device assembly wherein the substrate further includes a fifth connective element at the first floor of the first cavity;
The first semiconductor die has a sixth connective element at a bottom surface of the first semiconductor die, the sixth connective element coupled with the fifth connective element effective to electrically couple the first semiconductor die and the substrate.
Regarding claim 10, Shen et al. disclose a semiconductor device assembly comprising a third semiconductor die (110 annotated below in FIG. 5A) disposed in the first cavity below the first semiconductor die.
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Regarding claim 17, Shen et al. disclose a substrate comprising:
A first cavity (414) recessed in a top surface of the substrate (120.1S), the first cavity having a first connective element exposed at a side surface of the first cavity;
A second cavity (414) recessed in the top surface of the substrate, the second cavity having a second connective element exposed at a side surface of the second cavity; and circuitry ([0025] “Interposer 120.1 may include transistors, resistors, capacitors, and other devices (not shown) in substrate 120.1S”) internal to the interposer substrate and coupling the first and second connective element.
Regarding claim 18, Shen et al. disclose a substrate wherein the first connective element comprises a conductive contact. Shen does not disclose an inductor or optical element, however, it would be obvious to one of ordinary skill in the art before the effective filing date to form an inductor and optical element at the connective elements in order to increase inductance to optimize current regulation and smoothing, protect against transient change in current and voltage spikes, decrease the footprint of the semiconductor device and ensure precise alignment and stability.
Regarding claim 19, Shen et al. disclose a substrate which further includes a third connective element (140.1, FIG. 5A) exposed at a bottom surface of the first cavity (414).
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Regarding claim 20, Shen et al. disclose a substrate wherein the first cavity and second cavity have different depths (which can vary due to fabrication variation, metrology error, and die and connection sizes):
[0030] “The cavity depth depends on the thickness of dies 410 and connections 140.1.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable in view of Shen et al. (US 20200043817 A1).
Regarding claim 4, Shen et al. disclose a semiconductor device assembly including the first and third connective element, however, Shen does not disclose these elements as being inductive. It would be obvious to one of ordinary skill in the art before the effective filing date to form inductors at the connective elements (and other passive elements as suggested in [0025]) in order to increase inductance to optimize current regulation and smoothing and protect against transient change in current and voltage spikes.
[0025] “Interposer 120.1 may include transistors, resistors, capacitors, and other devices (not shown) in substrate 120.1S and redistribution layer 210.T.”
Regarding claim 5, Shen et al. disclose a semiconductor device assembly including the first and third connective element, however, Shen does not disclose these elements as being an optical element. It would be obvious to one of ordinary skill in the art before the effective filing date to form optical elements at the connective elements (and other elements as suggested in [0025]) and to electrically couple the first and third element through an optical connection in order to decrease the footprint of the semiconductor device and ensure precise alignment and stability.
Response to Arguments
Applicants' arguments filed October 15, 2025 have been fully considered but they are not persuasive.
Applicants amendment with regards to Claim 1 "A semiconductor device assembly, comprising: a substrate including: a first cavity having a first connective element at a first internal side surface of the first cavity vertically spaced from a first floor of the first cavity; and a second cavity having a second connective element at a second internal side surface of the second cavity vertically spaced from a second floor of the second cavity". Regarding claim 1, it is not clear how "a first internal side surface of the first cavity" is "vertically spaced from a first floor of the first cavity" and "a second internal side surface of the second cavity" is "vertically spaced from a second floor of the second cavity", because it appears that the first/second internal side surface of the first/second cavity shown in Fig. 6 of current application are connected to the first/second floor of the first/second cavity rather than being spaced from the first/second floor of the first/second cavity. Furthermore, it is not clear what a "floor" of the first and second cavity refers to, because a cavity is an empty space, and therefore, a cavity does not exactly have a floor.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joshua S Wyatt whose telephone number is (703) 756-1937. The examiner can normally be reached 7:00 AM - 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached on (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSHUA SCOTT WYATT/Examiner, Art Unit 2815
/JAY C KIM/Primary Examiner, Art Unit 2815