DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 08/10/2022. Claims 1-17 are currently pending, of which claims 1-17 are currently rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the output including an ith entry of a value and a jth entry of a value … the ith entry of the value being binary, the jth entry of the value being non-binary”. It is unclear if applicant intends for the ith and jth entries to represent the same value or a different value. Appropriate correction is required.
Claims 2-14 inherit the same deficiency as claim 1 by reason of dependence. They are rejected for the same reason.
Claims 15-17 recite similar limitations as claim 1 and are rejected for the same reason therein.
Claim 8 recites the limitations “an other part of the memory portions is configured to store an other part of the first vector,
an other part of the memory portions is configured to store a part of the second vector,
an other part of the memory portions is configured to store an other part of the second vector,
an other part of the memory portions is configured to store a part of the third vector, and
an other part of the memory portions is configured to store an other part of the third vector.”
It is unclear if applicant intends these parts of the memory portions to be the same parts, or different parts of the memory portions. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 and 17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding Claim 1, at Step 1 the claim is directed to an apparatus, which is a statutory category of invention.
At Step 2A, Prong 1, Examiner notes that claims are directed to mathematical concepts:
A calculation device, comprising:
a processing device configured to perform a processing procedure,
the processing procedure including a first update of a first vector, a second update of a second vector, and a third update of a third vector (mathematical calculations),
the first update including updating the first vector using the second vector and the third vector (mathematical calculations/relationships),
the second update including updating the second vector using the first vector (mathematical calculations/relationships), and
the processing device being configured to output an output of at least one of the first vector obtained after repeating the processing procedure or a function of the first vector obtained after the repeating the processing procedure (mathematical calculations/relationships),
the output including an ith entry of a value and a jth entry of a value,
the i being an integer of not less than 1 and not more than n,
the n being an integer of not less than 2,
the j being an integer of not less than 1 and not more than the n,
the j being different from the i,
the ith entry of the value being binary,
the jth entry of the value being non-binary,
a variable of the first vector including the ith entry of a first variable xi and the jth entry of a first variable xj,
a variable of the second vector including the ith entry of a second variable yi and the jth entry of a second variable yj (mathematical relationships),
the second update including updating the ith entry of the second variable yi by adding a first function calculated from the ith entry of the first variable xi and a second function calculated from the ith entry of the first variable xi to the ith entry of the second variable yi before the update (mathematical calculations/relationships), and
the second update including updating the jth entry of the second variable yj by adding the first function calculated from the jth entry of the first variable xj to the jth entry of the second variable yj before the update (mathematical calculations/relationships).
At Step 2A Prong 2, the additional elements are bolded above. These additional elements are merely an “apply it” scenario using generically recited computer components. See MPEP 2106.05(f). In the “A calculation device, comprising: a processing device configured to” and “the processing device being configured to” limitations, the claim is simply using generic processing devices to perform the mathematical calculations/relationships (updating vectors using first, second, and third vectors). The updating of vectors is merely a mathematical concept. As disclosed in the book “Vector Analysis” by Edwin Bidwell Wilson, a vector is defined as “a quantity which is considered as possessing direction as well as magnitude” (Vector Analysis Chapter 1 Addition and Scalar Multiplication, First Page) Hence, the updating of vectors requires performing mathematical calculations to modify the quantities that constitute the vector.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As explained in the step 2A prong 2 analysis, the additional elements are at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept.
Claim 2 is directed to the mathematical concept of setting the ith entry and jth entry as binary and non-binary values (mathematical relationships). Moreover, none of the additional elements regarding the generic computer components (i.e., first controller) are more than high level computer components that amount to mere instructions to apply the abstract idea on a generic computer. See MPEP 2106.05(f). At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Claim 3 merely describes the properties of the third vector (mathematical relationships). Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 4 further describes the properties of the third vector (mathematical relationships). Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 5 is directed to the mathematical concept of perform vector updates (mathematical calculations). Moreover, none of the additional elements regarding the generic computer components (i.e., processor, memory part, processing portions) are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer. See MPEP 2106.05(f). At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Claim 6 is directed to the mathematical concept of perform vector updates (mathematical calculations). Moreover, none of the additional elements regarding the generic computer components (i.e., processor, memory part, processing portions) are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer. See MPEP 2106.05(f). At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Claim 7 is directed to the mathematical concept of perform vector updates (mathematical calculations). Moreover, none of the additional elements regarding the generic computer components (i.e., processor, memory part, processing portions) are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer. See MPEP 2106.05(f). At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Claim 8 merely describes the generic computer component (memory part including plurality of memory portions) that is configured to store the results of the mathematical calculations (vector updates). Storing data in memory is considered insignificant extra-solution activity as recognized by the courts. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g. at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. These limitations therefore remain insignificant extra-solution activity even upon consideration. Thus, these limitations do no amount to significantly more.
Claim 9 is directed to the mathematical concept of perform vector updates (mathematical calculations). Moreover, none of the additional elements regarding the generic computer components (i.e., processor, memory part, processing portions, memory portions) are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer. See MPEP 2106.05(f). At Step 2B, as stated in claim 8, storing data in memory is recognized as an insignificant extra-solution activity as per MPEP 2106.05(d)(II).
Claim 10 is directed to the mathematical concept of perform vector updates (mathematical calculations). Moreover, none of the additional elements regarding the generic computer components (i.e., processor, memory part, processing portions, memory portions) are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer. See MPEP 2106.05(f). At Step 2B, as stated in claim 8, storing data in memory is recognized as an insignificant extra-solution activity as per MPEP 2106.05(d)(II).
Claim 11 is directed to the mathematical concept of perform vector updates (mathematical calculations). Moreover, none of the additional elements regarding the generic computer components (i.e., processor, memory part, processing portions, memory portions) are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer. See MPEP 2106.05(f). At Step 2B, as stated in claim 8, storing data in memory is recognized as an insignificant extra-solution activity as per MPEP 2106.05(d)(II).
Claim 12 is directed to the mathematical concept of updating vectors (mathematical calculations). Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 13 is directed to the mathematical concept of updating vectors (mathematical calculations). Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 14 is directed to the mathematical concept of updating vectors (mathematical calculations). Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 15 is an apparatus claim reciting similar limitations as claim 1 and is rejected for at least the same reasons therein. Herein, claim 15 is directed towards the statutory category of an apparatus, thus also satisfying Step 1. Under Step 2A Prong 2, the claim merely recites a generic computer to perform the mathematical concept recited in claim 1. At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Claim 17 is a method version of claim 1 and is rejected for at least the same reasons therein. Herein, claim 17 is directed towards the statutory categories of a method, thus also satisfying Step 1. Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 16 is rejected under 35 U.S.C. 101 because a recording medium being a computer-readable recording medium that records a calculation program would normally be considered statutory unless the specification defines “recording medium being a computer-readable recording medium” as including transient media such as signals, carries waves, transmissions, optical waves, transmission media or other media incapable of being touched or perceived absent the non-transitory medium through which they are conveyed.
Claim 16, is not limited to non-transitory embodiments. Specifically, in view of the specification (Page 27 Lines 10-32), the recording medium is not limited to non-transitory embodiments. Instead, the specification explains that the recording medium includes a magnetic disk, an optical disk, semiconductor memory, or other recording medium (including both non-transitory and transitory embodiments). Therefore, the claim is not limited to statutory subject matter, hence Claim 16 is non-statutory.
However, even if considered statutory (limited to only non-transitory embodiments), the claim recites similar limitations as claims 1, 15, and 17, and does not recite additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuangchuang Sun in NPL: “Distributed Optimization for Convex Mixed-Integer Programs based on Projected Subgradient Algorithm” (cited in IDS on 06/19/2023).
Claims 1-17 are rejected for the reasons described in the European search opinion for corresponding European Patent Application No.: EP 4239501 A1.
Prior Art Made of Record
Feng Wang in NPL: “A particle swarm optimization algorithm for mixed-variable optimization problems”, hereinafter “Wang” – teaches a Particle Swarm Optimization (PSO) algorithm to solve Mixed-Variable Optimization Problems. Wang teaches using both continuous (nonbinary) and discrete (binary) sets in two segments of a position vector x, and uses two separate algorithms to return, or update, continuous and discrete variables of vector x. See Wang: Algorithms 1-4, and Fig. 1.
Marianna de Santis in NPL: “Solving Multiobjective Mixed Integer Convex Optimization Problems”, hereinafter “de Santis” – teaches solving an NP hard problem using an algorithm for detecting or building feasible points of a mixed integer set. Algorithm 1 updates variable LW, and Algorithm 2 (called in algorithm 1 line 6) updates variables LPNS and LLUB. De Santis further discloses finding lower bounds of the continuous relaxation (non-binary values) of the problem (including variables) obtained by ignoring integrality constraints (binary values). See de Santis: Page 3 last paragraph, and Section 3.1 “Computation of upper bounds and local upper bounds” including Algorithm 1, and Section 3.3 “Correctness of MOMIX”, including Algorithm 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182