DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 08/10/2022. Claims 1-20 are currently pending, of which claims 1-20 are currently rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-12, 14-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lutz et al. (U.S. Patent Application Publication No.: US 20050210095 A1), hereinafter “Lutz”.
Regarding Claim 1, Lutz teaches:
Circuitry comprising:
a comparison circuit having a first input configured to receive a first input value, a second input configured to receive a second input value, and an output on which a corresponding comparison value is generated (Fig. 6, e.g., shows logic 510 (comparison circuit) that receives first and second integer data elements A and B (first and second input values); ¶0099, e.g., carry value register 525 stores comparison result from logic 510 (comparison circuit)); and
an adder circuit having a first input configured to receive the first input value, a second input configured to receive the second input value, a third input configured to receive the comparison value from the output of the comparison circuit, and an output on which an adder output value is generated, wherein the adder circuit is configured to compute the adder output value based on a sum of the first input value and the comparison value (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result; ¶0102, e.g., adder 535 adds two data elements and the comparison result).
Regarding Claim 2, Lutz teaches:
The circuitry of claim 1, wherein the adder circuit is configured to compute the adder output value based on a sum of the first input value, a version of the second input value different than the second input value, and the comparison value (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Operand B is inverted before being received by the adder (version of the second input value different than the second input value)).
Regarding Claim 3, Lutz teaches:
The circuitry of claim 1, wherein the adder circuit is configured to compute the adder output value based on a sum of the first input value, an inverted version of the second input value, and the comparison value (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Operand B is inverted before being received by the adder).
Regarding Claim 4, Lutz teaches:
The circuitry of claim 1, wherein the second input of the adder circuit is an inverting input configured to invert bits of the second input value (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Operand B is inverted before being received by the adder).
Regarding Claim 7, Lutz teaches:
The circuitry of claim 1, further comprising:
an inverter configured to receive the adder output value (Fig. 6, e.g., inverter 540 receives adder output).
Regarding Claim 8, Lutz teaches:
The circuitry of claim 1, further comprising:
a selection circuit having a first input configured to receive the adder output value directly from the output of the adder circuit, a second input configured to receive a version of the adder output value different than the adder output value, and a third input configured to receive the comparison value from the output of the comparison circuit (Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector). Multiplexer 545 receives n signal generated by logic 510 (comparison value generated by comparison circuit); ¶0102).
Regarding Claim 9, Lutz teaches:
The circuitry of claim 1, further comprising:
a selection circuit having a first input configured to receive the adder output value directly from the output of the adder circuit, a second input configured to receive an inverted version of the adder output value via an inverter, and a third input configured to receive the comparison value from the output of the comparison circuit (Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector). Multiplexer 545 receives n signal generated by logic 510 (comparison value generated by comparison circuit); ¶0102).
Regarding Claim 10, Lutz teaches:
The circuitry of claim 9, wherein the selection circuit has an output on which an absolute value of a difference between the first and second input values is generated (¶0100).
Regarding Claim 11, Lutz teaches:
A method comprising:
comparing a first input value to a second input value to obtain a comparison value (Fig. 6, e.g., shows logic 510 (comparison circuit) that receives first and second integer data elements A and B (first and second input values); ¶0099, e.g., carry value register 525 stores comparison result from logic 510 (comparison circuit));
computing a sum of the first input value, a version of the second input value different than the second input value, and the comparison value (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result; ¶0102, e.g., adder 535 adds two data elements and the comparison result); and
selecting between the sum and a version of the sum different than the sum (Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector) to be selected based on comparison result n; ¶0102).
Regarding Claim 12, Lutz teaches:
The method of claim 11, wherein comparing the first input value to the second input value comprises determining whether the first input value is greater than or equal to the second input value (¶0099, e.g., Logic 510 determines the largest value of first and second data elements (first and second input values) and outputs comparison result based on which value is largest; Fig. 6).
Regarding Claim 14, Lutz teaches:
The method of claim 11, wherein computing the sum comprises calculating a sum of the first input value, an inverted version of the second input value, and the comparison value (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Data element B is inverted before being received by the adder).
Regarding Claim 15, Lutz teaches:
The method of claim 11, wherein selecting between the sum and a version of the sum different than the sum comprises selecting between the sum and an inverted version of the sum (Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector) to be selected based on comparison result n; ¶0102).
Regarding Claim 16, Lutz teaches:
The method of claim 11, wherein selecting between the sum and a version of the sum different than the sum comprises:
selecting the sum upon determining that the comparison value is high (Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector) to be selected based on comparison result n; ¶0102); and
selecting a version of the sum different than then sum upon determining that the comparison value is low (Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector) to be selected based on comparison result n; ¶0102).
Regarding Claim 17, Lutz teaches:
Absolute difference circuitry comprising:
a comparison logic configured to receive first and second input numbers (Fig. 6, e.g., Logic 510 (comparison logic) receives data elements A and B (first and second input numbers)) and to generate a comparison output based on a comparison of the first and second input numbers (¶0099, e.g., Logic 510 determines the largest value of first and second data elements (first and second input values) and outputs comparison result based on which value is largest; Fig. 6);
an adder configured to receive the first and second input numbers and the comparison output and to generate an adder output (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result; ¶0102, e.g., adder 535 adds two data elements and the comparison result); and
a multiplexer configured to receive the adder output, a version of the adder output different than the adder output, and the comparison output (Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 to be selected based on comparison result n; ¶0102).
Regarding Claim 18, Lutz teaches:
The absolute difference circuitry of claim 17, wherein the adder is configured to generate the adder output by computing a sum of the first input number, an inverted version of the second input number, and the comparison output (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Data element B is inverted before being received by the adder).
Regarding Claim 19, Lutz teaches:
The absolute difference circuitry of claim 17, wherein the multiplexer is configured to:
receive the adder output, an inverted version of the adder output, and the comparison output; and
output either the adder output or the inverted version of the adder output based on the comparison output (Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 to be selected based on comparison result n; ¶0102).
Regarding Claim 20, Lutz teaches:
The absolute difference circuitry of claim 17, wherein the adder is the only adder in the absolute difference circuitry (¶0100).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lutz in view of M. Morris Mano in NPL: “Digital Design Third Edition” (https://nibmehub.com/opac-service/pdf/read/Digital%20Design-%203rd%20Edition.pdf), hereinafter “Mano”.
Regarding Claim 5, Lutz teaches:
The circuitry of claim 1, wherein the comparison circuit is configured to:
drive the comparison value to a … value upon determining that the first input value is greater than or equal to the second input value (¶0099, e.g., Logic 510 determines the largest value of first and second data elements (first and second input values) and outputs comparison result based on which value is largest; Fig. 6); and
drive the comparison value to [another value] upon determining that the first input value is less than the second input value (¶0099, e.g., Logic 510 determines the largest value of first and second data elements (first and second input values) and outputs comparison result based on which value is largest; Fig. 6).
Lutz does not teach:
drive the comparison value to a first value upon determining that the first input value is greater than or equal to the second input value; and
drive the comparison value to a second value different than the first value upon determining that the first input value is less than the second input value.
However, in the same field of endeavor, Mano teaches the fundamentals of a magnitude comparator, where it describes comparing two binary values and outputting a binary value depending on the condition. Mano explains “The comparison of two numbers is an operation that determines if one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether A > B, A = B, or A < B.” (Mano: Page 163, Section 5-4 Magnitude Comparator)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the comparator determining whether A > B, A = B, or A < B indicated by a binary variable as taught by Mano with the logic 510 as taught by Lutz. One would have been motivated to combine these references because both references disclose comparators in digital circuits, and Mano enhances the model of Lutz by allowing for the logic 510 to accurately indicate if A is larger, equal to, or smaller than B. Combination would cause for either of the conditions to be indicated true (high) or not true (low) by a binary variable as taught by Mano.
Regarding Claim 6, Lutz teaches:
The circuitry of claim 1, wherein the comparison circuit is configured to:
drive the comparison value high … (¶0099, e.g., logic 510 (comparison circuit) can produce a single comparison result (i.e. n=1), hence n would either have to be high or low); and
drive the comparison value low … (¶0099, e.g., logic 510 (comparison circuit) can produce a single comparison result (i.e. n=1), hence n would either have to be high or low).
Lutz does not teach:
drive the comparison value high upon determining that the first input value is greater than or equal to the second input value; and
drive the comparison value low upon determining that the first input value is less than the second input value.
However, in the same field of endeavor, Mano teaches the fundamentals of a magnitude comparator, where it describes comparing two binary values and outputting a binary value depending on the condition. Mano explains “The comparison of two numbers is an operation that determines if one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether A > B, A = B, or A < B.” (Mano: Page 163, Section 5-4 Magnitude Comparator)
The motivation to combine provided with respect to claim 5 applies equally to claim 6.
Regarding Claim 13, Lutz teaches the method of claim 12. Lutz does not teach:
wherein comparing the first input value to the second input value comprises further comprises:
asserting the comparison value in response to determining that the first input value is greater than or equal to the second input value; and
deasserting the comparison value in response to determining that the first input value is less than the second input value.
However, in the same field of endeavor, Mano teaches the fundamentals of a magnitude comparator, where it describes comparing two binary values and outputting a binary value depending on the condition. Mano explains “The comparison of two numbers is an operation that determines if one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether A > B, A = B, or A < B.” (Mano: Page 163, Section 5-4 Magnitude Comparator)
The motivation to combine provided with respect to claim 5 applies equally to claim 13.
Prior Art Made of Record
US 20170150175 A1 – teaches an absolute difference circuit using an adder, two inverse units, and an and gate. See Fig. 18 and corresponding description.
US 8131788 B1 – teaches a Difference unit 200 that includes inverters 203 and 207, adder 204, and exclusive-OR ("XOR") gate 209. See Fig. 2 and corresponding description.
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182