DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 05/05/2026. Claims 1-20 are currently pending, of which claims 1-20 are currently rejected.
Response to Arguments
Applicant’s arguments filed on 05/05/2026 have been fully considered, and are found persuasive. However, see new grounds of rejection bellow.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-12, 14-20 are rejected under 35 U.S.C. 103 as being anticipated by Lutz et al. (U.S. Patent Application Publication No.: US 20050210095 A1), hereinafter “Lutz”, in view of Keshab K. Parhi in NPL: “VLSI for Signal Processing” (diliev.com/home/applications/Library/Electronics/Electronics/CRC%20Press%20-%20Electrical%20Engineering%20Handbook%2C%202nd%20Edition/ch018.pdf), hereinafter “Parhi”.
Regarding Claim 1, Lutz teaches:
Circuitry comprising:
a comparison circuit having a first input configured to receive a first input value, a second input configured to receive a second input value, and an output on which a corresponding comparison value is generated (Fig. 6, e.g., shows logic 510 (comparison circuit) that receives first and second integer data elements A and B (first and second input values); ¶0099, e.g., carry value register 525 stores comparison result from logic 510 (comparison circuit)), wherein the comparison circuit is configured to perform a first computation to generate the comparison value (¶0099, e.g., logic 510 performs comparison (first computation) to generate comparison result); and
an adder circuit having a first input configured to receive the first input value, a second input configured to receive the second input value, a third input configured to receive the comparison value from the output of the comparison circuit, and an output on which an adder output value is generated, wherein the adder circuit is configured to perform a second computation to generate the adder output value based on a sum of the first input value and the comparison value (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result; ¶0102, e.g., adder 535 adds (second computation) two data elements and the comparison result), …
Lutz does not teach:
and wherein a portion of the second computation occurs in parallel with a portion of the first computation.
However, in the same field of endeavor, Parhi teaches “Retiming”, which is the process of removing a delay of a pipeline. Parhi explains “Removal of one delay from all input edges of a node and insertion of one delay to each outgoing edge of the same node is the simplest example of retiming. Unlike pipelining, retiming does not increase the latency of the system.” (Parhi: Page 5 First paragraph).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the pipeline stages in the absolute difference logic as taught by Lutz to remove the delay (registers 515, 520, and 525) in order to reduce latency as taught by Parhi. One would have been motivated to combine these references because both references disclose pipelining in digital circuits, and Parhi enhances the model of Lutz because “Unlike pipelining, retiming does not increase the latency of the system. Retiming can reduce the critical path of the data flow graph.” (Parhi: Page 5 First paragraph). Combination would cause for the comparison operation and the addition to perform computations in parallel due to the removal of the delay (registers 515, 520, 525).
Regarding Claim 2, Lutz in view of Parhi teach:
The circuitry of claim 1, wherein the adder circuit is configured to compute the adder output value based on a sum of the first input value, a version of the second input value different than the second input value, and the comparison value (Lutz: Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Operand B is inverted before being received by the adder (version of the second input value different than the second input value)).
Regarding Claim 3, Lutz in view of Parhi teach:
The circuitry of claim 1, wherein the adder circuit is configured to compute the adder output value based on a sum of the first input value, an inverted version of the second input value, and the comparison value (Lutz: Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Operand B is inverted before being received by the adder).
Regarding Claim 4, Lutz in view of Parhi teach:
The circuitry of claim 1, wherein the second input of the adder circuit is an inverting input configured to invert bits of the second input value (Lutz: Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Operand B is inverted before being received by the adder).
Regarding Claim 7, Lutz in view of Parhi teach:
The circuitry of claim 1, further comprising:
an inverter configured to receive the adder output value (Lutz: Fig. 6, e.g., inverter 540 receives adder output).
Regarding Claim 8, Lutz in view of Parhi teach:
The circuitry of claim 1, further comprising:
a selection circuit having a first input configured to receive the adder output value directly from the output of the adder circuit, a second input configured to receive a version of the adder output value different than the adder output value, and a third input configured to receive the comparison value from the output of the comparison circuit (Lutz: Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector). Multiplexer 545 receives n signal generated by logic 510 (comparison value generated by comparison circuit); ¶0102).
Regarding Claim 9, Lutz in view of Parhi teach:
The circuitry of claim 1, further comprising:
a selection circuit having a first input configured to receive the adder output value directly from the output of the adder circuit, a second input configured to receive an inverted version of the adder output value via an inverter, and a third input configured to receive the comparison value from the output of the comparison circuit (Lutz: Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector). Multiplexer 545 receives n signal generated by logic 510 (comparison value generated by comparison circuit); ¶0102).
Regarding Claim 10, Lutz in view of Parhi teach:
The circuitry of claim 9, wherein the selection circuit has an output on which an absolute value of a difference between the first and second input values is generated (Lutz: ¶0100).
Regarding Claim 11, Lutz teaches:
A method comprising:
computing a sum of a first input value, a version of a second input value different than the second input value, and a comparison value (Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result; ¶0102, e.g., adder 535 adds two data elements and the comparison result);
…
selecting between the sum and a version of the sum different than the sum (Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector) to be selected based on comparison result n; ¶0102).
Lutz does not teach:
during a portion of the sum computation, comparing the first input value to the second input value to obtain the comparison value;
However, in the same field of endeavor, Parhi teaches “Retiming”, which is the process of removing a delay of a pipeline. Parhi explains “Removal of one delay from all input edges of a node and insertion of one delay to each outgoing edge of the same node is the simplest example of retiming. Unlike pipelining, retiming does not increase the latency of the system.” (Parhi: Page 5 First paragraph).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the pipeline stages in the absolute difference logic as taught by Lutz to remove the delay (registers 515, 520, and 525) in order to reduce latency as taught by Parhi. One would have been motivated to combine these references because both references disclose pipelining in digital circuits, and Parhi enhances the model of Lutz because “Unlike pipelining, retiming does not increase the latency of the system. Retiming can reduce the critical path of the data flow graph.” (Parhi: Page 5 First paragraph). Combination would cause for the comparison operation and the addition to perform computations in parallel due to the removal of the delay (registers 515, 520, 525).
Regarding Claim 12, Lutz in view of Parhi teach:
The method of claim 11, wherein comparing the first input value to the second input value comprises determining whether the first input value is greater than or equal to the second input value (Lutz: ¶0099, e.g., Logic 510 determines the largest value of first and second data elements (first and second input values) and outputs comparison result based on which value is largest; Fig. 6).
Regarding Claim 14, Lutz in view of Parhi teach:
The method of claim 11, wherein computing the sum comprises calculating a sum of the first input value, an inverted version of the second input value, and the comparison value (Lutz: Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Data element B is inverted before being received by the adder).
Regarding Claim 15, Lutz in view of Parhi teach:
The method of claim 11, wherein selecting between the sum and a version of the sum different than the sum comprises selecting between the sum and an inverted version of the sum (Lutz: Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector) to be selected based on comparison result n; ¶0102).
Regarding Claim 16, Lutz in view of Parhi teach:
The method of claim 11, wherein selecting between the sum and a version of the sum different than the sum comprises:
selecting the sum upon determining that the comparison value is high (Lutz: Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector) to be selected based on comparison result n; ¶0102); and
selecting a version of the sum different than the sum upon determining that the comparison value is low (Lutz: Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 (selector) to be selected based on comparison result n; ¶0102).
Regarding Claim 17, Lutz teaches:
Absolute difference circuitry comprising:
a comparison logic configured to receive first and second input numbers (Lutz: Fig. 6, e.g., Logic 510 (comparison logic) receives data elements A and B (first and second input numbers)) and to generate a comparison output based on a comparison of the first and second input numbers (Lutz: ¶0099, e.g., Logic 510 determines the largest value of first and second data elements (first and second input values) and outputs comparison result based on which value is largest; Fig. 6);
an adder configured to receive the first and second input numbers and the comparison output and to generate an adder output (Lutz: Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result; ¶0102, e.g., adder 535 adds two data elements and the comparison result), … ; and
a multiplexer configured to receive the adder output, a version of the adder output different than the adder output, and the comparison output (Lutz: Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 to be selected based on comparison result n; ¶0102).
Lutz does not teach:
… wherein the adder is directly connected to the comparison logic;
However, in the same field of endeavor, Parhi teaches “Retiming”, which is the process of removing a delay of a pipeline. Parhi explains “Removal of one delay from all input edges of a node and insertion of one delay to each outgoing edge of the same node is the simplest example of retiming. Unlike pipelining, retiming does not increase the latency of the system.” (Parhi: Page 5 First paragraph).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the pipeline stages in the absolute difference logic as taught by Lutz to remove the delay (registers 515, 520, and 525) in order to reduce latency as taught by Parhi. One would have been motivated to combine these references because both references disclose pipelining in digital circuits, and Parhi enhances the model of Lutz because “Unlike pipelining, retiming does not increase the latency of the system. Retiming can reduce the critical path of the data flow graph.” (Parhi: Page 5 First paragraph). Combination would cause for the logic 510 to be directly connected to the adder 535 due to the removal of the delay (registers 515, 520, 525).
Regarding Claim 18, Lutz in view of Parhi teach:
The absolute difference circuitry of claim 17, wherein the adder is configured to generate the adder output by computing a sum of the first input number, an inverted version of the second input number, and the comparison output (Lutz: Fig. 6, e.g., adder 535 receives inputs A and B (first and second inputs) and receives carry value (third input), and outputs addition result. Data element B is inverted before being received by the adder).
Regarding Claim 19, Lutz in view of Parhi teach:
The absolute difference circuitry of claim 17, wherein the multiplexer is configured to:
receive the adder output, an inverted version of the adder output, and the comparison output; and
output either the adder output or the inverted version of the adder output based on the comparison output (Lutz: Fig. 6, e.g., Adder 535 outputs addition result and inverted addition result to multiplexer 545 to be selected based on comparison result n; ¶0102).
Regarding Claim 20, Lutz in view of Parhi teach:
The absolute difference circuitry of claim 17, wherein the adder is the only adder in the absolute difference circuitry (Lutz: ¶0100).
Claims 5-6, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lutz in view of Parhi, further in view of M. Morris Mano in NPL: “Digital Design Third Edition” (nibmehub.com/opac-service/pdf/read/Digital%20Design-%203rd%20Edition.pdf), hereinafter “Mano”.
Regarding Claim 5, Lutz in view of Parhi teach:
The circuitry of claim 1, wherein the comparison circuit is configured to:
drive the comparison value to a … value upon determining that the first input value is greater than or equal to the second input value (Lutz: ¶0099, e.g., Logic 510 determines the largest value of first and second data elements (first and second input values) and outputs comparison result based on which value is largest; Fig. 6); and
drive the comparison value to [another value] upon determining that the first input value is less than the second input value (Lutz: ¶0099, e.g., Logic 510 determines the largest value of first and second data elements (first and second input values) and outputs comparison result based on which value is largest; Fig. 6).
Lutz in view of Parhi do not teach:
drive the comparison value to a first value upon determining that the first input value is greater than or equal to the second input value; and
drive the comparison value to a second value different than the first value upon determining that the first input value is less than the second input value.
However, in the same field of endeavor, Mano teaches the fundamentals of a magnitude comparator, where it describes comparing two binary values and outputting a binary value depending on the condition. Mano explains “The comparison of two numbers is an operation that determines if one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether A > B, A = B, or A < B.” (Mano: Page 163, Section 5-4 Magnitude Comparator)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the comparator determining whether A > B, A = B, or A < B indicated by a binary variable as taught by Mano with the logic 510 as taught by Lutz in view of Parhi. One would have been motivated to combine these references because both references disclose comparators in digital circuits, and Mano enhances the model of Lutz in view of Parhi by allowing for the logic 510 to accurately indicate if A is larger, equal to, or smaller than B. Combination would cause for either of the conditions to be indicated true (high) or not true (low) by a binary variable as taught by Mano.
Regarding Claim 6, Lutz in view of Parhi teach:
The circuitry of claim 1, wherein the comparison circuit is configured to:
drive the comparison value high … (Lutz: ¶0099, e.g., logic 510 (comparison circuit) can produce a single comparison result (i.e. n=1), hence n would either have to be high or low); and
drive the comparison value low … (Lutz: ¶0099, e.g., logic 510 (comparison circuit) can produce a single comparison result (i.e. n=1), hence n would either have to be high or low).
Lutz in view of Parhi do not teach:
drive the comparison value high upon determining that the first input value is greater than or equal to the second input value; and
drive the comparison value low upon determining that the first input value is less than the second input value.
However, in the same field of endeavor, Mano teaches the fundamentals of a magnitude comparator, where it describes comparing two binary values and outputting a binary value depending on the condition. Mano explains “The comparison of two numbers is an operation that determines if one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether A > B, A = B, or A < B.” (Mano: Page 163, Section 5-4 Magnitude Comparator)
The motivation to combine provided with respect to claim 5 applies equally to claim 6.
Regarding Claim 13, Lutz in view of Parhi teach the method of claim 12. Lutz in view of Parhi do not teach:
wherein comparing the first input value to the second input value further comprises:
asserting the comparison value in response to determining that the first input value is greater than or equal to the second input value; and
deasserting the comparison value in response to determining that the first input value is less than the second input value.
However, in the same field of endeavor, Mano teaches the fundamentals of a magnitude comparator, where it describes comparing two binary values and outputting a binary value depending on the condition. Mano explains “The comparison of two numbers is an operation that determines if one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether A > B, A = B, or A < B.” (Mano: Page 163, Section 5-4 Magnitude Comparator)
The motivation to combine provided with respect to claim 5 applies equally to claim 13.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
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