Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is a non-final First Office Action.
This action is in response to communications filed on 08/10/2022.
Claims 1-19 are pending and have been considered.
Claims 10-18 are interpreted under 112(f). Independent claim 10 recites “interface unit configured to”… Claims 11-18 depend on claim 10 and therefore are also interpreted under 112(f).
Claim(s) 1-3, 6-7, 10-12, 15-16, 19 is/are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Rabinovitch et al, US 20150121138 A1
Claims 4-5, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over of RAB in view of Koh C.-K et al, Synthesis of Clock and Power/Ground Networks, Chapter 13, Electronic Design Automation , pp 751-850, 2009
Claims 8, 17 are rejected under 35 U.S.C. 103 as being unpatentable over of RAB in view of Kansal et al US 20200036402 A1
Claims 9, 18 are rejected under 35 U.S.C. 103 as being unpatentable over of RAB in view of Korchemny et al. US 20210232742 A1
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The application claims priority to the PR China Application CN202110995728.2 filed on 08/27/2021. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). No translation of the application has been provided.
Information Disclosure Statement (IDS)
The information disclosure statement (IDS) submitted on 08/10/2022, 12/23/2022 is/are in compliance with the provisions of 37 CFR 1.97.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “interface unit configured to” in claim 10. The 112(f) interpretation applied to its dependent claims 11-18 as well.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-7, 10-12, 15-16, 19 is/are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Rabinovitch et al, US 20150121138 A1, (“RAB”).
Regarding independent claim(s) 1, 10, 19 RAB discloses:
an interface unit configured to be connected to a host; a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to perform a method for synchronizing the first module and the second module of the logic system design, {RAB: see at least [0063] As shown in FIG. 10, computer 1020 may include a processor(s) 1060 that communicates with a number of peripheral devices via a bus subsystem 1090. These peripheral devices may include user output devices 1030, user input devices 1040, communications interface 1050, and a storage subsystem, such as random access memory (RAM) 1070 and disk drive 1080; [0070] RAM 1070 and disk drive 1080 may include a number of memories including a main random access memory (RAM) for storage of instructions; [0008] the hardware verification system further includes, in part, computer instructions that receive a circuit design and determine the second period based on a propagation delay of a signal path of the circuit design.}
wherein the first module and the second module operate according to a system clock, the first module includes a plurality of sub-modules, the method comprising: { RAB:[0074] Hardware modules or apparatuses described herein include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors, and/or other hardware modules or apparatuses now known or later developed.; [Claim 1] A hardware verification system comprising a plurality of programmable devices and a system clock}
determining, among the plurality of sub-modules, whether a target sub-module generates an event indication; {RAB: FIG. 7, (702)”Receive a circuit design:” (704) “Determine propagation delays of one or more signal paths in the circuit design” } In BRI target sub-module interpreted as the received circuit design, determining whether it generates an event indication interpreted as determine propagation delays.
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in response to determining that the target sub-module generates the event indication, switching a period of the system clock from a first clock period to a second clock period, wherein the first clock period is less than the second clock period; and running the target sub-module according to the second clock period. {{RAB: FIG. 7 (704), (706) “Generate a variable period clock signal from a system clock in accordance with the propagation delays”; [0008] In one embodiment, the variable period clock signal has a first period and a second period greater than the first period. …the hardware verification system further includes, in part, computer instructions that receive a circuit design and determine the second period based on a propagation delay of a signal path of the circuit design. Fig.7 (708) “Apply the variable period clock signal to the design” } In BRI determining that the target sub-module generates the event indication is interpreted as determining propagation delays. Run the module according to signal interpreted as apply the clock to the design.
Regarding claim(s) 2(1), 11(10) RAB discloses the limitations of the parent claim. RAB further discloses:
wherein the logic system design is implemented on an emulator, the emulator comprising a first Field Programmable Gate Array (FPGA) and a second FPGA, the first module runs on the first FPGA, and the second module runs on the second FPGA. { RAB:[0028] FIG. 1 is an exemplary high level block diagram of a hardware emulator or prototype system 102 that can be used to verify, test or debug a circuit design. As illustrated, the hardware emulation/prototype system 102 may include a multitude of programmable processors 104 (e.g., FPGAs) }
Regarding claim(s) 3(1), 12 (10) RAB discloses the limitations of the parent claim. RAB further discloses:
wherein the event indication comprises information indicating a change in an output signal of the target sub-module and information indicating a delay of the target sub-module, and the method further comprises: determining the second clock period according to the delay of the target sub-module. { RAB: [0008], computer instructions that receive a circuit design and determine the second period based on a propagation delay of a signal path of the circuit design. }
Regarding claim(s) 6(1), 15(10) RAB discloses the limitations of the parent claim. RAB further discloses:
in response to elapsing the second clock period, switching the period of the system clock from the second clock period to the first clock period. {).
The variable period clock has a first period that occurs in each N cycles of the system clock and a second period that occurs in each M cycles of the system clock, (RAB: FIG.4 TD2, TD1 in (404)
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}
IN BRI the limitation is interpreted as after ending the period/cycle of the clock, change to another clock.
Regarding claim(s) 7(6), 16(15) RAB discloses the limitations of the parent claim in which also discloses about instructions to the hardware verification system further includes, in part, computer instructions that receive a circuit design and determine the second period based on a propagation delay of a signal path of the circuit design. RAB further discloses:
wherein switching the period of the system clock from the second clock period to the first clock period further comprises: generating a clock generation instruction, to start generation of a rising edge of a clock signal of the system clock { [0032] Generally, building blocks (e.g., logic gates) of a DUT, may be sensitive to positive edge (rising edge), negative edge or both positive and negative edges of a clock signal. Without loss of generality, it is assumed that building blocks of the DUT are sensitive to positive edges of the clock signal.}
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
i. Determining the scope and contents of the prior art.
ii. Ascertaining the differences between the prior art and the claims at issue.
iii. Resolving the level of ordinary skill in the pertinent art.
iv. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims that share substantially similar limitations (even though not verbatim) are grouped and analyzed together; the analysis is done on the claim with most comprehensive limitations. The parenthesis following a claim number indicates the parent claim.
Claims 4 (3), 5(3), 13(12) 14(12) are rejected under 35 U.S.C. 103 as being unpatentable over of RAB in view of Koh C.-K et al, Synthesis of Clock and Power/Ground Networks, Chapter 13, Electronic Design Automation , 2009 pp 751-850 (“KOH”)
Regarding claim(s) 4(3) 13(12) RAB discloses the limitations of the parent claim. RAB does not disclose, however KOH discloses:
wherein the delay of the target sub-module comprises an internal delay of the target sub-module and a transmission delay between the first module and the second module, the second clock period being greater than or equal to a sum of the internal delay of the target sub-module and the transmission delay. { KOH: [753 bottom ]
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} In BRI the claim merely recites an instantiation of the fundamental principle of synchronous design, by which the clock period needs to be larger than the max of path delays (a.k.a. critical path). i.e. max of the sum of delays on the paths including logic delays, propagation delays, setup delays, and any other delay.
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined RAB, directed to reducing the clock of a circuit on emulator to take in consideration to that synchronicity is maintained, and KOH, making that extension of the period of the clock sufficiently large to deal with all the delays on the path. One of ordinary skill in the art would have been motivated to make such a combination in order to maintain a synchronous design (clocked) without timing errors, thus progressing at high speed/frequency, but below the limit that would create timing errors. Accordingly, the claimed subject matter would have been obvious over RAB in view of KOH.
Regarding claim(s) 5(3), 14(12) RAB teaches the limitations of the parent claim. RAB does not teach, however KOH teaches:
wherein a delay of one sub-module of the plurality of sub-modules comprises an internal delay of the one sub-module and a transmission delay between the first module and the second module, the second clock period being greater than or equal to a sum of the internal delay of a sub-module having a longest internal delay among the plurality of sub-modules and the transmission delay. { KOH: [753 bottom ]
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} In BRI the claim merely recites an instantiation of the fundamental principle of synchronous design, by which the clock period needs to be larger than the max of path delays (a.k.a. critical path). i.e. max of the sum of delays on the paths including logic delays, propagation delays, setup delays, etc. The same rationale as for claims 4 and 13. The fact that the period is greater than the longest delay is inherent to synchronous circuits.
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined RAB, directed to reducing the clock of a circuit on emulator to take in consideration to that synchronicity is maintained, and KOH making that extension of the period of the clock sufficiently large to deal with all the delays on the path, respectively longest delay. One of ordinary skill in the art would have been motivated to make such a combination in order to maintain a synchronous design (clocked) without timing errors, thus progressing at high speed/frequency, but below the limit that would create timing errors. Accordingly, the claimed subject matter would have been obvious over RAB in view of KOH.
Claims 8 (1), 17(10) are rejected under 35 U.S.C. 103 as being unpatentable over of RAB in view of Kansal et al US 20200036402 A1 (“KAN”)
Regarding claim(s) 8(1), 17(10) RAB discloses the limitations of the parent claim. RAB fails to teach, however KAN teaches:
wherein switching the period of the system clock from the first clock period to the second clock period further comprises: generating a clock stop instruction according to the event indication, to delay generation of a rising edge of a clock signal of the system clock. { KAN: [0036] control signal control 208 may be either an on/off signal to either delay the clock } In BRI the limitations recites generating a command to stop/delay the clock (which implicitly will delay the rising edge since the clock is stopped/delayed, until the command is overridden).
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined RAB, directed to reducing the clock of a circuit on emulator to take in consideration to that synchronicity is maintained, and KAN clock delaying as a simple method to obtain the needed delay for timing purposes.. One of ordinary skill in the art would have been motivated to make such a combination in order to ensure time constraints needed in emulation when dealing with signal path delays, and stopping/delaying the clock is one of the easiest ways to do it. Accordingly, the claimed subject matter would have been obvious over RAB in view of KAN.
Claims 9 (1), 18(10) are rejected under 35 U.S.C. 103 as being unpatentable over of RAB in view of Korchemny et al. US 20210232742 A1, (“KOR”)
Regarding claim(s) 9(1), 18(10) RAB discloses the limitations of the parent claim. RAB fails to teach, however KOR teaches:
wherein running the target sub-module according to the second clock period comprises: outputting an output signal of the target sub-module in the second clock period. {KOR:[0006] cause the processor to determine a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfigure a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, set a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogram the first and second clocks in accordance with the delay, and detect a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay } Output signal of target circuit interpreted as output of second flip-flop, which runs on second clock.
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined RAB, directed to reducing the clock of a circuit on emulator to take in consideration to that synchronicity is maintained, and KOR clock output in a longer clock period. One of ordinary skill in the art would have been motivated to make such a combination in order to ensure that the signal has enough time to propagate through path delays, and a clock with longer periods is one of the easiest ways to do it. Accordingly, the claimed subject matter would have been obvious over RAB in view of KOR.
Additional References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yamaoka N, US 20090210741 A1, (“YAM”)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADRIAN STOICA whose telephone number is (571) 272-3428. The examiner can normally be reached Monday to Friday, 9 a.m. -5 p.m. PT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ryan Pitaro can be reached on (571) 272-4071. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.S./Examiner, Art Unit 2188
/RYAN F PITARO/Supervisory Patent Examiner, Art Unit 2188